JPH0777972A - Image processor - Google Patents

Abstract

PURPOSE:To use a reducing circuit and a compressing circuit in common and to display a reduced image which is faithful to a read image by using a reduced image halfway in hierarchical encoding for a display image CONSTITUTION:When read information from a reader 1 is compressed by a hierarchical encoding method by using a reducing and encoding means 3 and memories 3 and 6, 7 and recorded on a magnetooptic disk 9, the reduced image obtained halfway in the hierarchical encoding process by the reducing and encoding means 3 is stored in a video RAM 4 and displayed on a display unit 5. On the display unit 5, the reduced image which is faithful to the read image can be displayed and the read quality can acurately be judged, and an image which is read deficiently can easily be found and reread.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus suitable for an image reading apparatus having a display means.

[0002]

2. Description of the Related Art In recent years, a device such as an electronic file device for optically reading a document and processing the read image data has been developed. As a function of these devices, displaying the read image data on a display in real time is one of the important functions for confirming whether or not the reading was performed correctly.

The structure of a conventional electronic file device of this type is shown in FIGS. FIG. 3 shows the configuration of the document reading unit of the electronic file device, and FIG. 4 shows the block configuration of the recording / display unit of the electronic file device. In FIG. 3, the document table 4
The bundle of documents placed on -1 is separated sheet by sheet by separation rollers 4-2 and 4-3 which are reversed, and conveyed by feed rollers 4-4, 5, 6, and 7. During this period, the original is illuminated by the fluorescent lamp 4-8, and an image of one line of the original is formed on the CCD image sensor 4-11 by the mirror 4-9 and the lens 4-10 and converted into an electric signal. It Here, since the original is conveyed perpendicularly to the reading direction of the CCD image sensor 4-11, the original information is stored in the CCD image sensor 4-1 when the original is fed.
Read by 1.

The image signal read from the original is compared with the image information read from the CCD image sensor 4-11 in FIG. 4 by the binarization circuit 5-1 to compare it with a predetermined threshold value, which is "0" (white) or "1". "(Black) binary signal.
Then, the compression circuit 5-2 performs a predetermined data compression process, and the compression result is recorded on the magneto-optical disk 5-3.

On the other hand, the output of the binarization circuit 5-1 is also output to the reduction circuit 5-4 at the same time, where it is subjected to reduction processing and temporarily stored in the video RAM 5-5. Then, this reduced image data is displayed on a display device 5-6 such as a CRT. As a coding method for compression, in recent years, ISO (International Standards Organization) has adopted binary image hierarchical coding (JB
IG) is being standardized. FIG. 5 shows the flow of processing of this encoding system, and FIG.
Is shown in the block diagram of. In this description, the reading resolution is 400 dpi. In these figures, first, the binarized 400d which is the output of the binarization circuit.
The image data 7-A of pi is reduced to 200 dpi by the reduction / encoding means 7-1 and stored in the memory A7-2. At the same time, the original image of 400 dpi and 200 dpi
The difference between the reduced images is encoded by the reducing / encoding means 7-1 and output as compressed data 7-8.

Next, the 200 dpi image stored in the memory A7-2 by the above-mentioned processing is reduced / encoded by the means 7-.
It is reduced to 100 dpi by 1 and stored in the memory B7-3. Similarly, a reduced image of 200 dpi and 100 dpi
The reduced image difference is encoded by the reduction / encoding means 7-1 and output as compressed data 7-8. This is repeated as shown in FIG. 6 to reduce the data until it becomes sufficiently small data, and these compressed data are recorded and used for communication. The reduction method used for this is PRES (Progressiv).
e Reduction Scheme), which is more faithful to the original picture.

[0007]

However, in the conventional device of this type, the display density of the display unit 5-6 is generally lower than the reading density, so that the reading density can be displayed once. No, I had to display a part. Further, when an original is to be displayed on the entire display surface, it is necessary to reduce the image data. However, since it is necessary to display the image data in real time, a complicated reduction method increases the cost. I had no choice but to reduce it by the method. Therefore, the reduction method faithful to the original image is not used, and the confirmation is insufficient only by the display of the display means.

[0008]

The present invention has been made for the purpose of solving the above-mentioned problems, and has the following structure as one means for solving the above-mentioned problems. That is, the image processing apparatus comprises display control means for displaying the input image information on the display means, and compression means for compressing the input image information according to a hierarchical encoding method, wherein the display control means is a hierarchy of the compression means. A reduced image obtained during the dynamic encoding process is displayed on the display means.

Further, for example, the compression means includes reduced image storage means for storing reduced images of hierarchical coding, and the reduced image storage means (for example, video RAM) displays the reduced images stored on the display means. Further, the compression means includes code data storage means for reducing the hierarchical coding,
In the hierarchical encoding process, the code data storage means and the reduced image storage means are switched and used.

[0010]

In the above structure, a reduced image in the middle of hierarchical encoding is used as a display image, so that a reduced image faithful to the read image can be displayed, and the reduction circuit can be shared with the compression circuit. The cost can be reduced.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described in detail below with reference to the drawings. FIG. 1 shows an embodiment according to the present invention. In FIG. 1, reference numeral 1 denotes a reading device for reading a document image, which can be configured, for example, as shown in FIG. Reference numeral 2 is a binarization circuit that compares the image information read by the reading device 1 with a predetermined threshold value and converts it into a binary signal of "0" (white) and "1" (black).

Numeral 3 is 1/2 the input image from the binarization circuit 3.
Reduction encoding means for reducing and compressing the difference between the input image and the reduced image, and compressing, 4 is a video RAM for storing display data to be displayed on a display such as a CRT, and the first reduced image When the is stored, this reduced image is displayed on the display unit 5. Also, a control unit (CPU) not shown
Also, the display information can be written in from. Reference numeral 5 denotes a display such as a CRT, which is a video RAM under the control of a control unit (CPU) (not shown) or the display 5 itself.
The stored contents of 4 are displayed as they are.

6 is a memory A for storing the second, 4 ... 2n (n is an integer) reduced image, and 7 is a third, 5 ... 2n + 1 memory.
(N is an integer) A memory B for storing the reduced image for the second time, 8 is a changeover switch for switching the memory for storing the reduced image between the video RAM and the memory B7, and 9 is compressed / encoded by the reducing / encoding means 3. It is a magneto-optical disk that stores compressed data.

Further, 11 is the binarized image data from the binarization circuit 2, and 12 is the compressed data which has been compressed / encoded by the reduction / encoding means 3. The operation of this embodiment having the above configuration will be described below. In this embodiment, the same compression encoding method as the compression encoding method shown in FIGS. 5 and 6 described above is adopted. In the following description, a case where the reading resolution of the reading device 1 is 400 dpi will be described as an example. However, this resolution is not limited to the above example, and the same result can be achieved by repeating the following encoding method at any resolution.

The changeover switch 8 is initially controlled by a control unit (not shown) so that the reduction / encoding means 3 and the video RAM 4 are connected to each other as shown in FIG. This allows
The binarized read signal from the binarization circuit 2 is reduced from 400 dpi to 200 dpi by the reduction / encoding means 3 and stored in the video RAM 4. At the same time, the reduction / encoding means encodes the difference between the images of 400 dpi and 200 dpi, and outputs the compressed data as magneto-optical disk 9 as compressed data.
Is output to. The display 5 displays the stored contents of the video RAM 4 by a known display control method.
The reduced read data is displayed in dpi.

Next, 200 stored in the video RAM 4
Similarly, the image of dpi is 100d by the reduction / encoding means 3.
It is reduced to a pi image and stored in the memory A6. At the same time, the reducing / encoding means are 200 dpi and 100 d.
The image difference of pi is encoded and output to the magneto-optical disk 9 as compressed data. Similarly, the image of 100 dpi stored in the memory A6 is similarly reduced by the reducing / encoding means 3 to the image of 50 dpi. However, since the image of 200 dpi is stored in the video RAM 4 and used for display, the image of 50 dpi cannot be stored in the video RAM 4. Therefore, in the present embodiment, the changeover switch 8 is switched to connect the reduction / encoding means 3 and the memory B7, and a 50 dpi image is stored in the memory B7. At the same time, the reduction / encoding means are 100 dpi and 50 dpi.
The image difference of i is encoded and output to the magneto-optical disk 9 as compressed data.

In this case, since the image stored in the memory B7 is an image obtained by reducing the read image to 1/8, the capacity of 1/64 of the read image is required. After that, the reduction / encoding process is sequentially performed by the hierarchical encoding method shown in FIG.
6 and the memory B7 are alternately recorded, and the compressed data 12 is sequentially output.

The compression encoding method described above is, for example, "Yoshida, Endo et al .:" Reduction method in binary image sequential reproduction encoding method "(PRES)", PCSJ30 (1990,
10) ”, etc., can be used for easier understanding. As described above, according to the present embodiment, by using the reduced image in the middle of the hierarchical encoding as the display image, the reduction circuit for display can be shared with the compression circuit of the read information, and with a simple configuration, Moreover, it is possible to display a reduced image that is faithful to the read image. Therefore, the cost can be reduced in total.

[Second Embodiment] The first embodiment described above
In the embodiment, the memory B7 and the changeover switch 8 are provided together with the video RAM 4. However, the present invention is not limited to the above examples. For example, when the video RAM 4 has a large storage capacity and the area not used for display is equal to or larger than the memory capacity required by the memory B7, the changeover switch 8 switches between the memories 4 and 7 to store the data. Instead of letting the video RA
A compressed data storage area to be stored in the memory B7 may be allocated to an empty area in M4, and the storage location of the reduced data by the reduction / encoding means 3 may be changed and stored. By controlling in this way, the configuration can be further simplified and the reliability can be improved.

Further, a memory having a storage capacity equal to or larger than two areas, that is, an area used as a video RAM and an area for storing a reduced image as the memory B may be provided in advance. Further, in the above description, an example has been described in which the 1/2 reduced image is first stored in the video RAM 4 and the 1/4 reduced image is stored in the memory A6. However, the present invention is not limited to the above examples, and
The reduced image of / 2 may be stored in the memory A6 first, and the reduced image of 1/4 may be stored in the video RAM 4.

By controlling in this manner, it is possible to display a 1/4 reduced image on the display unit 5. [Third Embodiment] Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 2 is a diagram showing the configuration of the third embodiment according to the present invention. The same components as those in FIG. 1 described above are designated by the same reference numerals and detailed description thereof will be omitted.

In FIG. 2, the memory A6 has the second, fourth and fourth memory A6s.
6, ... 2n (n is an integer) times reduced data is stored.
The memory B7 stores the first, third, fifth ... 2n-1 (n is an integer) reduced data. The video RAM 4 can be written by a control unit (CPU) (not shown)
In the embodiment, the display information of the display 5 is stored under the control of the DMA control circuit 21 described later.

Reference numeral 21 is a direct memory access (DMA) for the contents of the memory A6 or memory B7 to the video RAM4.
A DMA control circuit for transferring data by means of the memory B, a memory B changeover switch 22 for connecting the memory B7 to the reducing / encoding means 3 or the DMA control circuit 21, and a reference numeral 23 for controlling the memory A6 by the reducing / encoding means 3 and the DMA control. Circuit 21
It is a memory A changeover switch for changing over which one of them is connected.

The operation control of the third embodiment having the above configuration will be described below. In the third embodiment, if the memory B changeover switch 22 and the memory A changeover switch 23 are connected to the reduction / encoding means 3 side, the normal hierarchical encoding shown in, for example, FIG. 5 described above is performed. In the above encoding process, when read data reduced to the optimum size to be displayed on the display unit 5 exists in any of the memories, it is connected to the memory in which the reduced data is stored. When the reduction / encoding means 3 is not accessing the memory, the switch is used to reduce / encode the switch 3.
The side is switched to the DMA control circuit 21 side. Then, the reduced image is transferred from the target memory to the video RAM 4 by DMA.
Transfer to. Then, after the DMA transfer is completed, the switch may be connected again to the reduction / encoding means side. By controlling in this way, it is possible to display any reduced size image data on the display unit 5.

For example, the image read by the reading device 1 is 400 dpi, and the display device 5 displays 200 dpi.
When it is desired to display the reduced image of, the reduction / encoding means 3 switches the memory B changeover switch 22 to the DMA control circuit 21 side at the time when the reduced / encoding means 3 generates the reduced image of 200 dpi and stores it in the memory B7, and the video is recorded from the memory B7 by DMA. If the reduced image is transferred to the RAM 4, the display 5 displays 20
An image of 0 dpi can be displayed. And this D
After the MA transfer is completed, the reducing / encoding means 3 and the memory B7 are again used.
Connect with and.

In the above description, an example in which the switch with the DMA control circuit 21 is switched by using a switch has been described for ease of description, but the present invention is not limited to this method and the memory A6 and the memory are used. B7, the DMA control circuit 21 is connected by a common bus, and when the reduction / encoding means 3 generates a desired reduced image and stores it in the memory, the DMA control circuit 21 stores the predetermined image storage area storage data in the memory. Is written in a predetermined area of the video RAM 4, and thereafter, CP (not shown) is controlled by known bus control.
The U or each memory may be configured to perform the DMA transfer at an empty timing when the bus is not used. With this configuration, a predetermined reduced image can be stored in the video RAM 4 without disturbing other controls.

As described above, according to the third embodiment, it is possible to display image data of any reduced size on the display device 5. The present invention may be applied to a system including a plurality of devices or an apparatus including one device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

Further, although the above description has been made by exemplifying the case where it is applied to the electronic file device, the present invention is not limited to the above device, and a facsimile device and other arbitrary compression encoding processing are performed. Of course, it can be applied to the device.

[0029]

As described above, according to the present invention, when the read image is reduced and displayed on the display, the reduced image in the middle of the hierarchical encoding can be used as the reduced image for display. There is an effect that a reduced image faithful to the original image can be obtained and the cost can be reduced without adding an additional reduction circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment according to the present invention.

FIG. 2 is a block diagram showing a configuration of a third exemplary embodiment according to the present invention.

FIG. 3 is a diagram showing a configuration of a document reading unit of the electronic file device.

FIG. 4 is a diagram showing a block configuration of a recording / display unit of a conventional electronic file device.

[Fig. 5] Fig. 5 is a diagram for describing a flow of a hierarchical encoding process.

FIG. 6 is a diagram showing a configuration of a part that achieves a hierarchical encoding process.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Reader 2,5-1 Binarization circuit 3,7-1 Reduction / encoding means 4,5-5 Video RAM 5 Display 6,7-2 Memory A 7,7-3 Memory B 8,22, 23 Changeover switch 9,5-3 Magneto-optical disk 11 Binary image data 12 Compressed data 21 DMA control circuit 4-1 Original platen 4-2, 4-3 Separation roller 4-4 to 4-7 Feed roller 4-8 Fluorescent lamp 4-9 Mirror 4-10 Lens 4-11 CCD image sensor 5-2 Compression circuit 5-4 Reduction circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04N 1/415

Claims (5)

[Claims] 1. An image processing apparatus comprising: display control means for displaying input image information on a display means; and compression means for compressing the input image information according to a hierarchical encoding method, wherein the display control means comprises: An image processing apparatus, wherein a reduced image obtained during the hierarchical encoding process by the compression unit is displayed on the display unit. 2. The compression means includes reduced image storage means for storing a reduced image of hierarchical coding, and the reduced image storage means stores the reduced image on a display means. 1. The image processing device according to 1. 3. The image processing apparatus according to claim 2, wherein the reduced image storage means is a video RAM. 4. The compression means includes code data storage means for reducing hierarchical coding, and the code data storage means and the reduced image storage means are switched and used in the hierarchical coding processing. The image processing apparatus according to claim 2 or 3. 5. The compression means is characterized in that the reduced image subjected to the hierarchical coding processing is transferred to and stored in the reduced image storage means so that it can be accessed from other than the compression means, and the reduced image can be displayed on the display means. The image processing apparatus according to claim 4.