JPH0777333B2 - Limiter circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a limiter circuit for extracting a signal amplitude of an AC input with a specific voltage width.

[Conventional technology]

In signal processing in a recording / reproducing system, frequency noise carried on a video signal is erased by, for example, an antiphase noise canceller.

The high-frequency antiphase noise canceller is configured as shown in FIG. 3, and as shown in D of FIG. 4, the input signal V _IN such as a video signal on which high frequency noise N is _{added is transferred} to the capacitor 2
As shown in E of FIG. 4, only the high frequency noise N is extracted and amplified by the amplifier 4, then the limiter circuit 6 limits the amplitude, and the attenuator 8 attenuates it. In addition to 10, the high frequency noise N is eliminated from the input signal V _IN, and the output signal V _OUT as shown in F of FIG. 4 is taken out. In this case, V _S is a synchronizing signal and V _V is a signal representing an image. Therefore, in such a high-frequency anti-phase noise canceller, it is necessary that the limiter circuit 6 can adjust the level of the high-frequency noise N extracted from the input signal V _IN as needed in order to perform efficient noise cancellation. Is.

By the way, the conventional limiter circuit 6, for example, as shown in FIG. 5, inputs an input signal V _IN to a differential amplifier including transistors 12, 14, resistors 16, 18, 20 and constant current sources 22, 24. The limiter level is determined by the forward drop voltage V _{F of the} diodes 26 and 28 (or the base-emitter voltage V _BE when the transistors on the IC are used). , For example, the peak-to-peak voltage is fixed at about 0.7V.

[Problems to be solved by the invention]

When such a limiter circuit 6 is used, since the limiter level is fixed, the amplification gain of the amplifier 4 must be set high especially for a small signal, and such a limiter circuit 6 has a high frequency range. It is not suitable for the anti-phase noise canceller.

In order to adjust the limiter level in the limiter circuit 6, an attached circuit using a variable resistor or the like is required,
When the limiter circuit 6 is composed of IC, the number of terminals increases,
The circuit configuration becomes complicated. Further, such a limiter circuit 6 is unstable because it has temperature characteristics at the limiter level.

Therefore, the present invention is intended to provide a limiter circuit which can set an arbitrary limiter level, can be adjusted to an arbitrary level, and can obtain a stable limiter output having no temperature characteristic.

[Means for solving problems]

The limiter circuit of the present invention, as illustrated in FIG.
A midpoint voltage setting circuit (60) that generates a midpoint voltage that sets the midpoint level of the input signal to be subjected to amplitude limitation, and an upper limiter based on the midpoint voltage generated by the midpoint voltage setting circuit. A limiter level setting circuit (50) for generating a limiter level and a lower limiter level, and a current mirror circuit (transistor 40 and diode 42) as an active load in a differential pair composed of first and second transistors (34, 36). ,
A first amplifier (31) for amplifying the input signal by setting the midpoint voltage from the midpoint voltage setting circuit to the base of the first transistor together with the input signal; and third and fourth transistors ( A differential pair of transistors 44, 46), wherein the input signal is applied to the base side of the third transistor through the first amplifier, and the upper limiter level is set at the base of the fourth transistor. A second amplifier (3 that extracts the amplitude portion of the input signal exceeding the upper limiter level of the input signal).
2) and a differential pair consisting of fifth and sixth transistors (52, 54), the input signal being applied to the base side of the fifth transistor through the first amplifier, The lower limiter level is set on the base of a transistor, and a third amplifier (33) for extracting an amplitude part of the input signal below the lower limiter level is provided. [Operation] In the limiter circuit of the present invention, the first amplifier 31 functions as a buffer circuit that allows the input signal V _IN to pass therethrough, and the amplitude portion of the output signal V _OUT that exceeds the upper limit side limiter level of the upper limit side level of the output signal V _OUT is output to the second amplifier. Except for 32, the amplitude part of the lower limit level of the output signal V _OUT of the first amplifier 31 which is lower than the lower limit limiter level is included in the third amplifier 33.
By removing with, it is possible to extract an AC signal having an amplitude determined by the upper limit side and lower limit side limiter level,
Moreover, the lower and upper limiter levels V _L and V _H are
Since it is set as the bias input of the second or third amplifier 32, 33, it can be adjusted by adjusting the bias input, and the desired limiter level can be adjusted by the adjustment.
V _LH is set, and the output signal whose amplitude is limited by the limiter level V _LH is taken out.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the limiter circuit of the present invention.

Input signal V such as video signal applied to input terminal 30
_{The IN} is added to the first amplifier 31 and amplified, and then the second
Amplifier 32 and a third amplifier 33 in addition to the amplifier
The amplitude is limited by the upper limiter level V _H set to 32 and the lower limiter level V _LH set by the lower limiter level V _L set to the amplifier 33.

The amplifier 31 includes a differential amplifier including a differential pair including first and second transistors 34 and 36 and a current mirror circuit including a transistor 40 and a diode 42 as an active load in a differential amplifier including an inverting input. An all-feedback amplifier is configured by commonly connecting the base and collector of the side transistor 36, and an output terminal 43 for extracting the limiter output V _OUT is provided.

The amplifier 32 is composed of a differential pair consisting of a third and a fourth transistor 44 and 46 and a differential amplifier consisting of a constant current source 48, and the base and collector of the transistor 44 on the non-inverting input side are the base of the transistor 36. The upper limiter level V _H is set as a bias input from the limiter level setting circuit 50 to the base of the transistor 46 which is shared with the collector and is on the inverting input side thereof.

The amplifier 33 is composed of a differential pair composed of the fifth and sixth transistors 52 and 54 and a differential amplifier composed of a constant current source 56, and the base of the transistor 52 on the non-inverting input side is the base of the transistor 36. Even shared with collectors,
The lower limiter level V _L is set as a bias input from the limiter level setting circuit 50 to the base of the transistor 54 on the inverting input side. The collector of the transistor 52 has the same power supply terminal 58 as the collector of the transistor 46.
Is connected to the power supply line to which a positive voltage Vcc is applied, the collector of the transistor 54 is connected to the base of the transistor 40, and the operating current of the transistor 54 is supplied from the diode 42.

Then, in these amplifiers 31, 32, 33, the respective operating currents are set by the constant currents I ₁ , I ₂ , I ₃ of the constant current sources 38, 48, 56, and the constant currents I ₁ , I ₂ , I The relationship of ₃ is I ₁ <I ₂ , I ₁ <I ₃
By setting, for example, 2I ₁ = I ₂ and 2I ₁ = I ₃ , the collector potential of the transistor 36 can be clamped to the lower limit side limiter level V _L and the upper limit side limiter level V _H.

Next, the limiter level setting circuit 50 for setting the lower limit side limiter level V _L and the upper limit side limiter level V _H as bias inputs to the amplifiers 32 and 33 is a midpoint voltage setting circuit.
An upper limit side limiter level V _H and a lower limit side limiter level V _L having the same width are set on the upper and lower sides of the center point voltage V _M set by 60 as the center. That is, the limiter level setting circuit 50 is configured such that the bases of the transistors 62 and 64 of the differential amplifier circuit including the transistors 62 and 64, the resistor 66, and the constant current sources 68, 70, 72, and 74 are connected to the bases of the resistors 76 and 78 to generate voltage. A specific voltage is applied as a bias input from the source 80, and a variable resistance is applied to the voltage control terminal 82 provided at the base of the transistor 64.
It is a connection of 84. In addition, the midpoint voltage setting circuit 60
Is composed of a constant voltage circuit consisting of a transistor 86 and resistors 88, 90, 92, 94. When the current values of the constant current sources 68, 70, 72, 74 are aligned, the midpoint voltage is applied to the emitter side of the transistor 86.
V _M is obtained. This midpoint voltage V _M is applied to the transistors 62 and 64.
It is added through resistors 96 and 98 to the collector side of.

By the way, the lower limiter level V _L is the current flowing through the resistor 96 due to the difference between the collector currents of the constant current source 68 and the transistor 62.
It is set by the product of I _A and the resistance value R ₉₆ of the resistor ₉₆ (= I _A · R ₉₆ ), and the upper limiter level V _H is set to the resistor 98 by the difference between the collector currents of the constant current source 70 and the transistor 64. It is set by the product of the current I _B flowing and the resistance value R ₉₈ of the resistor ₉₈ (= I _B · R ₉₈ ), but the current I _A , I _B flowing through each resistor 96, 98 can be changed by the value of the variable resistor 84. Therefore, the lower limit side limiter level _VL and the upper limit side limiter level _VH are set according to the resistance value of the variable resistor 84, and the limiter level _VLH is determined.

Further, the midpoint voltage V _M set by the midpoint voltage setting circuit 60 is
It is applied to the base of the transistor 34 on the non-inverting input side of the amplifier 31 via a resistor 97 to set the midpoint level of the amplitude of the input signal V _IN .

Therefore, when the input signal V _IN is applied to the input terminal 30 as shown in A of FIG. 2, the limiter level setting circuit 50 causes the amplifier 33 to set the lower limiter level.
Assuming that the upper limiter level V _H1 is set to L _L1 and the amplifier 32, as shown in B of FIG.
Removes the amplitude part of the signal from the amplifier 31 that exceeds the upper limit side limit level V _H1, and removes the amplitude part that falls below the lower limit side limiter level V _L1 at the amplifier 33, so that the amplitude limiter level V _LH1 is applied. _Assuming that the output signal V _OUT1 thus generated is taken out from the output terminal 43 and the lower limit side limiter level V _L2 and the upper limit side limiter level V _H2 are set by the limiter level setting circuit 50,
As shown in C of the figure, the output signal V _OUT2 whose amplitude is limited by the limiter level V _LH2 is taken out from the output terminal 43.

In this way, the amplitude of the input signal V _IN can be limited by the limiter level V _LH that is arbitrarily set around the midpoint level V _M , and in particular, the limiter level V L can be adjusted according to the signal amplitude of the input signal V _{IN. Since LH} can be set, unlike the conventional circuit, it is not necessary to set the gain of the preceding amplifier in consideration of the signal amplitude, and the amplitude can be limited even for a small amplitude signal.

Moreover, the limiter level L _LH can be set independently without changing the gain of the amplifier, and can be set as a value having no temperature characteristic by the limiter level setting circuit 50, so that it is stable and is not affected by the temperature characteristic. The limiter output is obtained.

Although the limiter level V _LH necessary for the amplifiers 32 and 33 is set by using the limiter level setting circuit 50 in the above-described embodiment, the power supply is replaced by the limiter level V _LH set by the limiter level setting circuit 50. By dividing the voltage Vcc by a resistor divider circuit, the upper limit side limiter level V _H is added to the base of the transistor 46, the lower limit side limiter level V _L is added to the base of the transistor 54, and the limiter level V _LH is set between the bases. May be. Further, in this case, when the white clip level is V _H and the dark clip level is V _L , it can be used as a white / dark clip circuit.

〔The invention's effect〕

As described above, according to the present invention, the limiter level can be set arbitrarily, a limiter output having no stable temperature characteristic can be obtained, and it is necessary regardless of the magnitude of the large amplitude to the small amplitude. It is possible to limit the amplitude.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a limiter circuit of the present invention, FIG. 2 is a diagram showing an input signal and its output signal to the limiter circuit shown in FIG. 1, and FIG. 3 is a high frequency negative phase noise canceller. FIG. 4 is a block diagram showing the input / output waveforms of the high frequency anti-phase noise canceller shown in FIG. 3, and FIG. 5 is a circuit diagram showing a conventional limiter circuit. 31 ... First amplifier 32 ... Second amplifier 33 ... Third amplifier 34 ... First transistor 36 ... Second transistor 40 ... Transistor (current mirror circuit) 42 ... Diode (current mirror circuit) 44 ... Third Transistor 46 ... Fourth transistor 50 ... Limiter level setting circuit 52 ... Fifth transistor 54 ... Sixth transistor 60 ... Midpoint voltage setting circuit

Claims (1)

[Claims] 1. A midpoint voltage setting circuit for generating a midpoint voltage for setting a midpoint level of an input signal to be subjected to amplitude limitation, and an upper limit based on the midpoint voltage generated by the midpoint voltage setting circuit. Limiter level setting circuit for generating a side limiter level and a lower limit side limiter level, and a current mirror circuit as an active load in a differential pair composed of first and second transistors, and the base of the first transistor together with the input signal. A first amplifier which sets the midpoint voltage from the midpoint voltage setting circuit to amplify the input signal; and a differential pair including third and fourth transistors, the base side of the third transistor Is applied with the input signal through the first amplifier, the base of the fourth transistor is set to the upper limiter level, and the upper limit of the input signal is set to the upper limiter level. A second amplifier which takes out except for an amplitude portion exceeding the miter level and a differential pair composed of fifth and sixth transistors are provided, and the input signal passes through the first amplifier to the base side of the fifth transistor. In addition, a third amplifier, in which the lower limit side limiter level is set at the base of the sixth transistor, and a third amplifier which extracts the amplitude part of the input signal below the lower limit side limiter level is taken out, Limiter circuit to do.