JPH0775120B2 - Sample-hold circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a high-speed sample-hold circuit, and more particularly to improvement of hold characteristics.

(Prior Art) One type of sample hold circuit is configured to sample a signal under measurement with a diode bridge and hold the sampled signal under measurement in a hold capacitor.

FIG. 5 is a circuit diagram showing an example of such a conventional sample and hold circuit. In FIG. 5, D _{1 to} D ₄ are diodes that form a diode bridge. CC ₁ , CC ₂
It is a constant current source, one end of the constant current source CC ₁ is connected to the connection point of the anode of the diode D _{1 and} the anode of D ₃ , and one end of the constant current source CC ₂ is the cathode of the diode D _{2 and} the cathode of D ₄ . It is connected to the connection point with. L is a signal line through which the signal under measurement is transmitted, and is connected to a connection point between the cathode of the diode D ₁ and the anode of D ₂ . C _S is a hold capacitor, one end of which is connected to the connection point between the cathode of the diode D ₃ and the anode of D ₄ , and the other end is connected to the common potential point. V _P1 is a positive pulse generator, one end of which is connected to a common potential point via a bias power supply −V _B connected in the reverse direction, and the other end of which is a diode D ₅ connected in the reverse direction.
It is connected to the connection point between the diode bridge and the constant current source CC ₁ via. V _P2 is a pulse generator of negative polarity, one end of which is connected to a common potential point via a bias power supply + V _B connected in the forward direction, and the other end of which is a diode connected via a diode D ₆ connected in the forward direction. Bridge and constant current source CC ₂
It is connected to the connection point with.

In such a configuration, when sampling the measured signal Vx of the signal line L, the bias power supplies −V _B , + V _B
By superimposing the positive and negative output pulse signals of the pulse generators V _P1 and V _P2 on the respective outputs, the diodes D ₅ and D ₆ are turned off and the diode bridge is turned on. As a result, the potential of the signal under measurement Vx of the signal line L at that time is held in the hold capacitor C _S.

FIG. 6 shows a drive pulse applied to the diode bridge.
FIG. 7 is a waveform diagram of V _P1 and V _P2 . In FIG. 6, time T ₄ represents the time when the driving pulses V _P1 and V _P2 are sufficiently larger than the bias voltages −V _B and + V _{B, and} only the diode bridge composed of the diodes D _{1 to} D ₄ is turned on. There is. However, when the potential of the signal line L is near OV, time T ₄ has elapsed after the driving pulse V
_When the amplitudes of _P1 and V _P2 gradually decrease and the absolute value from then onwards falls below the bias voltage −V _B , + V _B , the time T _{6 for} turning on all the diodes D _{1 to} D ₆ occurs. . This time T ₆ is not a moment, but has a predetermined time width due to the characteristics of the diode. That is, these diodes D ₁ to D _6, since the terminal voltage V _F, as shown in FIG. 7 is turned on within a certain range, the driving pulse V _P1, diode D ₁ with a change in V _P2 to D V _{F of 4} becomes smaller D ₅ , D ₆
As described above, all the diodes D _{1 to} D ₆ are turned on during the constant time T ₆ in which V _F increases.

Further, in such a configuration, the bias voltage −V _B , + V
The absolute value of _{B and} the absolute values of drive pulses V _P1 and V _P2 are equal,
The hold capacitor C _S which corresponds to the diode bridge load is assumed not connected, the voltage V _d at the output point of the diode bridge at time T ₄ becomes Vx as shown in FIG. 8.

Incidentally, in T ₆ such time, when the time constant represented by the product of the on resistance and the hold capacitor C _S when viewed drive pulse generator side from the hold capacitor C _S and T _N, T _N ≦ T _In the case of ₆ , the electric charge charged in the hold capacitor C _S escapes to the drive pulse generator side, and the voltage V _CS of the hold capacitor C _S becomes as shown in Fig. 9, and the peak of V _d Only the voltage smaller than the value can be held.

(Problems to be solved by the invention) In order to prevent such escape of charges, a hold capacitor is provided.
If the capacitance of C _S is increased and the time constant T _N is increased, the rate of loss of charge decreases, but on the other hand, the hold capacitor C _{S is connected} to the signal line L within the time T ₄ when the diode bridge is on. The electric potential Vx cannot be held sufficiently.
This is because when the _ON resistance of the diode at time T ₄ is turned _ON , R _ON · C _S > T ₄ .

Further, when the time T ₄ is increased, the measured signal Vx of high frequency transmitted on the signal line L cannot be sampled.

The present invention focuses on such a point, and an object thereof is to provide a sample hold circuit capable of stably sampling a high speed signal.

(Means for Solving Problems) A sample-hold circuit of the present invention is a sample-hold circuit configured to sample a signal under measurement with a diode bridge and hold the sampled signal under measurement in a hold capacitor. Inductance is connected in series between the diode bridge and the hold capacitor, and the half cycle of the resonance circuit formed by these hold capacitor and inductance is set to be equal to or slightly longer than the on time of the diode bridge. Is characterized by.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and the same parts as those in FIG. 5 are designated by the same reference numerals. In FIG. 1, Lr is an inductance, which is connected in series between the diode bridge and the hold capacitor C _S. Here, the half cycle of the resonance circuit composed of the hold capacitor C _S and the inductance Lr is set to about T ₄ + 2T ₆ .

With this configuration, the hold capacitor C _S after the diode bridge is completely turned off.
The charged voltage V _CS becomes larger than the peak value of V _d as shown in FIG.

FIG. 3 is an equivalent circuit diagram of a main part of FIG.

In FIG. 3, if the switch S is kept on from an arbitrary point in time, the voltage V ₁ and the current I are as shown by the solid line in FIG. However, if the resonance frequency of the resonance circuit composed of the inductance L ₁ and the capacitor C ₁ is f ₁ , then γ << 2πf ₁ L ₁ . On the other hand, switch S is half of this resonance circuit.
It is assumed that the period, that is, 1 / (2f ₁ ) is turned on and then turned off. The current flowing through the inductance L ₁ of the case just charges held in the capacitor C ₁ by turning off the switch S so has become zero would be directly held, the voltage V ₁ of the capacitor C ₁ is Fourth
As shown by the broken line in the figure, a constant value of approximately 2V ₀ will be held.

(Effects of the Invention) As described above, according to the present invention, it is possible to realize a sample hold circuit capable of stably sampling a high-speed signal with a relatively simple configuration, and the practical effect is great.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a waveform diagram for explaining the operation of the figure, FIG. 3 is an equivalent circuit diagram of the main part of FIG. 1, FIG. 4 is a waveform diagram for explaining the operation of FIG. 3, and FIG. 6 is a waveform diagram for explaining the operation of FIG. 5, and FIG. 9 is a characteristic diagram of a diode. D _{1 to} D ₆ …… Diode, C _S …… Hold capacitor, L _r
...... Inductance.

Claims (1)

[Claims] 1. A sample-hold circuit configured to sample a signal under measurement with a diode bridge and hold the sampled signal under measurement with a hold capacitor, wherein an inductance is connected in series between the diode bridge and the hold capacitor. A sample and hold circuit that is connected and set to the same or slightly longer than the on-time of the diode bridge of 1/2 cycle of the resonance circuit formed by these hold capacitors and inductance.