JPH0774325A - Semiconductor storage device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the reliability of a DRAM. CONSTITUTION:An impurity region 6b, which becomes the source/ drain region of a transfer gate transistor 3b, is formed on the main surface of a semiconductor substrate. The first layer insulating film 10 is formed on the main surface of the semiconductor substrate 1. On the first layer insulating film 10, a contact hole 10a is provided on the impurity region 6b. A plug 11 is formed in the above-mentioned contact hole 10a. A barrier layer 13 is formed on the upper surface of the plug 11. A capacitor lower electrode 14 is formed on the barrier layer 13 and the first layer insulating film 10. A capacitor dielectric film 15 and a capacitor upper electrode 16 are formed covering the above- mentioned capacitor lower electrode 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a DRAM (Dynamic Random).
The present invention relates to a structure of a plug for electrically connecting a transfer gate transistor and a capacitor in an access memory) and a method of manufacturing a DRAM having such a plug.

[0002]

2. Description of the Related Art Conventionally, a DRAM has been known as a semiconductor memory device capable of randomly inputting / outputting stored information. Generally, a DRAM has a memory cell array section which is a storage area for accumulating a large amount of stored information, and a peripheral circuit section required for input / output with the outside.

FIG. 36 is a block diagram showing a structure of a general DRAM. Referring to FIG. 36, DRAM 150
Is a memory cell array 151 for storing storage information.
A row-and-column address buffer 152 for externally receiving an address signal for selecting a memory cell forming a unit memory circuit, and a row decoder 153 and a column for designating a memory cell by decoding the address signal. A decoder 154, a sense refresh amplifier 155 for amplifying and reading a signal stored in a designated memory cell, a data-in buffer 156 and a data-out buffer 157 for data input / output, and a clock signal. And a clock generator 158 for

In a memory cell array 151 occupying a large area on a semiconductor chip, a plurality of memory cells for accumulating unit storage information are arranged in a matrix.
Generally, one memory cell is connected to one MOS (Metal Ox).
ide Semiconductor) transistor and one capacitor connected to the transistor. Such a memory cell is called a one-transistor / one-capacitor type memory cell. Since this type of memory cell has a simple structure, it is easy to improve the degree of integration of the memory cell array. Therefore, it is widely used in large capacity DRAM.

DRAM memory cells can be classified into several types depending on the structure of the capacitor. Among them, there is a so-called stacked type capacitor. In this stacked type capacitor, the main area of the capacitor is extended to above the gate electrode and the field oxide film to increase the facing area between the electrodes of the capacitor.

As a result, the capacitance of the capacitor can be increased. Since the stacked type capacitor has such characteristics, it is possible to secure the capacitance of the capacitor even when the element is miniaturized due to the integration of the semiconductor memory device. As a result, with the high integration of semiconductor memory devices, stacked type capacitors have come to be widely used.

However, the element is further miniaturized,
For example, in a 256 Mbit DRAM or the like, even if the above-mentioned stacked type capacitor is used, it is difficult to secure a certain capacitance.

Therefore, in order to increase the capacitance of the capacitor, attempts have been made to use a high dielectric film made of a high dielectric constant material such as PZT (lead zirconate titanate ceramic) as the dielectric film of the capacitor. FIG. 37 shows an example of a DRAM in which the above-mentioned high dielectric film such as PZT is used as the dielectric film of the capacitor.

Referring to FIG. 37, p-type semiconductor substrate 201
A field oxide film 202 is formed in the element isolation region on the main surface of the. Transfer gate transistors 203a and 203b are formed in the element formation region on the main surface of the semiconductor substrate 201.

Transfer gate transistor 203
a is an n-type impurity region 206, which is a source / drain region formed on the main surface of the semiconductor substrate 201 with a space.
c, 206a, and a gate electrode 204b formed on the channel region 221 between the impurity regions 206c, 206a with a gate insulating film 205 interposed.

Further, the transfer gate transistor 203b includes n-type impurity regions 206a and 206b serving as source / drain regions and the impurity regions 206a and 206a.
The gate insulating film 20 is formed on the channel region 221 between 206b.
5 has a gate electrode 204c formed therebetween.

On the other hand, the gate electrode 20 of another transfer gate transistor is formed on the field oxide film 202.
4d is extended. Gate electrodes 204b, 204c,
An oxide film 207 is formed so as to cover 204d.
The impurity region 20 is formed on the impurity region 206a.
Buried bit line 208 is formed so as to be electrically connected to 6a. An insulating layer 209 is formed so as to cover the embedded bit line 208.

A first interlayer insulating film 210 is formed so as to cover insulating film 209 and oxide film 207. The upper surface of the first interlayer insulating film 210 is flattened.
In the first interlayer insulating film 210, the impurity region 20
A contact hole 210a is formed in a portion located on 6b.

A plug 211 electrically connected to the impurity region 206b is formed in the contact hole 210a. The upper surface of the plug 211 is buried in the contact hole 210a. This is due to the method of forming the plug 211, and will be described later.

The barrier layer 2 made of TiN or the like extends from the upper surface of the plug 211 to the upper surface of the first interlayer insulating film 210.
13 is formed. A capacitor lower electrode 214 made of platinum (Pt) or the like is formed on the barrier layer 213. The barrier layer 213 is provided to prevent mutual diffusion of the material of the capacitor lower electrode 214 and the material of the plug 211.

A capacitor dielectric film 215 is formed so as to cover the capacitor lower electrode 214. As a material of the capacitor dielectric film 215, a high dielectric film such as SrTiO ₃ can be used. A capacitor upper electrode 216 is formed so as to cover the capacitor dielectric film 215. Examples of the material of the capacitor upper electrode 216 include platinum (Pt) and the like.

A second interlayer insulating film 217 is formed so as to cover the capacitor upper electrode 216. The upper surface of the second interlayer insulating film 217 is flattened. First aluminum wiring layers 218 are formed on the second interlayer insulating film 217 at intervals. A protective film 219 is formed so as to cover the first aluminum wiring layer 218. A second aluminum wiring layer 220 is formed on the protective film 219.

The capacitor lower electrode 214, the capacitor dielectric film 215, and the capacitor upper electrode 216 constitute a capacitor 250.

38 to 46, a method for manufacturing the conventional DRAM shown in FIG. 37 will be described.
38 to 46 are cross-sectional views showing the first to ninth steps of the conventional DRAM manufacturing process.

First, referring to FIG. 38, a semiconductor substrate 201
LOCOS (Local Oxid
of the field oxide film 202 using the
To form. Next, the gate insulating film 205 is formed by using a thermal oxidation method or the like. Gate electrodes (word lines) 204b, 204c, and 204d are selectively formed on the gate insulating film 205 and the field oxide film 202.

The gate electrodes 204b, 204c, 20
Impurity is injected into the main surface of the semiconductor substrate 201 by using 4d as a mask, whereby
c, 206a, 206b are formed respectively. And
An oxide film 207 is formed so as to cover the gate electrodes 204b, 204c, 204d.

The polycrystalline silicon is used as the semiconductor substrate 20.
After being formed on the entire surface 1, the buried bit line 208 electrically connected to the impurity region 206a is formed by patterning into a predetermined shape. This embedded bit line 208
An insulating layer 209 is formed so as to cover the. Then CVD
(Chemical Vapor Deposition) method, etc.
And the interlayer insulating film 210 is formed. Then, the first interlayer insulating film 210 is subjected to a flattening process to flatten the upper surface of the first interlayer insulating film 210.

Next, referring to FIG. 39, a resist pattern 222 patterned into a predetermined shape is formed on first interlayer insulating film 210. This resist pattern 22
Using 2 as a mask, the first interlayer insulating film 210 is anisotropically etched. As a result, the contact hole 210a is formed as shown in FIG.

Then, referring to FIG. 41, a polycrystalline silicon layer 211 is formed by CVD or the like so as to fill contact hole 210a and cover first interlayer insulating film 210.
a is formed. By etching back the polycrystalline silicon layer 211a, the plug 211 is formed in the contact hole 210a as shown in FIG.

At this time, the upper surface of the plug 211 is buried in the contact hole 210a. This is because the first interlayer insulating film 2 has a step (not shown) at the time of etching back the polycrystalline silicon layer 211a.
This is because the over-etching process is performed so that the etching residue of the polycrystalline silicon does not remain on the upper surface of the substrate 10. This is because if the above etching residue remains, a short circuit between wirings may occur. By performing the over-etching process in this way, as shown in FIG. 42, the upper surface of the plug 211 is covered with the contact hole 210a.
The distance D from the upper edge of the side wall of the contact hole 201
It is buried in a.

Next, referring to FIG. 43, a TiN layer 213a is formed on plug 211 and first interlayer insulating film 210 by using a sputtering method or the like. This Ti
A platinum layer 214a is formed on the N layer 213a by a sputtering method or the like. A resist pattern 223 patterned into a predetermined shape is formed on the platinum layer 214a.

Next, using the resist pattern 223 as a mask, a platinum layer 214a and a TiN layer 213a are formed.
Is subjected to anisotropic etching treatment. Thereby, barrier layer 213 and capacitor lower electrode 214 are formed as shown in FIG. After that, resist pattern 2
Remove 23.

Next, referring to FIG. 45, a high dielectric film 215 is formed to cover the capacitor lower electrode 214 by a sputtering method or the like. The material of the dielectric film 215 is SrTiO ₃ or Pb (Zr, Ti) O _3.
And so on. A platinum layer 216 is formed so as to cover the high dielectric film 215. This platinum layer 216
Is processed into a predetermined shape to form the capacitor upper electrode 216.

Then, referring to FIG. 46, a second interlayer insulating film 217 is formed by CVD or the like so as to cover capacitor upper electrode 216. Then, the first aluminum wiring layer 218 is formed on the second interlayer insulating film 217 at a predetermined interval. Then, a protective film 219 made of a silicon oxide film or the like is formed by CVD or the like so as to cover the first aluminum wiring layer 218. A second aluminum wiring layer 220 is formed on this protective film 219. Through the above steps, the conventional DRAM shown in FIG. 37 is formed.

[0030]

However, the conventional DRAM described above has the following problems. The problem will be described with reference to FIG. FIG. 47 is an enlarged cross-sectional view of the connection portion between the conventional capacitor 250 and the plug 211.

Referring to FIG. 47, barrier layer 213 is formed on plug 211 from upper surface 210 of first interlayer insulating film 210.
It is formed over a. This barrier layer 213
Has a predetermined film thickness t5 capable of sufficiently exerting the barrier function. The lower electrode 214 of the capacitor is formed on the barrier layer 213. The lower electrode 214 of this capacitor
Also has a predetermined film thickness t4.

The barrier layer 213 and the capacitor lower electrode 214 are laminated on the upper surface 210a of the first interlayer insulating film 210. Therefore, the upper surface 214b of the capacitor lower electrode 214 and the first interlayer insulating film 210
A relatively large step is formed between the upper surface 210a and the upper surface 210a. The step H of this step is the sum of the film thickness t4 of the capacitor lower electrode 214 and the film thickness t5 of the barrier layer 213.

The capacitor dielectric film 215 is formed to cover the capacitor lower electrode 214. That is, the capacitor dielectric film 215 is formed to cover the stepped portion between the upper surface 214b of the capacitor lower electrode 214 and the upper surface 210a of the interlayer insulating film 210 as described above.

Regarding the method of forming the capacitor dielectric film 215, it is difficult to obtain desired characteristics when the capacitor dielectric film 215 is formed by the CVD method. Has been formed by the law. Therefore, it can be said that the step coverage is poor. Therefore, on the stepped portion, a portion where the film thickness is locally thin is likely to be formed in the capacitor dielectric film.

More specifically, referring to FIG. 47, while the thickness of the capacitor dielectric film 215 located on the upper surface 214b of the capacitor lower electrode 214 is t7,
The film thickness of the capacitor dielectric film 215 on the stepped portion is t6, which is likely to be thin. It is considered that this becomes more prominent as the height difference of the step portion increases.

Since the film thickness of the capacitor dielectric film 215 is locally reduced, a leak current easily flows between the capacitor lower electrode 214 and the capacitor upper electrode 216 at that portion. Problems arise. That is, DRAM
However, there will be a problem that the reliability of the device becomes low.

The present invention is made to solve the above problems. An object of the present invention is to provide a highly reliable DRAM by reducing the step difference of the base of the capacitor dielectric film.

[0038]

According to one aspect, a semiconductor memory device according to the present invention is a semiconductor substrate having a main surface, and is formed on the main surface of the semiconductor substrate and reaches the main surface of the semiconductor substrate. An interlayer insulating film having a contact hole, a plug formed in this contact hole, an electric connection with the main surface of the semiconductor substrate through this plug, and being formed only in the contact hole. A barrier layer containing at least one material selected from the group consisting of a melting point metal oxide, a refractory metal nitride, a refractory metal silicide, and a refractory metal nitride oxide, and a barrier layer formed on the barrier layer Capacitor lower electrode, a capacitor dielectric film made of a high dielectric constant material formed on the capacitor lower electrode, and a capacitor formed on the capacitor dielectric film. And a motor upper electrode.

In another aspect of the semiconductor memory device according to the present invention, an interlayer insulating film having a semiconductor substrate having a main surface and a contact hole formed on the main surface of the semiconductor substrate and reaching the main surface of the semiconductor substrate. A plug embedded in the contact hole so as to contact the main surface of the semiconductor substrate, a capacitor lower electrode formed on the plug, and a capacitor dielectric formed on the capacitor lower electrode and made of a high dielectric constant material. The plug has a body film and a capacitor upper electrode formed on the capacitor dielectric film, and the plug is made of a material having a barrier function of preventing diffusion of the semiconductor substrate material and the capacitor lower electrode material.

According to the method of manufacturing a semiconductor memory device of the present invention, in one aspect, first, an interlayer insulating film having a contact hole reaching the main surface of the semiconductor substrate is formed on the main surface of the semiconductor substrate. . A plug is formed in the contact hole. Then, a barrier layer is formed so as to cover the interlayer insulating film and fill the contact hole. The barrier layer is left only in the contact hole by performing a treatment for reducing the thickness of the barrier layer from the surface portion of the barrier layer. Then, a capacitor lower electrode, a capacitor dielectric film made of a high dielectric constant material, and a capacitor upper electrode are sequentially formed on this barrier layer.

According to the method of manufacturing a semiconductor memory device in accordance with the present invention, in another aspect, first, an interlayer insulating film having a contact hole reaching the main surface of the semiconductor substrate is formed on the main surface of the semiconductor substrate. Then, a barrier layer is formed so as to cover the interlayer insulating film and fill the contact hole. A treatment for reducing the thickness of the barrier layer is applied to the surface portion of the barrier layer, and the barrier layer is left only in the contact hole to form a barrier layer in contact with the main surface of the semiconductor substrate. Then, a capacitor lower electrode, a capacitor dielectric film made of a high dielectric constant material, and a capacitor upper electrode are sequentially formed on this barrier layer.

[0042]

According to the present invention, the barrier layer is formed only in the contact hole. Therefore, unlike the conventional case, the laminated structure of the barrier layer and the capacitor lower electrode is not formed on the upper surface of the interlayer insulating film, and the capacitor lower electrode is directly formed on the upper surface of the interlayer insulating film. This makes it possible to reduce the step difference between the upper surface of the capacitor lower electrode and the upper surface of the interlayer insulating film as compared with the conventional case. That is, it is possible to reduce the step difference of the base of the capacitor dielectric film.

As a result, it becomes possible to improve the coverage of the step of the capacitor dielectric film as compared with the conventional case. As a result, it is possible to suppress the possibility that a portion where the film thickness is locally thinned in the capacitor dielectric film located on the step portion is lower than in the conventional case. As a result, the possibility of leak current in the capacitor can be suppressed to a low level, and the reliability of the semiconductor memory device can be improved.

[0044]

Embodiments of the present invention will be described below with reference to FIGS.

(First Embodiment) First, a DRAM according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a partial sectional view showing a DRAM according to a first embodiment of the present invention. 2 to 1
2 is a DRAM according to the first embodiment of the present invention.
FIG. 13 is a partial cross-sectional view showing the first to eleventh steps of the manufacturing process of.

First, the structure of the DRAM according to the first embodiment of the present invention will be described with reference to FIG. Referring to FIG. 1, field oxide film 2 is formed in the element isolation region on the main surface of p-type semiconductor substrate 1. Transfer gate transistors 3a and 3b are formed in the element formation regions on the main surface of semiconductor substrate 1, respectively.

Transfer gate transistor 3a
Is an n-type impurity region 6a, 6c which is a source / drain region formed at a distance from each other, and a gate formed on the channel region 21 between the impurity regions 6a, 6c with a gate insulating film 5 interposed therebetween. It has an electrode (word line) 4b.

Transfer gate transistor 3b
Are impurity regions 6a and 6b which are formed with a space therebetween and serve as source / drain regions, and the impurity regions 6a and 6b.
The gate electrode 4c is formed on the channel region 21 between a and 6b with the gate insulating film 5 interposed. Further, the gate electrode 4d of another transfer gate transistor is also formed on the field oxide film 2.

An oxide film 7 is formed so as to cover gate electrodes 4b, 4c and 4d. Buried bit line 8 electrically connected to impurity region 6a is formed on impurity region 6a. An insulating layer 9 is formed so as to cover the embedded bit line 8. A first interlayer insulating film 10 is formed so as to cover the insulating layer 9 and the oxide film 7. The upper surface 10b of the first interlayer insulating film 10 is flattened. In addition, the first interlayer insulating film 10 includes
In this case, contact hole 10a is formed in the portion located on impurity region 6b.

A plug 11 made of polycrystalline silicon is formed in the contact hole 10a. The upper surface of the plug 11 is buried in the contact hole 10a. This is due to the method of forming the plug 11 and will be described later.

In the contact hole 10a, the plug is
A barrier layer 13 is formed on the groove 11. This bali
The material of the layer 13 is Ti, TiSi, TiN, T
iO ₂, TiON, W, WSi, WN, WO, WON,
TiOx, TiSix, WSix (0 <x <2), WO
Examples thereof include y (0 <y <3). Also,
A concave portion is formed on the upper surface of the barrier layer 13.
Between the bottom surface of the concave portion and the upper surface 10b of the first interlayer insulating film 10.
Is D1. Of the upper surface of the barrier layer 13.
The recess is formed by the method of forming the barrier layer 13 and the plug 11.
And is consequently formed on its upper surface.
It is what is done.

When Ti is selected as the material of the barrier layer 13, the barrier layer 13 preferably has a film thickness of 50 Å to 300 Å or more. In addition, the barrier layer 13
When TiSi, TiN, or TiON is selected as the material, the barrier layer 13 preferably has a film thickness of about 100 Å to 300 Å or more. In addition, the barrier layer 13
When TiO ₂ is selected as the material for the barrier layer 1,
3 preferably has a film thickness of about 100 Å to 400 Å or more. Further, as the material of the barrier layer 13, W, WS
When i, WN, WO or WON is selected, the film thickness of the barrier layer 13 is preferably about 100 Å to 500 Å or more. Further, as the material of the barrier layer 13, TiO 2 is used.
When x and TiSix are selected, the thickness of the barrier layer 13 is preferably about 100Å to about 300Å.
When WSix and WOy are selected as the material of the barrier layer 13, the thickness of the barrier layer 13 is about 100Å ~
It is preferably about 500Å. Thereby, the barrier layer 13 can exhibit a sufficient barrier function.

A capacitor lower electrode 14 made of platinum (Pt) or the like is formed on the barrier layer 13. The thickness of the capacitor lower electrode 14 is preferably 300
It is about Å-2000Å. The barrier layer 13 has a function of preventing mutual diffusion of the material of the capacitor lower electrode 14 and the material of the plug 11.

A capacitor dielectric film 15 is formed so as to cover the first interlayer insulating film 10 and the capacitor lower electrode 14. As a material of the capacitor dielectric film 15,
High dielectric films such as SrTiO ₃ and BaTiO ₃ can be mentioned. The thickness of the capacitor dielectric film 15 is preferably about 500Å to 2000Å.

At this time, as shown in FIG. 1, the capacitor lower electrode 14 is directly formed on the upper surface 10b of the first interlayer insulating film 10. Therefore, the step difference between the upper surface 14a of the capacitor lower electrode 14 and the upper surface 10b of the first interlayer insulating film 10 is reduced as compared with the conventional case. That is, it is possible to reduce the step difference of the base of the capacitor dielectric film 15 as compared with the conventional case.

As a result, the step coverage of the capacitor dielectric film 15 can be improved more than before, and a portion where the film thickness of the capacitor dielectric film 15 is locally thinned can occur on the stepped portion. It is possible to reduce the property compared with the conventional one. This makes it possible to form a DRAM having a highly reliable capacitor.

Further, by forming the barrier layer 13 only in the contact hole 10a, it becomes possible to reduce the step difference of the underlying layer of the capacitor lower electrode 14 as compared with the conventional case.

A capacitor upper electrode 16 is formed so as to cover the capacitor dielectric film 15 described above. Examples of the material for the capacitor upper electrode 16 include platinum (Pt). Also, this capacitor upper electrode 16
The film thickness of is preferably about 300Å to 2000Å. Another material of the capacitor upper electrode 16 may be polycrystalline silicon. In this case, the film thickness of the capacitor upper electrode 16 is preferably 2000Å
It is about 6000Å.

A second interlayer insulating film 17 made of an oxide film or the like is formed so as to cover the capacitor upper electrode 16. A first aluminum wiring layer 18 is formed on the second interlayer insulating film 17 at a predetermined interval. The protective film 1 covers the first aluminum wiring layer 18.
9 is formed. A second aluminum wiring layer 20 is formed on this protective film 19.

Next, a method of manufacturing the DRAM of the first embodiment having the above structure will be described with reference to FIGS.

Referring to FIG. 2, field oxide film 2, transfer gate transistors 3a and 3b, buried bit line 8 and oxide film are formed on the main surface of p type semiconductor substrate 1 in the same manner as in the conventional example. 7 and insulating layer 9 are formed respectively. Then, using a CVD method or the like, a TEOS (Tetra Ethyl Ortho Silicate) film having a film thickness of about 0.3 to 1.0 μm is deposited so as to cover the insulating layer 9 and the oxide film 7. Then, the TEOS film is subjected to a reflow process to be flattened. Thereby, the first interlayer insulating film 10 is formed.

Next, referring to FIG. 3, a resist pattern 22 patterned into a predetermined shape is formed on first interlayer insulating film 10. Then, this resist pattern 22
Using as a mask, the first interlayer insulating film 10 is etched. Thereby, as shown in FIG. 4, contact hole 10a reaching the surface of impurity region 6b is formed. The opening size of the contact hole 10a is preferably about □ 0.3 μm to □ 0.8 μm.

Next, referring to FIG. 5, a polycrystalline silicon layer 11a is formed by a CVD method using SiH _{4 so} as to fill the contact hole 10a and cover the first interlayer insulating film 10. The film thickness t of the polycrystalline silicon layer 11a is preferably about 3000 Å to about 10,000 Å. At this time, the temperature of the semiconductor substrate 1 is about 6
The temperature is maintained at about 00 ° C to 700 ° C.

Next, referring to FIG. 6, RIE (Reactive
Ion Etching) method or the like is used to form the polycrystalline silicon layer 11
Etch back treatment is applied to a. Thereby, the plug 11 is formed in the contact hole 10a. At this time, an over-etching process is performed so that the residue of the polycrystalline silicon layer 11a does not remain on the surface of the first interlayer insulating film 10. As a result, the upper surface of the plug 11 is buried in the contact hole 10a. At this time, the distance D between the upper surface of the plug 11 and the upper end of the side wall of the contact hole 10a is about 100Å to about 2000Å.

Next, referring to FIG. 7, the barrier layer 13a is formed on the upper surface of the plug 11 and the upper surface of the first interlayer insulating film 10.
Deposit. The film thickness t1 of the barrier layer 13a is preferably about 1000Å to 3000Å. The film thickness t1 of the barrier layer 13a is a film thickness capable of filling the portion on the upper surface of the plug 11 in the contact hole 10a.

Various materials can be considered as the material of the barrier layer 13a. Hereinafter, each deposition method will be described in detail with reference to materials that can be the barrier layer 13a.

First, when Ti is selected as the material of the barrier layer 13a, the barrier layer 13a is formed by the sputtering method or the like. Further, as the material of the barrier layer 13a, TiSi,
When TiSix is selected, the following two forming methods can be considered. The first method is RTA (Rapi) at a temperature of about 500 ° C. after forming a Ti film by a sputtering method or the like.
By performing d Thermal Anneal treatment, TiSi is formed only on the interface with the plug 11 made of polycrystalline silicon. A second method is a method of forming by a CVD method using TiCl ₄ and SiH ₄ . At this time, the temperature of the semiconductor substrate 1 is
It is maintained at 400 ° C to 500 ° C.

When TiN is selected as the material of the barrier layer 13a, the following three forming methods can be considered. First
The above method is a method of forming by a reactive sputtering method in an N ₂ atmosphere. The second method is a method of forming by a CVD method using TiCl ₄ and NH ₃ .
At this time, the temperature of the semiconductor substrate 1 is maintained at 400 ° C to 500 ° C. The third method is a method of nitriding the Ti film. This is done by RTA treatment in an N ₂ or NH ₃ atmosphere. At this time, the processing temperature is about 700 ° C
It is maintained at about 900 ° C.

The material of the barrier layer 13a is TiO ₂ , T
When iOx is selected, the following three forming methods are possible. The first method is a reactive sputtering method in an O ₂ atmosphere. The second method is a method of forming by a CVD method using TiCl ₄ and O ₂ . At this time, the temperature of the semiconductor substrate 1 is maintained at 400 ° C. or lower.
The third method is the oxidation of Ti. This is 500 ℃ ~
It is carried out by heat treatment in an O ₂ atmosphere at a temperature of 700 ° C.

When TiON is selected as the material of the barrier layer 13a, the following three forming methods can be considered. The first method is a reactive sputtering method in an atmosphere of N ₂ and O ₂ . The second method is TiCl ₄ and NH _3.
And a CVD method using O ₂ . At this time, the temperature of the semiconductor substrate 1 is maintained at about 400 ° C to 500 ° C. The third method is the oxidation of TiN. This is 500 ℃ ~ 70
It is performed by heat treatment in an O ₂ atmosphere at a temperature of 0 ° C.

When W is selected as the material of the barrier layer 13a, the following two methods can be considered. The first method is a sputtering method. The second method is a CVD method using WF ₆ . W as the material of the barrier layer 13a
If Si or WSix is selected, WF ₆ and SiH ₄
Is formed by the CVD method using.

When WN is selected as the material of the barrier layer 13a, it is formed by subjecting W to a lamp annealing treatment in a N ₂ or NH ₄ atmosphere at a temperature of 600 ° C. to 800 ° C. When WO or WOy is selected as the material of the barrier layer 13a, 400 ° C. to 600 ° C.
It is formed by subjecting W to a heat treatment in an O ₂ atmosphere at a temperature of ° C.

WON is selected as the material of the barrier layer 13a
In that case, the following two forming methods can be considered. First
Is carried out at a temperature of 500 ° C. to 600 ° C.₂In the atmosphere
This is a method of subjecting WN to heat treatment. The second method is 60
N at a temperature of 0 ° C to 800 ° C ₂Or NH_FourIn the atmosphere
Is a method of subjecting WO to a lamp annealing treatment.

After the barrier layer 13a is deposited by the above method, the barrier layer 13a is etched back. Thereby, the barrier layer 13 is left only in the contact hole 10a. The minimum film thickness required for the barrier layer 13 varies depending on the material as described above, but the film thickness of the barrier layer 13 is not less than the above film thickness capable of sufficiently exhibiting the barrier function for each material. Any film thickness will do.

Further, the above etchback method differs depending on whether the material of the barrier layer 13a is Ti-based or W-based. . That is, when the barrier layer 13a is made of a Ti-based material, RIE processing using a Cl-based gas is performed, and when the barrier layer 13a is a W-based material, RIE processing is performed using an F-based gas.

As a result, the recess 12a is formed on the upper surface of the barrier layer 13 by the above-mentioned etch-back process, as shown in FIG. The distance D1 between the bottom surface of the recess 12a and the top surface 10b of the first interlayer insulating film 10 is 0 to about 1.
It becomes 000Å. The distance D1 is smaller than the distance D between the upper surface of the plug 11 and the upper surface of the first interlayer insulating film 10. This is because the deposited film thickness t1 of the barrier layer 13a is smaller than the deposited film thickness t of the polycrystalline silicon layer 11a, so that the amount of overetching at the time of etch back can be small.

By forming the barrier layer 13 in the contact hole 10a in this manner, it is possible to reduce the step difference of the underlying layer of the capacitor lower electrode formed in a later step. This facilitates formation of the capacitor lower electrode. Further, the surface of the capacitor lower electrode can be made flatter than ever, and the film thickness of the capacitor dielectric film on the capacitor lower electrode can be made more uniform than ever before. As a result, the possibility of leak current in the capacitor can be reduced, and the reliability of the capacitor can be improved.

Next, the barrier layer 13 and the first interlayer insulating film 10 are covered by a sputtering method or the like,
A capacitor lower electrode material layer made of platinum (Pt) or the like is formed. The thickness of the capacitor lower electrode material layer is preferably about 300Å to 2000Å. And
This capacitor lower electrode material layer is patterned into a predetermined shape. As a result, the capacitor lower electrode 14 is formed as shown in FIG.

Next, referring to FIG. 10, SrTiO _{3 is formed} so as to cover the capacitor lower electrode 14 by a reactive sputtering method at a temperature of 500 ° C. to 700 ° C.
A capacitor dielectric film 15 made of a high dielectric film such as BaTiO ₃ is formed in a predetermined shape. The thickness of the capacitor dielectric film 15 is preferably about 500Å to 2000Å.

When the capacitor dielectric film 15 is formed, the upper surface 14 of the capacitor lower electrode 14 serving as a base of the capacitor dielectric film 15 is formed.
The difference between a and the upper surface 10b of the first interlayer insulating film 10 is
Since the barrier layer 13 is formed in the contact hole 10a, the barrier layer 13 is reduced more than before. Therefore, it becomes possible to improve the coverage of the step of the capacitor dielectric film 15 as compared with the conventional case.

As a result, it is possible to reduce the possibility that a portion where the film thickness is locally thin is formed on the capacitor dielectric film 15 on the stepped portion as compared with the conventional case. Thereby, it becomes possible to improve the reliability of the capacitor.

Next, referring to FIG. 11, a capacitor upper electrode 16 is formed so as to cover the capacitor dielectric film 15. Examples of the material for the capacitor upper electrode 16 include platinum (Pt). The forming method and the film thickness are the same as those of the capacitor lower electrode 14 described above.

As the material of the capacitor upper electrode 14,
Polycrystalline silicon etc. can also be mentioned. In this case, C using SiH ₄ at a temperature of 600 ° C. to 700 ° C.
It is formed by the VD method. Further, the thickness of this polycrystalline silicon is preferably about 2000 Å to 6000 Å. After the capacitor upper electrode 16 is formed as described above, the capacitor upper electrode 16 is patterned into a predetermined shape by the RIE method or the like.

Next, referring to FIG. 12, a second interlayer insulating film 17 is formed so as to cover the capacitor upper electrode 16. The material of the second interlayer insulating film 17 is TEO.
S film etc. can be mentioned. Then, the second interlayer insulating film 17 is also flattened. At this time, by embedding the barrier layer 13 in the contact hole 10a, as a result, the step difference on the surface of the capacitor upper electrode 16 can be reduced more than ever before. This facilitates the flattening of the second interlayer insulating film 17. Along with this, the wiring layers (18, 20) formed on the second interlayer insulating film 17 are easily formed.

After forming the second interlayer insulating film 17, the first aluminum wiring layer 18, the protective film 19 and the second aluminum wiring layer 20 are formed in the same manner as in the conventional method.
Thereby, the DR in the first embodiment shown in FIG.
AM will be formed.

(Second Embodiment) Next, referring to FIGS. 13 to 16, a DRAM according to a second embodiment of the present invention will be described.
Will be described. FIG. 13 is a partial sectional view showing a DRAM according to the second embodiment of the present invention. Figure 1
4 to 16 are partial cross-sectional views showing sixth to eighth steps of manufacturing the DRAM according to the second embodiment of the present invention.

Referring to FIG. 13, in the present embodiment, the upper surface of barrier layer 13 and the upper surface 10b of first interlayer insulating film 10 are formed.
And are almost flush. This is due to the method of forming the barrier layer 13, and will be described later in detail. Thus, the upper surface of the barrier layer 13 and the first interlayer insulating film 1
Since the upper surface 10b of 0 is substantially flush with the upper surface 10a of the capacitor lower electrode 14 formed thereon, the upper surface 14a is flattened more than in the case of the first embodiment. The other structure is almost the same as that of the first embodiment shown in FIG.

Next, with reference to FIGS. 14 to 16, a method of manufacturing the DRAM in the second embodiment will be described. First, referring to FIG. 14, the plugs 11 are formed in the same manner as in the first embodiment. Then, a barrier layer 13a is deposited so as to cover the plug 11 and the first interlayer insulating film 10. The film thickness t8 of this barrier layer 13a
Is a thickness such that at least a portion of the contact hole 10a on the upper surface of the plug 11 can be filled with the barrier layer 13a.

Next, referring to FIG. 15, the barrier layer 13a is subjected to CMP (Chemical Mechanical Polishing). Thereby, the barrier layer 13 is left only in the contact hole 10a. At this time, since the barrier layer 13 is left in the contact hole 10a by the CMP process, the upper surface of the barrier layer 13 and the upper surface of the first interlayer insulating film 10 can be made substantially flush with each other.

Next, referring to FIG. 16, capacitor lower electrode 14 is formed on barrier layer 13 and upper surface 10b of first interlayer insulating film 10. At this time, the upper surface 14a of the capacitor lower electrode 14 is further flattened as compared with the case of the first embodiment. The material and forming method of the capacitor lower electrode 14 are the same as those in the first embodiment.

A capacitor dielectric film 15 is formed so as to cover the capacitor lower electrode 14 by the same method as in the first embodiment. In this case as well, as in the case of the first embodiment described above, the step difference of the underlying layer of the capacitor dielectric film 15 is reduced as compared with the conventional case. As a result, the same effect as that of the first embodiment can be obtained. Then, the capacitor upper electrode 16 is formed so as to cover the capacitor dielectric film 15 by the same method as in the case of the first embodiment.

After that, the DR in the second embodiment shown in FIG. 13 is carried out through the same steps as those in the first embodiment.
AM will be formed.

(Third Embodiment) Next, a third embodiment according to the present invention will be described with reference to FIGS. FIG. 17 is a partial sectional view showing a DRAM according to the third embodiment of the present invention. 18 to 21 are
It is a fragmentary sectional view showing the 6th process of a DRAM manufacturing process in a 3rd example based on this invention.

First, the structure of the DRAM of the third embodiment will be described with reference to FIG. Referring to FIG.
In this embodiment, the barrier layer has a two-layer structure. That is, the first barrier layer 13 is formed on the upper surface of the plug 11.
b is formed, and the second barrier layer 13c is formed on the first barrier layer 13b.

At this time, a recess is formed on the surface of the second barrier layer 13c as in the case of the barrier layer 13 described above, and the bottom of the recess and the upper surface 10 of the first interlayer insulating film 10 are formed.
The distance to b is D2. The value of this D2 is
It is smaller than the distance D1 between the bottom surface of the recess of the barrier layer 13 and the top surface 10b of the first interlayer insulating film 10 in the first embodiment. This is due to the method of forming the barrier layer and will be described later.

As described above, since the distance D1 is smaller than the distance D, it is possible to reduce the step difference of the underlying layer of the capacitor lower electrode 14 as compared with the first embodiment. As a result, the upper surface of the capacitor lower polarization 14 can be made even flatter than in the first embodiment. The other structure is similar to that of the first embodiment shown in FIG.

In this embodiment, the barrier layer is composed of the first barrier layer 13b which contacts the upper surface of the plug 11 and the first barrier layer 13b.
Second barrier layer 13c formed on the barrier layer 13b of
And has a two-layer structure. Therefore, the first barrier layer 13b located in the contact hole 10a is not directly subjected to the etch back process.

Therefore, the film thickness of the first barrier layer 13b located in the contact hole 10a is maintained at the film thickness at the time of deposition. On the other hand, since the upper surface of the second barrier layer 13c located in the contact hole 10a is directly subjected to the etch back process, the film thickness of the second barrier layer 13c may vary depending on the etching conditions. .

The same applies to the above first embodiment. That is, in the above-described first embodiment, the barrier layer 1 remaining in the contact hole 10a is
In No. 3, there is a possibility that there is a portion where the film thickness becomes locally thin due to etching conditions and the like. The barrier property is not sufficiently exhibited unless the barrier layer has a film thickness equal to or larger than a predetermined film thickness.

In this embodiment, the first layer located in the lower layer
Since the film thickness of the barrier layer 13b is maintained at the film thickness at the time of deposition, the barrier function is sufficiently exhibited even if the film thickness of the second barrier layer 13c varies. This makes it possible to obtain a barrier layer that can exhibit a barrier function more stably than in the case of the first embodiment.

Next, with reference to FIGS.
A method of manufacturing the DRAM in the embodiment will be described.

First, with reference to FIG. 18, the plugs 11 are formed in the same manner as in the first embodiment. Plug 1
A first barrier layer 13b is deposited so as to cover the first and first interlayer insulating films 10. The film thickness of the first barrier layer 13b is a film thickness that can function as a barrier layer. This first
The second barrier layer 13c is deposited on the barrier layer 13b. The film thickness t2 of the second barrier layer 13c is a film thickness capable of filling the portion of the contact hole 10a located on the upper surface of the plug 11.

Examples of the material for the first barrier layer 13b include Ti and TiSi. This T
The film thickness of i is preferably about 50 to 300Å.
The thickness of TiSi is preferably 100 to 300.
It is about Å.

When Ti is selected as the first barrier layer 13b, the material of the second barrier layer 13c is preferably TiO or TiO. The film thickness of TiO and TiO is preferably about 100 to 300 Å. Further, when TiSi is selected as the first barrier layer 13b, the second barrier layer 13c is preferably TiO or TiO. The film thickness thereof is the same as in the above case.

Next, referring to FIG. 19, the second barrier layer 13c is etched back by RIE using a Cl-based gas. Thereby, the second barrier layer 13c is left only in the contact hole 10a. At this time, as a result, the concave portion 12b is formed on the surface of the second barrier layer 13c. The recess 12b is smaller than the recess 12a formed in the barrier layer 13 in the first embodiment. This is because the laminated structure of the first and second barrier layers 13b and 13c is formed on the side wall of the contact hole 10a. As a result, the base of the capacitor lower electrode 14 can be made flatter than in the first embodiment.

Then, referring to FIG. 20, the first barrier layer 13b is etched back to leave the first barrier layer 13b only in the contact hole 10a. At this time, the first barrier layer 13b located in the contact hole 10a is not directly subjected to the above-mentioned etch back treatment. Thereby, in the contact hole 10a, the film thickness of the first barrier layer 13b is maintained at the film thickness at the time of deposition. Thereby, the first barrier layer 13b surely exhibits the barrier function.

The distance D2 between the bottom surface of the recess 12b formed on the surface of the second barrier layer 13c and the upper surface of the first interlayer insulating film 10 is the distance D in the first embodiment.
It is smaller than. This is because the laminated structure of the first and second barrier layers 13b and 13c is formed on the upper surface of the plug 11.

Next, referring to FIG. 21, first and second
The first interlayer insulating film 10 from above the barrier layers 13b and 13c of
A capacitor lower electrode 14 is formed over the upper surface 10b of the capacitor. The capacitor dielectric film 15 and the capacitor upper electrode 16 are formed so as to cover the capacitor lower electrode 14.
Is formed. The materials and manufacturing method of the capacitor lower electrode 14, the capacitor dielectric film 15 and the capacitor upper electrode 16 are the same as those in the first embodiment.

In this embodiment, the second barrier layer 13
Since the recess 12b on the surface c is smaller than the recess 12a on the surface of the barrier layer 13 in the first embodiment,
The surface 14a of the capacitor lower electrode 14 can be made flatter than in the case of the first embodiment. Further, similarly to the first embodiment, the step coverage of the underlayer of the capacitor dielectric film 15 is also improved in this embodiment.

As described above, the capacitor upper electrode 16
After forming, the DRAM in the third embodiment shown in FIG. 17 is formed through the same steps as those in the first embodiment.

(Fourth Embodiment) Next, a fourth embodiment according to the present invention will be described with reference to FIGS. FIG. 22 is a partial sectional view showing a DRAM according to the fourth embodiment of the present invention. 23 to 26,
It is a fragmentary sectional view showing the 6th process of a DRAM manufacturing process in a 4th example based on this invention.

First, with reference to FIG. 22, the structure of the DRAM according to the third embodiment of the present invention will be described.
With reference to FIG. 22, in the present embodiment, the barrier layer is 3
It has a layered structure. That is, on the upper surface of the plug 11,
The first barrier layer 13d is formed, and the second barrier layer 13e is formed on the first barrier layer 13d.
The third barrier layer 13f is formed on the barrier layer 13e. The other structure is similar to that of the first embodiment.

In this embodiment, since the barrier layer has a three-layer structure, the bottom surface of the recess formed on the surface of the third barrier layer 13f and the top surface 1 of the first interlayer insulating film 10 are formed.
The distance D3 from 0b can be smaller than the distance D2 in the third embodiment. Thereby,
It is possible to flatten the base of the capacitor lower electrode 14 more than in the case of the third embodiment.

Further, in this embodiment, the first and second barrier layers 13 in the contact hole 10a are formed.
The film thicknesses of d and 13e are maintained as they were at the time of deposition.
That is, the first and second barrier layers 13d and 13e
Ensures that the film thickness capable of functioning as a barrier layer is maintained. As a result, the barrier property of the barrier layer can be ensured more reliably than in the case of the first embodiment.

Further, it becomes easier to make the barrier layer thicker than the barrier layers in the first and second embodiments. This facilitates the formation of a barrier layer that exhibits a barrier function superior to those of the first and second embodiments.

Next, the manufacturing method in the above-mentioned fourth embodiment will be described with reference to FIGS.

First, with reference to FIG. 23, the plug 11 is formed through the same steps as those in the first embodiment. Then, a first barrier layer 13d is deposited so as to cover the plug 11 and the first interlayer insulating film 10. The film thickness of the first barrier layer 13d is a film thickness that can sufficiently exhibit the function as a barrier layer.

A second barrier layer 13e is deposited on this first barrier layer 13d. The film thickness of the second barrier layer 13e is also a film thickness capable of sufficiently exhibiting the function as a barrier layer. The third barrier layer 1 is formed on the second barrier layer 13e.
Deposit 3f. The film thickness t3 of the third barrier layer 13f
Is a thickness with which the portion of the contact hole 10a on the second barrier layer 13e can be filled with the third barrier layer 13f.

The following combinations of materials for the first barrier layer 13a, the second barrier layer 13e, and the third barrier layer 13f can be considered. Ti (third barrier layer) / TiN (second barrier layer) / Ti (first barrier layer), Ti / TiON / Ti, Ti / TiN
/ TiSi, Ti / TiON / TiSi, W / TiN /
Ti, WSi / TiN / Ti, WN / TiN / Ti, W
O / TiN / Ti, WON / TiN / Ti, etc.

The thickness of Ti is preferably 50 to 50.
It is about 300Å. Further, the film thickness of TiN is preferably 100 to 300Å. Further, the film thickness of TiON is preferably about 100 Å to 300 Å. Ti
The film thickness of Si is preferably about 100Å to 300Å. The film thickness of W, WSi, WN, WO, WON is preferably about 100Å to 500Å.

Regarding the film thickness of the third barrier layer 13f, it is preferable that the third barrier layer 13f is formed to have a film thickness equal to or more than the above film thickness for the selected material.

Next, referring to FIG. 24, the third barrier layer 13f is subjected to an etch back process. Thereby, the third barrier layer 13a is left only in the contact hole 10a. Next, the second barrier layer 13e and the first barrier layer 13d are sequentially etched. As a result, as shown in FIG. 25, the first and second barrier layers 13d and 13e are left only in the contact hole 10a.

As a result, as shown in FIG. 25, the third
The concave portion 12c is formed on the surface of the barrier layer 13f in the same manner as in the first and third embodiments. However, the recess 12c is smaller than in the case of the first and third embodiments. This is because the first, second and third barrier layers 13 are formed on the sidewalls of the contact hole 10a.
This is because a laminated structure of d, 13e, and 13f is formed.

The distance D3 between the bottom surface of the recess 12c and the top surface of the first interlayer insulating film 10 is even smaller than D2 in the third embodiment. This is because the laminated structure of the first, second and third barrier layers 13d, 13e and 13f is formed on the upper surface of the plug 11. As a result, the base of the capacitor lower electrode 14 is flattened more than in the case of the third embodiment.

Next, referring to FIG. 26, the capacitor lower electrode 14 is formed over the first, second and third barrier layers 13d, 13e, 13f and the upper surface 10b of the first interlayer insulating film 10. . Then, a capacitor dielectric film 15 and a capacitor upper electrode 16 are formed so as to cover the capacitor lower electrode 14, respectively.

The manufacturing method and material of the capacitor lower electrode 14, the capacitor dielectric film 15, and the capacitor upper electrode 16 are the same as those in the first embodiment.
After that, the same steps as those in the first embodiment described above are performed, and the process shown in FIG.
The DRAM shown in 2 will be formed.

(Fifth Embodiment) Next, a fifth embodiment according to the present invention will be described with reference to FIGS. FIG. 27 is a partial sectional view showing a DRAM according to the fifth embodiment of the present invention. 28 to 31 are
It is a fragmentary sectional view showing the 4th process of a DRAM manufacturing process in a 5th example based on this invention.

First, with reference to FIG. 27, the structure of a DRAM according to the fifth embodiment of the present invention will be described.
Referring to FIG. 27, in the present embodiment, connection conductor portion 13g having a function as a plug and a function as a barrier layer is formed in contact hole 10a.

Since the connecting conductor portion 13g is thicker than the barrier layer of each of the above-mentioned embodiments, it can be said that it has the best barrier function. However, the upper surface of the connection conductor portion 13g is buried in the contact hole 10a. This is due to the forming method and will be described later. Therefore, a step portion is formed on the upper surface 14a of the capacitor lower electrode 14 at a portion located on the connection conductor portion 13g. However, this step is not as large as the step between the capacitor lower electrode 214b and the upper surface 210a of the first interlayer insulating film 210 in the conventional example,
It is possible to improve the coverage of the step of the capacitor dielectric film 15 as compared with the conventional example.

A method of manufacturing the DRAM in the fifth embodiment will be described with reference to FIGS. 28 to 31. First, referring to FIG. 28, contact hole 10a is formed through the same steps as those in the first embodiment.
Next, a connecting conductor portion material 13h is deposited so as to fill the contact hole 10a and cover the first interlayer insulating film 10. The material of the connecting conductor portion material 13h is TIN.
And so on. The film thickness t9 of the connecting conductor material 13h is preferably 3000Å to 100.
It is about 00Å. The film thickness t of the connecting conductor material 13h
9 is a film thickness capable of filling the contact hole 10a with the connecting conductor material 13h.

As the method for forming the connecting conductor portion material 13h, the following two forming methods can be considered. The first method is
It is formed by a CVD method using TiCl ₄ and NH ₄ . The second method is a method of forming using a reactive sputtering method.

Then, referring to FIG. 29, the connection conductor portion material 13h is etched back by the RIE method using a Cl-based gas. Thereby, the connection conductor portion 13g is formed in the contact hole 10a. At this time, an over-etching process is performed so that the connecting conductor material 13h does not remain on the upper surface of the first interlayer insulating film 10. Therefore, the upper surface of the connection conductor portion 13g is buried in the contact hole 10a. As a result, the distance D4 between the upper surface of the connecting conductor portion 13g and the upper surface 10a of the first interlayer insulating film 10 is about 100Å to about 2000Å.
It will be about.

Then, referring to FIG. 30, the capacitor lower electrode 14 is formed over the connection conductor portion 13g and the first interlayer insulating film 10 by the same method as in the first embodiment. At this time, since the upper surface of the connection conductor portion 13g is buried in the contact hole 10a, a step is formed on the surface of the capacitor upper electrode 14.

Then, referring to FIG. 31, a capacitor dielectric film 15 and a capacitor upper electrode 16 are formed to cover the capacitor lower electrode 14 by the same method as in the first embodiment. After that, the DRAM shown in FIG. 27 is formed through the same steps as those in the first embodiment.

(Sixth Embodiment) Next, a sixth embodiment according to the present invention will be described with reference to FIGS. FIG. 32 shows D in the sixth embodiment according to the present invention.
It is a fragmentary sectional view showing RAM. 33 to 35 are partial cross-sectional views showing fourth to sixth steps of the DRAM manufacturing process of the sixth embodiment according to the present invention.

First, with reference to FIG. 32, the structure of a DRAM according to the sixth embodiment of the present invention will be described.
In this embodiment, the upper surface of the connecting conductor portion 13g and the upper surface 10b of the first interlayer insulating film 10 are substantially flush with each other. This is due to the method of forming the connecting conductor portion 13g and will be described later. Therefore, the upper surface 14a of the capacitor lower electrode 14 is substantially flat.

At this time, since the connecting conductor portion 13g is made of a material having a barrier function, an excellent barrier function is secured as in the case of the fifth embodiment. Further, the step difference of the underlying layer of the capacitor dielectric film 15 is smaller than that of the prior art as in the first embodiment, and the upper surface 14a of the capacitor lower electrode 14 is a substantially flat surface. The step coverage of the capacitor dielectric film 15 is further improved as compared with the fifth embodiment. .

A method of manufacturing the DRAM in the sixth embodiment will be described with reference to FIGS. 33 to 35. Referring to FIG. 33, connection conductor material 13h is formed by the same method as in the fifth embodiment. At this time, the film thickness t10 of the connecting conductor portion material 13h is a film thickness capable of filling the contact hole 10a with the connecting conductor portion material 13h.

Next, referring to FIG. 34, the above-mentioned connecting conductor portion material 13h is subjected to CMP processing. As a result, FIG.
As shown in FIG. 5, the connection conductor portion 13g is formed in the contact hole 10a. Since the connecting conductor portion 13g is formed by performing the CMP process as described above, the upper surface of the connecting conductor portion 13g and the upper surface of the first interlayer insulating film 10 can be substantially flush with each other.

Next, referring to FIG. 35, the connection conductor portion 13
A capacitor lower electrode 14 is formed on g and on the upper surface 10b of the first interlayer insulating film 10 by the same method as in the first embodiment. At this time, since the upper surface of the connection conductor portion 13g and the upper surface 10b of the first interlayer insulating film 10 are substantially flush with each other, the upper surface 14a of the capacitor lower electrode 14 is a substantially flat surface.

Capacitor dielectric film 15 and capacitor upper electrode 16 are formed to cover capacitor lower electrode 14 by the same method as in the first embodiment. After that, the DRAM shown in FIG. 32 is formed through the same steps as those in the first embodiment.

[0142]

According to the present invention, since the barrier layer is formed in the contact hole, it is possible to reduce the step difference between the upper surface of the capacitor lower electrode and the upper surface of the interlayer insulating film as compared with the conventional case. That is, the step difference of the base of the capacitor dielectric film is reduced. As a result, the step coverage of the capacitor dielectric film can be improved more than ever before. Thereby, in the capacitor dielectric film,
It becomes more difficult to form a locally thinned portion than in the conventional case. When a part where the film thickness is locally thin is formed in the capacitor dielectric film, at that part,
There is a high possibility that a leak current will flow between the capacitor upper electrode and the capacitor lower electrode.

According to the present invention, as described above, it is possible to reduce the possibility that a portion where the film thickness is locally thinned is formed in the capacitor dielectric film as compared with the conventional case. As a result, it becomes possible to improve the reliability of the capacitor more than ever before. As a result, the reliability of the semiconductor memory device can be improved.

[Brief description of drawings]

FIG. 1 is a DRA in a first embodiment according to the present invention.
It is a fragmentary sectional view showing M.

FIG. 2 is a DRA in the first embodiment according to the present invention.
It is a fragmentary sectional view showing the 1st process of a manufacturing process of M.

FIG. 3 is a DRA in the first embodiment according to the present invention.
It is a fragmentary sectional view showing the 2nd process of a manufacturing process of M.

FIG. 4 is a DRA in the first embodiment according to the present invention.
It is a fragmentary sectional view showing the 3rd process of a manufacturing process of M.

FIG. 5: DRA in the first embodiment according to the present invention
It is a fragmentary sectional view showing the 4th process of the manufacturing process of M.

FIG. 6 is a DRA in the first embodiment according to the present invention.
It is a fragmentary sectional view showing the 5th process of a manufacturing process of M.

FIG. 7: DRA in the first embodiment according to the present invention
It is a fragmentary sectional view showing the 6th process of a manufacturing process of M.

FIG. 8: DRA in the first embodiment according to the present invention
It is a fragmentary sectional view showing the 7th process of a manufacturing process of M.

FIG. 9 is a DRA in the first embodiment according to the present invention.
It is a fragmentary sectional view showing the 8th process of a manufacturing process of M.

FIG. 10: DR in the first embodiment according to the present invention
It is a fragmentary sectional view showing the 9th process of a manufacturing process of AM.

FIG. 11 is a DR in the first embodiment according to the present invention.
It is a fragmentary sectional view showing the 10th process of a manufacturing process of AM.

FIG. 12: DR in the first embodiment according to the present invention
It is a fragmentary sectional view showing the 11th process of a manufacturing process of AM.

FIG. 13 is a DR in a second embodiment according to the present invention.
It is a fragmentary sectional view showing AM.

FIG. 14 DR in the second embodiment according to the present invention
It is a fragmentary sectional view showing the 6th process of a manufacturing process of AM.

FIG. 15 is a DR in a second embodiment according to the present invention.
It is a fragmentary sectional view showing the 7th process of a manufacturing process of AM.

FIG. 16 is a DR in a second embodiment according to the present invention.
It is a fragmentary sectional view showing the 8th process of a manufacturing process of AM.

FIG. 17 is a DR in a third embodiment according to the present invention.
It is a fragmentary sectional view showing AM.

FIG. 18 shows a DR in the third embodiment according to the present invention.
It is a fragmentary sectional view showing the 6th process of a manufacturing process of AM.

FIG. 19 shows a DR in the third embodiment according to the present invention.
It is a fragmentary sectional view showing the 7th process of a manufacturing process of AM.

FIG. 20: DR in the third embodiment according to the present invention
It is a fragmentary sectional view showing the 8th process of a manufacturing process of AM.

FIG. 21 is a DR in a third embodiment according to the present invention.
It is a fragmentary sectional view showing the 9th process of a manufacturing process of AM.

FIG. 22 shows a DR in the fourth embodiment according to the present invention.
It is a fragmentary sectional view showing AM.

FIG. 23 is a DR in a fourth embodiment according to the present invention.
It is a fragmentary sectional view showing the 6th process of a manufacturing process of AM.

FIG. 24 is a DR according to a fourth embodiment of the present invention.
It is a fragmentary sectional view showing the 7th process of a manufacturing process of AM.

FIG. 25 is a DR in the fourth embodiment according to the present invention.
It is a fragmentary sectional view showing the 8th process of a manufacturing process of AM.

FIG. 26 is a DR in a fourth embodiment according to the present invention.
It is a fragmentary sectional view showing the 9th process of a manufacturing process of AM.

FIG. 27 is a DR in a fifth embodiment according to the present invention.
It is a fragmentary sectional view showing AM.

FIG. 28 is a DR in a fifth embodiment according to the present invention.
It is a fragmentary sectional view showing the 4th process of a manufacturing process of AM.

FIG. 29 is a DR in a fifth embodiment according to the present invention.
It is a fragmentary sectional view showing the 5th process of a manufacturing process of AM.

FIG. 30 is a DR in a fifth embodiment according to the present invention.
It is a fragmentary sectional view showing the 6th process of a manufacturing process of AM.

FIG. 31 is a DR according to a fifth embodiment of the present invention.
It is a fragmentary sectional view showing the 7th process of a manufacturing process of AM.

FIG. 32 is a DR in a sixth embodiment according to the present invention.
It is a fragmentary sectional view showing AM.

FIG. 33 is a DR in a sixth embodiment according to the present invention.
It is a fragmentary sectional view showing the 4th process of a manufacturing process of AM.

FIG. 34 is a DR according to a sixth embodiment of the present invention.
It is a fragmentary sectional view showing the 5th process of a manufacturing process of AM.

FIG. 35 is a DR in a sixth embodiment according to the present invention.
It is a fragmentary sectional view showing the 6th process of a manufacturing process of AM.

FIG. 36 is a block diagram showing a general structure of a DRAM.

FIG. 37 is a partial cross-sectional view showing an example of a conventional DRAM.

FIG. 38 is a partial cross-sectional view showing the first step of the conventional DRAM manufacturing steps.

FIG. 39 is a partial cross-sectional view showing a second step of the conventional DRAM manufacturing process.

FIG. 40 is a partial cross-sectional view showing a third step of the conventional DRAM manufacturing steps.

FIG. 41 is a partial cross-sectional view showing a fourth step of the manufacturing process of the conventional DRAM.

FIG. 42 is a partial cross sectional view showing a fifth step of the conventional DRAM manufacturing steps.

FIG. 43 is a partial cross sectional view showing a sixth step of the conventional DRAM manufacturing steps.

FIG. 44 is a partial cross sectional view showing a seventh step of the conventional DRAM manufacturing steps.

FIG. 45 is a partial cross sectional view showing an eighth step of the manufacturing process of the conventional DRAM.

FIG. 46 is a partial cross-sectional view showing a ninth step of the conventional DRAM manufacturing steps.

FIG. 47 is an enlarged cross-sectional view of a connection portion between a capacitor and a plug in a conventional DRAM.

[Explanation of symbols]

1,201 semiconductor substrate 3a, 3b, 203a, 203b transfer gate transistor 10,210 first interlayer insulating film 10a, 210a contact hole 11,211 plug 13, 13a, 213 barrier layer 13b, 13d first barrier layer 13c, 13e 2nd barrier layer 13f 3rd barrier layer 13g Connection conductor part 14,214 Capacitor lower electrode 15,215 Capacitor dielectric film 16,216 Capacitor upper electrode

Claims (5)

[Claims] 1. A semiconductor substrate having a main surface, an interlayer insulating film having a contact hole formed on the main surface of the semiconductor substrate and reaching the main surface of the semiconductor substrate, and formed in the contact hole. A plug, which is electrically connected to the main surface of the semiconductor substrate through the plug and is formed only in the contact hole,
A barrier layer containing at least one material selected from the group consisting of refractory metals, refractory metal oxides, refractory metal nitrides, refractory metal silicides, refractory metal nitride oxides, and A capacitor lower electrode formed on the barrier layer, a capacitor dielectric film made of a high dielectric constant material formed on the capacitor lower electrode, and a capacitor upper electrode formed on the capacitor dielectric film. Semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein the capacitor lower electrode is made of a high melting point noble metal. 3. A semiconductor substrate having a main surface, an interlayer insulating film having a contact hole formed on the main surface of the semiconductor substrate and reaching the main surface of the semiconductor substrate, and contacting the main surface of the semiconductor substrate. A plug buried in the contact hole, a capacitor lower electrode formed on the plug, a capacitor dielectric film formed on the capacitor lower electrode and made of a high dielectric constant material, A semiconductor memory device, comprising: a capacitor upper electrode formed on a body film, wherein the plug is made of a material having a barrier function of preventing diffusion of the semiconductor substrate material and the capacitor lower electrode material. 4. A step of forming, on a main surface of a semiconductor substrate, an interlayer insulating film having a contact hole reaching the main surface of the semiconductor substrate; a step of forming a plug in the contact hole; A step of forming a barrier layer so as to cover the film and fill the contact hole; and a step of reducing the thickness of the barrier layer from the surface portion of the barrier layer, thereby forming the barrier layer in the contact hole. And a step of sequentially forming a capacitor lower electrode, a capacitor dielectric film made of a high dielectric constant material, and a capacitor upper electrode on the barrier layer. 5. A step of forming, on the main surface of the semiconductor substrate, an interlayer insulating film having a contact hole reaching the main surface of the semiconductor substrate, and covering the interlayer insulating film and filling the contact hole. A step of forming a barrier layer into the contact hole, and a treatment for reducing the thickness of the barrier layer from the surface portion of the barrier layer to leave the barrier layer only in the contact hole, thereby forming the semiconductor substrate in the contact hole. A semiconductor memory device comprising: a step of forming a barrier layer in contact with the main surface; and a step of sequentially forming a capacitor lower electrode, a capacitor dielectric film made of a high dielectric constant material, and a capacitor upper electrode on the barrier layer. Manufacturing method.