JPH0773354B2 - Video signal processor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording / reproducing apparatus, and more particularly to a video signal processing apparatus suitable for video signal processing for high density recording of a wide band video signal.

[Conventional technology]

A new high-definition television system that has several times as much image information as conventional so-called high-definition televisions that can provide much higher definition and higher image quality than the current television system, and therefore requires several times the bandwidth. Is under consideration.

In order to put this high-definition television into practical use, the realization of a magnetic recording / reproducing device such as a VTR capable of accurately recording / reproducing a wideband high-definition video signal has become an important issue. A prototype of this VTR for high-definition television is reported in a document entitled "VTR for high-definition television" by Ogaya, Tateno, and Tsujikawa in Technical Report PPOE 56-2 (November 1984) of the Institute of Television Engineers of Japan. Has been done.

This VTR was prototyped mainly for studio use. A head drum with a relatively large diameter was used to achieve a wider band, and a method of recording video signals by dividing them into 4-channel multi-tracks was adopted. ing.

[Problems to be solved by the invention]

In order to widely disseminate this high-definition television to general households, it is necessary to simultaneously disseminate VTRs for high-definition television. To this end, it is important to make the VTR for high-definition televisions compact, to reduce the cost of the device, and to enable long-time recording / playback with a small cassette. In order to solve these problems, it is necessary to reduce the size of the head drum to reduce the size and weight of the device, reduce the number of channels, reduce the circuit scale, and reduce the cost.

In view of the above, an object of the present invention is to time-division-multiplex a luminance signal and a color-difference signal with minimum redundancy, narrow an occupied band of a video signal, and record it by dividing it into a plurality of channels. To reduce the transmission band per channel to reduce the size and weight of the device and reduce the cost, and also to minimize the number of memories to be used, and to realize a video signal processing device that can reduce the circuit scale. is there.

[Means for solving problems]

The above object is achieved as follows. That is, of the wideband video signal, the luminance signal is time-expanded a times and is alternately distributed to two channels for each line. The color-difference signal is subjected to vertical edge band limitation and rear-edge sequential conversion, and b
Double time extension and distribute to the above two channels. For each channel, the horizontal blanking period and the vertical blanking period are removed so as to minimize, and a luminance signal time-expanded a times, a color difference signal time-expanded b times, and synchronization information are further transmitted. Divide and multiplex. Then, the obtained 2-channel video signals are simultaneously recorded in the VTR. At this time, a period for switching heads is provided within an overlap period in which two heads facing each other simultaneously contact the tape.

In order to perform the above signal processing, two channels of memory are assigned to one channel and one signal. Memory capacity is 1 of video signal
In the field period, it is an integral multiple of at least 1/2 of the effective video signal portion excluding the vertical blanking period.
Approximately 1/2 of the effective video signal part in these two systems of memory
Alternately write a signal every integer multiple of and read from the memory on the side not written.

The video signal thus recorded using the two channels is restored by the following signal processing during reproduction. That is, the luminance signal of each channel is time-expanded to 1 / a times, the signals of each channel are alternately selected, and the original luminance signal is restored when a series of signals is obtained. Further, the color difference signals of the respective channels are time-expanded to 1 / b times, and the original simultaneous signals are restored by interpolating the line-sequential signals.

In order to perform the above signal processing, two systems of memories are assigned to each of the luminance signal and the color difference signal per channel. This memory capacity is an integral multiple of at least approximately 1/2 of the effective video signal portion excluding the vertical blanking period in one field period of the video signal. Signals are alternately written into the memories of the two systems every integer multiple of approximately 1/2 of the effective video signal portion, and the signals are read out from the memory on the non-writing side.

[Action]

The above two memories for recording and reproducing have similar functions. That is, by providing at least an integral multiple of the storage capacity of about 1/2 of the effective video signal portion in the memory, in the case of an odd multiple, the period corresponding to the vertical blanking interval m _V after the signal processing, the even in the case of doubled, when the vertical blanking period of the original image signal and l _V, a period corresponding to m _V + l _V, also read start timing from the memory caused by such rotation unevenness of the cylinder varies, normal A signal processing operation can be performed. This means that, shows that the time base correction capability of m _V or m _V + l _V there.

Therefore, normal signal processing can be performed with a small number of memories even with respect to time variations within the above period.

〔Example〕

Below, a high-definition TV signal is sent to a helical scan VTR.
An embodiment of the present invention in the case of recording dividedly into one channel will be described.

As an example, a high-definition television signal is composed of 30 frames per second and 1125 scanning lines per frame. In addition, one frame is composed of two flareds, and 2: 1 interlaced scanning is performed. Two sets of magnetic heads facing each other, four in total, are used, and the magnetic tape is wound around the cylinder by 180 ° or more.
The video signal shall be recorded over 180 °.

FIG. 1 is a block diagram of a recording system circuit of a VTR showing an embodiment of the present invention. In FIG. 1, 1, 2, and 3 are input terminals for video signals of three primary colors of red (R), green (G), and blue (B), 4 is an input terminal of a horizontal synchronizing signal HD, and 5 is a vertical synchronizing signal. VD input terminal, 10 is a signal conversion circuit for converting the three primary color signals R, G, B into a luminance signal Y and two color difference signals C _W , C _N ,
20,21,22 are reduction pass filters (hereinafter referred to as LPF), 23,2
4, 25 are AD conversion circuits, 30, 31 are line memories, 32, 33 are vertical pre-value N filters, 34 are line sequential conversion circuits, 40, 41 are serial / parallel conversion circuits, 50-57 are memories, 60 ~ 63 is a selection circuit, 70 ~ 73 is a parallel / serial conversion circuit, 80,8
1 is a selection circuit, 90, 91 is a DA conversion circuit, 92, 93 is an FM signal processing circuit 94, 95 is a recording amplifier, 100, 100 ', 101, 101' are magnetic heads, 102 is a magnetic tape, 110 is a rotational phase of the magnetic heads 100, 101. Is a tuck signal waveform shaping circuit, 112 is a delay circuit, 120 is a PLL circuit, and 121 is a control signal generation circuit.

The three primary color signals R, G, B input from the terminals 1, 2, 3 are input to the signal conversion circuit 10 and converted into a luminance signal Y and two color difference signals C _W , C _N. Signals output from the signal conversion circuit 10 Y, C _W ,
C _N is input to LPFs 20, 21 and 22, respectively, and is limited to a required band, and then converted into digital signals after being subjected to sampling processing by AD conversion circuits 23, 24 and 25, respectively.

The sampling processing of the AD conversion circuits 23, 24, 25 is performed based on the clock signals _Y and _C from the control signal generation circuit 121. The horizontal synchronizing signal HD input from the terminal 4 is input to the PLL circuit, and the clock signal CK synchronized with the input three primary color signals R, G, B is obtained. The clock signal CK is input to the control signal generation circuit 121, where sampling clocks _Y and _C are generated.

The frequencies of the sampling clocks _Y and _C are set to be at least twice the cutoff frequencies of the LPFs 20 and 21. As an example, the cutoff frequency of LPF20 is 20MH
z, LPF21,22 cutoff frequency 7MHz, _Y
50MHz, To be

The digital luminance signal converted by the AD conversion circuit 23 based on the clock signal _Y is input to the serial / parallel conversion circuit 40, and its output parallel signal is stored in the memories 50, 51, 54, 55.
Are written in sequence. Where serial-parallel conversion circuit
At 40, the serial data of the input digital luminance signal is converted into parallel data and phase-divided so as to have a transmission rate writable in the memories 50, 51, 54, 55.

On the other hand, the digital color difference signals input and output from the AD conversion circuits 24 and 25 are written in the line memories 30 and 31 each having a storage capacity of several lines. The vertical pre-value filters 32 and 33 read the digital color difference signals from the line memories 30 and 31, perform arithmetic processing based on the digital color difference signal data, and limit the band in the vertical direction to 1/2 or less. The outputs of the vertical direction pre-value filters 32 and 33 are input to the line-sequential conversion circuit 34, the color difference signals C _W and C _N are alternately selected for each line, and the color-difference line-sequential signals are output from the line-sequential conversion circuit 34. .

The color difference line sequential signal output from the line sequential conversion circuit 34 is input to the serial / parallel conversion circuit 41, and the serial line sequential signal is converted into a parallel line sequential signal. Then, the parallel line sequential signals are written in the memories 52, 53, 56 and 57.

Hereinafter, a method of writing data in the memories 50 to 57 and a method of reading data from the memories 50 to 57 will be described.
In this embodiment, since a wideband video signal is recorded in a small cassette for a long time, it can be said that the video signal is a redundant period. The signal is processed and recorded so that the horizontal and vertical blanking periods are minimized. FIG. 2 is a waveform diagram for explaining the blanking period removal method. FIG. 2 (1) is a waveform diagram of the input video signal. One field consists of 1 = 562.5 scanning lines, and the vertical blanking period is 58.5H (1H indicates one horizontal scanning period 29.63μs). Indicates that there is. In FIG. 2 (2), the video signal shown in (1) is divided into two channels, and the time axis is expanded about twice, the redundant vertical blanking period is removed, and one field is scanned with m = 261 lines. It shows that the vertical blanking period is 5H '(1H' indicates one horizontal scanning period 63.86 μs after signal processing).

Therefore, one horizontal scanning period H'after signal processing can be expressed by the equation (1) with the field frequency being _V.

Also, the time axis expansion rate e _H ′ during one horizontal scanning period after signal processing
Can be expressed by equation (2).

Regarding the sampling frequency _Y, it is necessary to satisfy the equations (3) and (4) because the sample phases of the input video signal and the video signal after the signal processing have to be the same in each line. _Y = _V × l × p (3) _Y = _V × m × c × q (4) Here, p and q are integers, and c represents the number of channel divisions. Specifically, if p = 1624 and q = 1750, then _Y = 54.81MH
It becomes z.

Next, FIG. 2 (3) is a diagram showing the waveforms of the luminance signal Y and the color difference signals C _W and C _N which are the output signals of the signal conversion circuit 10. Here, τ ₀ represents a horizontal blanking period, and τ ₁ represents an effective video period excluding the horizontal blanking period τ ₀ .

FIG. 2 (4) shows a waveform after dividing one channel into two channels, extending one horizontal scanning period twice, and further removing the vertical blanking period to set one horizontal scanning period to 1H '. The luminance signal is time-expanded to a times, the color difference signal is time-expanded to b times, and time-division multiplexed in the horizontal blanking period of the luminance signal time-expanded to a times. Furthermore, horizontal synchronization information of time τ _s is time-division multiplexed during the horizontal blanking period.

Therefore, the processing condition necessary to obtain the signal shown in FIG. 2 (4) is the expression (5).

1H ′ = aτ ₁ + bτ ₁ + τ _s (5) Here, the horizontal sync information has a negative polarity so that the sync information can be reliably separated at the time of reproduction and the signal restoration processing can be performed without a time axis error. It is composed of a synchronization signal and a time axis reference signal such as a burst signal.

As described above, by dividing the channel and removing the redundant horizontal and vertical blanking periods, it is possible to reduce the signal band per channel, and therefore it is possible to achieve long-time recording or miniaturize the cassette tape. .

In the signal band after two-channel division and time division multiplexing, the cutoff frequency of LPF20 is B _Y and the cutoff frequency of LPF21,22 is B _C Of these, the larger value can be represented. In VTR Of these, it is necessary to record up to the larger band, The recording efficiency can be improved by determining the extension rates a and b so that the values of the two become substantially equal. In the case of the specific example described above, And And can be made approximately equal.

The signal band per channel is 10.5 MHz, which is more than double the current TV signal band (4.2 MHz), only by dividing the two channels and removing the redundant horizontal and vertical blanking periods. In order to record a wideband video signal, the magnetic tape 102 and the magnetic heads 100,
01 relative speed needs to be increased. As a method of increasing the relative speed, a method of increasing the diameter of the drum on which the magnetic heads 100 and 101 are mounted, a method of increasing the rotational speed of the drum, and the like can be considered. Since the former method makes the apparatus larger, the case of using the latter method will be described.
In this case, since the signal of one field is recorded over a plurality of tracks, the signal becomes discontinuous at the track switching portion during reproduction, and so-called skew distortion occurs. Therefore, at the time of recording, a period for head switching is provided for recording to remove skew distortion, and at the time of reproduction, the head is switched within the head switching period, and the head switching period is removed to remove skew distortion. You can

In FIG. 2 (2), the head switching period is indicated by diagonal lines. This figure shows an example of recording one field by dividing it into three segments. In the case of segment recording, the segment ID signal and achromatic level of the color difference signal may be inserted for each segment as necessary, and 2H 'is allocated including these signal periods and the head switching period. And

The above signal processing can be performed as follows.

When the video signal band is widened like a high-definition television signal, the sampling frequencies _{Y 1} and _{C 2} are high, so that it is difficult to write and read from one memory chip at the same time. In order to write and read at the same time, it is necessary to increase the number of divided phases of parallel conversion of the serial / parallel conversion circuits 40 and 41 and reduce the data transmission rate. Therefore, the number of memory chips increases in proportion to the number of phases of the parallel signal.

In the present invention, data is written in two memories per channel for one phase of the serial / parallel conversion circuits 40 and 41. That is, the output digital luminance signal of the serial / parallel conversion circuit 40 is line by line in the memory 50 (51) and the memory 54.
Alternately input to (55).

3 and 4 are diagrams showing the relationship between the addresses of the memories 50 to 57 and the stored line numbers. In Figure 3, memory
Reference numerals 50 and 51 represent the luminance signal memory of channel 1,
Each corresponds to the memories 50 and 51 in FIG. Memory 54,55
Shows the memory for the luminance signal of channel 2, which corresponds to the memories 54 and 55 in FIG. 1, respectively. Here, the side recorded by the magnetic head 100 in FIG. 1 is referred to as channel 1, and the side recorded by the magnetic head 101 is referred to as channel 2.

That is, each line is alternately written into the memories 50 and 54, and a line for one field except for the vertical blanking period is written. Then, in the next field, the lines are alternately written into the memories 51 and 55. Specifically, as shown in FIG. 3, the memory 50 has Y1, Y3, ..., Y503, and the memory 54 has Y2, Y4 ,.
4 is written, then Y56 is stored in memory 51 in the next field.
3, Y565, ..., Y1065, Y564, Y566, Y1066 are written in the memory 55.

Similarly, the memories 52 and 53 in FIG. 4 are memories for the color difference signal of channel 1, and correspond to the memories 52 and 53 in FIG. 1, respectively. Memories 56 and 57 are color difference signal memories of channel 2, and correspond to the memories 56 and 57 of FIG. 1, respectively.

The color difference signals are alternately written in the memories 52 and 56 every two lines. That is, the data CW is stored in the addresses 1 and 2 of the memory 52 shown in FIG.
1, CN2, then data CW3,
CN4 is written. After the lines for one field except the vertical blanking period are sequentially written, the lines are sequentially written in the memories 53 and 57 every two lines in the same manner.

When the number of phase divisions of the serial / parallel conversion circuits 40 and 41 is P _Y and P _C respectively, the write clocks to the memories 50, 51, 54 and 55 are And the write clock to the memory 52,53,56,57 is Becomes

As shown in FIG. 4, the color difference signals are distributed to channel 1 and channel 2 for every two lines for the following reason. Since the color difference signals are recorded line-sequentially, the wide band color difference signals C _W and the narrow band color difference signals C _N appear alternately. Therefore, if these are alternately distributed among the channels, the color difference signal C _W is recorded in one channel and the color difference signal C _N is recorded in the other channel, and the color difference signal C _W is recorded from only one channel due to dropout or the like. If the reproduction signal cannot be obtained over the period, the color signal cannot be restored. By distributing the color difference signals for every two lines, the color difference signals C _W and
C _N can be recorded, and even when a reproduction signal cannot be obtained from only one channel for a long period of time, it is possible to compensate for a signal missing from a signal on an adjacent line.

Then, the reading of the memories 50 to 57 is performed as follows. That is, in FIGS. 3 and 4, the memories 50, 54 (52,
In the field where 56) is in the write state, memories 51, 55 (5
Read from the memory 51, 55 (53, 57) in the field where the memory 50, 54 (52, 56) is in the writing state.

Further, the read clock signal frequency at this time is the luminance signal,
Depending on the time base expansion rate of the color difference signal, the readout clock of the luminance signal is The color difference signal read clock is Becomes

Further, the read control of the luminance signal and the color difference signal is performed based on the read control signal (not shown) of the memories 50 to 57 created by the control signal generation circuit 121.

The signals read from the memories 50 and 51 are input to the selection circuit 60, and the luminance signal which is alternately selected for each field and recorded in channel 1 is output from the selection circuit 60. Selection circuit 60
Is output to the parallel / serial conversion circuit 70, and the input parallel data is input to the selection circuit 80 after being converted into serial data. Similarly, memory 52,53
Is output to the selection circuit 80 via the selection circuit 61 and the parallel / serial conversion circuit 71. Output of memories 54 and 55,
The outputs of memories 56 and 57 are selection circuits 62 and 63
It is input to the selection circuit 81 via the serial conversion circuits 72 and 73.

Further, the selection circuits 80 and 81 are supplied with the synchronization information S composed of the above-described negative polarity synchronization signal and burst signal. The synchronization information S is generated by the control signal generation circuit 121 and is output at the timing shown in FIG. 2 (4) for the luminance signal and the color difference signal.

The digital video signals selected by the selection circuits 80 and 81 and output as shown in FIG. 2 (4) and divided into two channels are input to DA conversion circuits 90 and 91, respectively, and converted into analog signals. FM signal processing circuit 92,93, recording amplifier 94,9
5, magnetic tape through the magnetic head 100,100 ', 101,101'
Stored in 102.

Here, the FM signal processing circuits 92 and 93 are configured by circuits used for normal FM recording, and specifically, are configured by a clamp circuit, a pre-emphasis circuit, an FM modulation circuit and the like.

As described above, the signals shown in FIGS. 2 (2) and 2 (4) are recorded on the magnetic tape 102. At this time, the head switching period shown by the hatched portion in FIG. 2 (2) is recorded within the overlap period in which the magnetic heads 100, 100 '(101, 101') facing each other simultaneously contact the magnetic tape 102. However, the head switching period fluctuates within the overlap period due to uneven rotation of the cylinder. If the rotation unevenness is large due to the control characteristics of the rotation of the cylinder, the head switching period may deviate from the overlap period. This is not only for segment recording but also for head switching in the case of the present embodiment in which the vertical blanking period is minimized even when the cylinder diameter is increased and recording is performed in one field per track. When the period is short and the rotation unevenness of the cylinder is large, the head switching period may deviate from the overlap period. If the head switching period deviates from the overlap period, the video signal may be lost or discontinuous, resulting in significant image quality deterioration.

Therefore, the magnetic heads 100, 10 input from the terminal 110 are input.
The tack signal indicating the rotational phase of 0 ', 101, 101' is shaped by the waveform shaping circuit 111, delayed by the delay circuit 112, and then input to the control signal generation circuit 121. Delayed tack signal S
According to T, the read control signals of the memories 50 to 57 and the synchronization information are generated. That is, when the delayed tack signal ST is input, reading from the memories 50 to 57 is started, and 1/3 of one field is read.
The temporary reading is stopped when the number of lines corresponding to 1 segment is read, a no signal period is provided for the head switching period, and the reading of the memories 50 to 57 is started when the delayed tack signal ST is input again. To do.

By the above operation, the head switching period can be surely provided within the overlap period. This method corrects fluctuations on the tape pattern caused by uneven rotation of the cylinder by expanding and contracting the head switching period. As a result, the recording / reproducing process can be reliably performed even if the vertical blanking period is minimized.

Further, in the present embodiment described with reference to FIGS. 1 to 4, it is sufficient for the memories 50 to 57 to store the effective video signal portion except the vertical blanking period in one field period of the video signal. By using a memory having a capacity, it is possible to correct a time variation caused by uneven rotation of the cylinder over a wide range.

That is, in FIG. 2 (1) and (2), the field ₁
Immediately after the data of is written in the memory 50, 52, 54, 56,
The data in the field ₃ may be read from the memories 50, 52, 54 and 56 as shown in FIG. 2 (2) before the writing of the data to the memories 50, 52, 54 and 56 is started. Therefore, if the vertical blanking period of the input video signal is l _V H and the vertical blanking period after signal processing is m _V H ', the maximum l _V H + m _V H'
It is possible to correct up to the time axis fluctuation. Home VT
In R, there is generally a time axis variation of about several H to several tens of H, but it can be seen that this value can be sufficiently obtained by this method. Moreover, according to the present embodiment, it is possible to configure the minimum number of memory chips, that is, two memory chips per channel per phase.

Further, with the same configuration as that of the embodiment shown in FIG.
The same effect as described above can be obtained by configuring 57 with a memory having a capacity half that of the effective video signal portion in one field. However, in this case, the correction range for the time variation is reduced.

FIG. 5 shows writing when using a memory having a capacity of 1/2 of the effective video signal portion in one field as the memories 50 to 57,
It is a timing diagram which shows a read timing. FIG. 5 (1) shows the write / read timing of the memory 50 (or 52, 54, 56) and FIG. 5 (2) of the memory 51 (or 53, 55, 57). In FIG. 5, W indicates a write timing and R indicates a read timing.

Field _1-1 (showing the first half of field ₁ ) is written to memory 50 and the field continues to memory 51.
_1-2 (indicate the second half of field ₁ ) is written. The first half of the field is written in the memory 50 and the second half of the field is written in the memory 51 in the following order. General reading starts from field _2-1 immediately after field _1-1 is written in memory 50.
Is read until writing is started. Further, the reading of the memory 51 is performed immediately after the writing of the field _1-2 and before the writing of the field _2-2 is started. However, since the vertical blanking period m _V H ′ after signal processing is shorter than the vertical blanking period l _V H of the input video signal, memory 50
_{If 1-1} reading is done until just before writing field _2-1 then _1-2 reading is done in memory 51.
It overlaps with the writing of _2-2 . Therefore, the margin for time fluctuation is at most m _V H.

In this embodiment, there is an effect that the memory capacity of the memories 50 to 57 can be reduced by half. This embodiment is effective when the rotation irregularity of the cylinder is relatively small. Further, the head switching period can be made long, which is particularly effective when it is not necessary to perform recording in synchronization with the rotational phase of the magnetic heads 100, 100 ', 101, 101'.

The memory capacity of the memories 50 to 57 is the same as in the embodiment shown in FIG. 2 when the memory capacity is an even multiple of 1/2 of the effective video signal portion in one field. Time variation correction similar to that of the embodiment shown in FIG. 5 can be performed.

An embodiment of a circuit for reproducing the signal recorded as described above is shown in FIG.

In FIG. 6, 200 to 203 are reproduction amplifiers, and 204, 205, 240.
~ 243,250,251 is a switching circuit, 210,211 is an FM demodulation processing circuit, 212,213 is a sync information separation circuit such as a negative sync signal or burst signal added at the time of recording, 214,215 is a write clock WCK generation circuit phase-synchronized with the separated sync information, 220 and 221 are AD conversion circuits, 222 and 223 are serial / parallel conversion circuits, 230 to 237 are memories, 252 and 253 are interpolation circuits for interpolating thinned lines when line-sequential conversion of color difference signals, and 260 to 262 are parallel and serial conversion circuits. , 263
265 is a DA conversion circuit, 266 is a signal conversion circuit for converting reproduced luminance signals and color difference signals into original three primary color signals, and 270 to 272 are output terminals of reproduced three primary color signals, 280
Is an input terminal of the reference clock RCK, 281 is a read address generation circuit of the memories 230 to 237, 282 is a synchronization signal generation circuit, 283
Is a horizontal sync signal HD output terminal, and 284 is a vertical sync signal output terminal.

The video signals reproduced by the magnetic heads 100, 100 ', 101, 101' from the magnetic tape 102 are input to the preamplifiers 200 to 203, amplified and then input to the switching circuits 204, 205.
The magnetic heads 100 and 100 ', 101 and 101' are arranged to face each other by 180 °. Therefore, every time the cylinder rotates 180 °, the video signal is alternately reproduced. According to the embodiment shown in FIG. 1, the head switching period is recorded within the overlap period, so that the switching circuit can be operated within the head switching period.
Reference numerals 204 and 205 perform switching processing of reproduction signals.

Output signals from the switching circuits 204 and 205 are input to the FM demodulation processing circuits 210 and 211, respectively, and FM demodulated. The FM demodulated video signals are input to AD conversion circuits 220 and 221, and synchronization information separation circuits 212 and 213, respectively. Sync information separation circuit 21
In 2,213, the negative sync signal and the burst signal added at the time of recording are separately output. The burst signal obtained here is input to the write clock generation circuits 214 and 215, and the write clock signal WCK phase-locked with the burst signal is obtained. Since the write clock signal WCK is phase-synchronized with the reproduced burst signal, it follows the jitter of the reproduced video signal in synchronization. Therefore, based on the write clock signal WCK, sampling is performed by the AD conversion circuits 220 and 221, converted to a digital signal, written to the memory, and read based on the stable reference clock signal RCK obtained by a crystal oscillator, etc. It is possible to remove the time axis fluctuation such as. The frequency of the write clock signal WCK is set to be twice the band of the reproduced video signal or more. Let the frequency be _-W . In the embodiment shown in FIG. 6, the AD conversion circuit 2
The outputs of 20,221 are input to the serial / parallel conversion circuits 222,223, converted to parallel data, and then stored in the memory 230.
~ 233 and memory 234 ~ 237. Memory 2 at this time
The write addresses of 30 to 233 and memories 234 to 237 follow the write address signals generated by the write address generation circuits 216 and 217 according to the write clock WCK generated by the write clock generation circuit 214.

Note that the number of phase divisions of the serial / parallel conversion circuits 222 and 223 is appropriately selected according to the writing and reading speeds of the memories 230 to 237, and is not always necessary in the case of a high speed memory.

Here, the luminance signal and the color difference signal of the channel 1 are stored in the memories 230 and 231 and the memories 232 to 233, and the memories 234 and 235 and the memory 23 are stored.
The luminance signal and the color difference signal of channel 2 are written in 6,237. Also, each of the two memories 230,231 (232 and 233,234 and 23
5, 236 and 237), the valid data of the video signal portion other than the vertical blanking period in one field period of the video signal are alternately written. And one memory 230
When (232, 234, 236) is in the writing state, writing and reading are reversed after one field is read from the other memory 231 (233, 235, 237). Incidentally, during the head switching period provided at the time of recording, the synchronous information is not written in the memories 230 to 237 but is continuously read from the memories 230 to 237 so that they are simultaneously removed.

FIG. 7 is a timing chart showing the memory processing situation. (1) shows the operating state of the memory 230 (232, 234, 236) and (2) shows the operating state of the memory 231 (233, 235, 237), W shows the writing state and R shows the reading state. Figure 2 (1),
Similar to the case described with reference to (2), there is a time margin of m _V H '+ l _V H in order that writing and reading do not overlap with respect to time variation. The time fluctuation at the time of reproduction also occurs due to uneven rotation of the cylinder, tape tension fluctuation, etc., and is a value within the range of several H to ten and several H, and this value can be sufficiently obtained in this embodiment. The number of memory chips is also 1
The phase can be minimized to two per signal.

The read addresses of the memories 230 to 237 are generated by the read address generation circuit 281 based on the stable reference clock RCK input from the terminal 280. The reading speed of the memories 230 to 237 depends on the luminance and color difference signals.
For the frequency _W of, the read clock of the luminance signal is a
_W , the read clock of the color difference signal is b _W. here
a and b are the expansion rates of the luminance signal and the color difference signal at the time of recording described above.

The data read by the memories 230 (232, 234, 236) and 231 (233, 235, 237) is input to the switching circuit 240 (241, 242, 243) and the memory on the read side is selected for each field. Furthermore, the outputs of the switching circuits 240 and 242 are input to the switching circuit 250, and the side from which data is output is alternately selected for each line. As a result, the original luminance signal data is output from the switching circuit 250.

On the other hand, the color difference signal data output from the switching circuits 241 and 243 is input to the switching circuit 251, and the color difference signal C _W is output to the interpolation circuit 2
At 52, the color difference signal C _N is input to the interpolation circuit 253. The interpolation circuits 252 and 253 restore the signals of the lines thinned by the line-sequential conversion during recording by interpolation. The outputs of the switching circuit 250 and the interpolation circuits 252 and 253 are input to the parallel / serial conversion circuits 260 to 262, respectively, and the parallel data are converted to serial data and then input to the signal conversion circuit 266 via the DA conversion circuits 263 to 265. It The signal conversion circuit 266 produces the three primary color signals R, G, B from the luminance signal Y and the color difference signals C _W , C _N, and outputs them from terminals 270, 271, 272, respectively.

Further, the reference clock RCK is input to the sync signal generation circuit 282, and the horizontal sync signal HD and the vertical sync signal VD are respectively input to the terminal 28.
It is output from 3,284.

As described above, the original three primary color signals R, G, B can be reliably reproduced and restored.

In the above embodiment, the memory capacity of the memories 230 to 237 has been described as a capacity sufficient to store an effective video signal in one field. However, like the recording system memory described in FIG. The same effect can be obtained by using a memory having a capacity sufficient to store 1/2 of the effective video signal. However, even in this case, the time variation margin is m _V H ′.
Will decrease. Generally, if the memory capacity is an odd multiple of 1/2 of the effective video signal in one field, the time variation margin is m _V H ', and if it is an even multiple, the time variation margin is l _V H + m _V H'. Becomes

FIG. 8 is a block diagram showing another embodiment of the present invention.
FIG. 8 is partially common with FIG. 1, and detailed description thereof will be omitted. In FIG. 8, reference numerals 50 ', 52', 54 'and 56' are memories. In the embodiment shown in FIG. 1, the luminance signal and the color difference signal are written in different memories, but in the embodiment shown in FIG. 8, the luminance signal and the color difference signal are written in the same memory. FIG. 9 shows the relationship between address signal data on the memory at that time.

When writing the luminance signal to the memory 50 ', the memory 5
When the color difference signal is written in 4'and the luminance signal is written in the memory 54 ', the color difference signal is written in the memory 50'. At this time, the memories 52 'and 56' are in the read mode. And 1
After the field, the relationship between writing and reading is reversed.

The line memories 30 and 31 are also used as buffer memories so that the writing of the luminance signal and the color difference signals does not overlap in the same memory, and the luminance signals and the color difference signals are stored in the memories 50 ', 52', 54 'and 56'. Control to write alternately.

According to this embodiment, the number of memories used can be further reduced.

It should be noted that the embodiments shown in FIGS. 1, 6, and 8 show the case of dividing into two channels, but the present invention can be applied to the case of dividing into one channel or three channels, In any case, the gist of the present invention is not deviated.

Further, in the embodiment shown in FIG. 5, the storage capacity of the memories 50 to 57 is 1/2 of the effective video signal of one field, but a pair of memories 50 and 51 (52 and 53, 54 and 55, 56 and 57),
The capacity of one memory 50 is set to the effective video signal of one field. The capacity of the other memory 51 is set to the effective video signal of one field. (Complex same order) is also possible. FIG. 10 is a timing chart showing an example thereof.

Fig. 10 (1) is effective video signal period of one field signal period for writing into the memory 50 of _{(l H -l V H) 1/2} ( indicated by a solid line)
It is a timing chart at the time of making it increase only from (DELTA) to (it shows by a dotted line). When the writing period to the memory 50 is increased by Δ,
The reading period Δ'from the memory 50 can be expressed by equation (6).

Further, the period τ _m during which the memory 50 is neither written to nor read in one field period can be expressed by equation (7).

As can be seen from FIG. 10 (1), if τ _m > Δ ′ + Δ, signal processing can be normally performed in the memories 50 and 51 without overlapping writing and reading. The time margin at this time is τ _m
It becomes − (Δ ′ + Δ).

FIG. 10 (2) is effective video signal period of one field signal period for writing into the memory 50 of _{(l H -l V H) 1/2} ( indicated by a solid line)
It is a timing chart at the time of decreasing from Δ to (displayed by a dotted line). Also in this case, if τ _m > Δ ′ + Δ, the memory 5
With 0 and 51, signal processing can be normally performed without overlapping writing and reading. The time margin at this time is τ _m −
(Δ ′ + Δ).

〔The invention's effect〕

According to the present invention, the horizontal blanking period and the vertical blanking period are minimized, and the luminance signal, the line-sequential color difference signal, and the synchronization information are divided into two channels and then time-division multiplexed, so that the signal band can be narrowed. it can. Furthermore, in order to perform the above signal processing, 1/2 of the effective video signal excluding the vertical blanking period in one field period of the video signal
By using two lines of memory to store integer multiples of
You can take a large margin against time fluctuations, and
The number of memories used can be minimized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a VTR recording system showing an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation thereof, and FIGS. 3 and 4 are memory addresses. FIG. 5 is a diagram showing the relationship of data, FIG. 5 is a timing diagram showing the timing of writing and reading of memory, FIG. 6 is a block diagram of a VTR reproducing system showing an embodiment of the present invention, and FIG. 7 is writing of memory. FIG. 8 is a schematic diagram showing the relationship between reading and reading, FIG. 8 is a block diagram of a VTR recording system showing another embodiment of the present invention, FIG. 9 is a diagram showing the relationship between memory addresses and data, and FIG. FIG. 6 is a diagram showing write and read timings when system memories have different capacities. 30,31 ...... Line memory 50 to 57,50 'to 56', 230 to 237 ...... Memory 112 ...... Delay circuit 121 ...... Control signal generation circuit 214,215 ...... Clock generation circuit 216,217 ...... Write address generation circuit 281 ... ... Read address generation circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masakazu Hamaguchi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Home Appliances Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-61-196407 (JP, A)

Claims (4)

[Claims] 1. A device for expanding or compressing a time axis by deleting or adding a part of a vertical blanking period included in a video signal, wherein the vertical blanking period of one field period of the video signal is There are two memories for storing video information in which one unit is an integer multiple of at least approximately 1/2 of an effective video signal portion excluding a part, and the above-mentioned video signal is stored in the two memories with a predetermined write clock. Means for alternately writing every unit, means for alternately reading the written signal from the two systems of memory at a predetermined read clock for each unit, and writing and reading of the two systems of memory. And means for controlling the timing,
An apparatus for processing a video signal, characterized in that reading is carried out from each of the memories of the two systems after completion of writing so that the memories of the two systems are not simultaneously written and read. 2. A helical scan type magnetic recording / reproducing apparatus for recording one field of the video signal by dividing it into g (g is a positive integer) tracks and recording the video signal. Means for detecting the rotational phase of the magnetic head, means for sequentially reading from the two systems of memories based on the output of the detection means, and two effective memories for the effective video signal in the one field period. An apparatus for processing a video signal according to claim 1, further comprising means for stopping the reading after reading 1 / g. 3. The video signal comprises a luminance signal and a color difference line sequential signal, and at least about 1 / th of an effective luminance signal portion except a part of the vertical blanking period in one field period of the luminance signal. Two systems of luminance signal memory for storing luminance information in which an integral multiple of 2 is set as one unit, and an effective color difference signal portion excluding a part of the vertical blanking period in one field period of the color difference line sequential signal. At least about 1/2
And a unit for alternately writing the luminance signal for each unit in a predetermined write clock in the luminance signal memories of the two systems for storing the color difference information in which the integral multiple of 1 is one unit. And means for alternately writing the color difference signals for each unit in the two-system color difference signal memories at a predetermined write clock, and the written signal at a predetermined read clock from the luminance signal memory for the unit. Means for alternately reading for each unit, means for alternately reading the written signal for each unit from the color difference signal memory at a predetermined read clock, the luminance signal memory, and the color difference signal memory Of the luminance signal memory and the color difference signal memory by reading after completion of writing from the respective luminance signal memory and color difference signal memory. Processor of the video signal of the claims paragraph 1, wherein the controller controls not to perform write and read at the same time in each of the memory for each and a color difference signal. 4. The video signal is divided into h (h is a positive integer) channels, and a part of the vertical blanking period in one field period of the video signal is excluded for each of the h channels. At least approximately 1 / of the effective video signal
Two memories for storing video information having an integral multiple of 2h as one unit, and means for alternately writing the above-mentioned video signal for each unit at a predetermined write clock in the two memories for each channel. Means for alternately reading the written signal for each unit from the two-system memory for each channel at a predetermined read clock, and means for controlling the writing and reading timing of the two-system memory for each channel. Wherein the two channels of the memory for each channel are read after the writing is completed and the two channels of the memory for each channel are controlled so that writing and reading are not performed simultaneously. A video signal processing device according to claim 1.