JPH0769863B2 - Data processing device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a data processing device, and more particularly to a memory access control method for a data processing device including a buffer storage device having a bypass buffer.

2. Description of the Related Art Conventionally, in this type of data processing device, by providing a bypass buffer in the buffer storage device, the block read data returned from the main storage device in response to a block read request at the time of a cache miss is temporarily stored. There is a method for storing the block read data in the bypass buffer and processing a subsequent memory access request first without waiting for the transfer of the block read data to the cache memory to speed up the processing at the time of a cache miss.

In this processing method, when the read request is a cache miss hit, until the first reply data of the block read data for the block read request to the main storage device corresponding to the read request is returned from the main storage device,
Subsequent memory access requests are suppressed.

At this time, the time from the transmission of the block read request to the main storage device to the return of the first reply data is used, and the read request which has become the cache miss hit before the read request becomes the cache miss hit. Thus, the data returned from the main storage device and stored in the bypass buffer is transferred to the cache memory.

In such a conventional data processing device, when a read request is a cache mishit, subsequent memory access requests are always suppressed until the requested block read data is returned from the main storage device. It is necessary to wait for the block read data to be returned as many times as the number of cache misses occur, and there is a drawback that the performance in the case of continuously making block read requests to the main storage device is significantly reduced.

SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks of the related art, and a data processing device capable of reducing the waiting time for returning block read data and the waiting time for a memory access request. For the purpose of providing.

According to the data processing device of the present invention, when a read request from a higher-level device results in a cache miss, the block data transferred from the main storage device is temporarily stored in the bypass buffer and then written to the cache memory. And a consecutive data read request results in a cache mishit,
Sending means for continuously sending the first and second block read requests to the main storage device corresponding to the first and second read requests, and the first and second block read by the sending means. When the requests are continuously transmitted, the block data transferred from the main storage device by the first block read request is written into the cache memory by bypassing the bypass buffer,
And a means for controlling the block data transferred from the main storage device by the second block read request to be temporarily stored in the bypass buffer and then written in the cache memory.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, request code register (MQR) 1
A request code transmitted from a memory access request source (not shown) (not shown) via a signal line 100 is held in the column. This request code includes the type of memory access request, the instruction content, and the validity.

The request code held in the request code register 1 is sent to the request code register 2 via the signal line 102.
To the cache access control circuit 16 and the memory access control circuit 17, respectively.

The request code register 2 holds the request code sent from the request code register 1, and sends the request code to the cache access control circuit 16 and the memory access control circuit 17 via the signal line 103, respectively.

The request address register (PAR) 3 holds the request address sent from the request source via the signal line 101. The request address held in the request address register 3 is transferred via the signal line 104 to the request address register 4 and the block address register (CB
A) 8, the detection circuit 15, and the memory access control circuit 17, respectively.

Of the request addresses held in the request address register 3, the key address is sent to the address array 5 and the detection circuit 6 via the signal line 105, and the set address is supplied to the address array 5 via the signal line 106. . That is, the key address stored in the address array 5 is read by this set address.

Further, the block address composed of the key address and the set address is sent to the detection circuit 11 via the signal line 107.

The request address register 4 holds the request address sent from the request address register 3, and sends the request address to the detection circuit 15 and the memory access control circuit 17 via the signal line 108, respectively.

Of the request addresses held in the request address register 4, the data array address is the signal line 10
9 is sent to the switching circuit 9 via 9 and the data array address in the block is sent via the signal line 110 to the bypass buffer 1
Supplied to 3. That is, the block read data from the main memory device stored in the bypass buffer 13 is read by the in-block data array address.

The address array 5 is an address portion of the cache memory, and stores the correspondence between the blocks registered in the cache memory and the blocks of the main storage device (not shown). The key address stored in the address array 5 is read by the set address from the request address register 3 and sent to the detection circuit 6 via the signal line 111.

The detection circuit 6 compares the key address from the request address register 3 and the key address from the address array 5, and the comparison result is an FDB (found block) signal via the signal line 112 through the cache access control circuit 16 and the memory access. It is output to the control circuit 17, respectively.

The switching circuit 7 switches between block read data input from the main memory device via the signal line 119 and block data input from the bypass buffer 13 via the signal line 120, and outputs the data to the signal line 113. To the data array 10 via.

The block address register 8 holds the request address sent from the request address register 3. That is, the block address register 8 holds the address of the block read data from the main storage device registered in the bypass buffer 13. The block address of the request addresses held in the block address register 8 is detected by the detection circuit 11 via the signal line 114.
And the data array address is sent to the switching circuit 9 via the signal line 115.

The switching circuit 9 switches between the data array address from the request address register 4 and the data array address from the block address register 8 and supplies the data array address to the data array 10 via the signal line 116.

The data array 10 is the data section of the cache memory,
Part of the data stored in the main storage device is stored. Further, the data stored in the data array 10 is read by the data array address from the switching circuit 9,
It is sent to the switching circuit 14 via the signal line 117.

The detection circuit 11 compares the block address from the request address register 3 with the block address from the block address register 8, and the comparison result is used as a bypass buffer match signal via the signal line 118 to bypass buffer control unit 12 and cache access control. It is output to the circuit 16.

The bypass buffer 13 stores the block read data sent from the main storage device via the signal line 119. The block read data stored in the bypass buffer 13 is read by the in-block data array address from the request address register 4 and sent to the switching circuits 7 and 14 via the signal line 120, respectively.

The switching circuit 14 stores the data read from the data array,
The block read data read from the bypass buffer 13 and the block read data sent from the main memory device are switched, and the data is sent to the request source via the signal line 121.

The detection circuit 15 compares the request addresses held in the request address registers 3 and 4, respectively, and the comparison result is output as a match signal to the cache access control circuit 16 and the memory access control circuit 17 via the signal line 122.

The cache access control circuit 16 and the memory access control circuit 17 decode the request code sent from the request code register 1 and generate and distribute a control signal to each circuit (control signal lines to each circuit are not shown. No).

When the request code register 1 receives the read request from the request source, the cache access control circuit 16 checks the FDB signal from the detection circuit 6 and the bypass buffer match signal from the detection circuit 11 and receives them in the request address register 3. When the FDB signal from the detection circuit 6 for the request address of the read request is on, that is, the key address from the request address register 3 and the key address read from the address array 5 match and the data designated by the request address is Cache access control circuit that exists in cache memory
When notified to 16 and the memory access control circuit 17, the bypass buffer match signal from the detection circuit 11 is referred to.

When the bypass buffer match signal from the detection circuit 11 is off, that is, when the block address from the request address register 3 and the block address from the block address register 8 do not match, the data array address from the request address register 4 Is supplied to the data array 10 via the switching circuit 9, whereby the data read from the data array 10 is returned to the request source via the switching circuit 14.

If the bypass buffer match signal from the detection circuit 11 is on, that is, if the block address from the request address register 3 and the block address from the block address register 8 match, the block from the request address register 4 The data read from the bypass buffer 13 by the data array address is returned to the request source via the switching circuit 14.

When the FDB signal from the detection circuit 6 for the request address received in the request address register 3 is off, that is, when the key address from the request address register 3 and the key address read from the address array 5 do not match. The memory access control circuit 17 outputs the main memory request code to the main memory device via the signal line 125 and the main memory request address via the signal line 126, respectively, thereby sending a block read request to the main memory device. To be done.

On the other hand, until the block read data is returned from the main memory device, the key address of the request address held in the request address register 3 is registered in the entry of the address array 5, and the request address is stored in the block address register 8. be registered.

At this time, since the request address of the request address register 3 has been transferred to the request address register 4, the request address register 4 keeps the request address until the first block read data is returned from the main memory. Is retained.
Similarly, the request code register 2 holds the request code transferred from the request code register 1 until the first block read data is returned from the main storage device.

When valid data exists in the bypass buffer 13, the data in the bypass buffer 13 is transferred to the data array 10 by using the period until the first reply data is returned from the main storage device. In this case, when the data in bypass buffer 13 is read from the main memory device, the data array address held in block address register 8 is supplied to data array 10 via switching circuit 9.

Here, the block read request sent from the memory access control circuit 17 is a transfer request for one block of the main storage device, and in the present embodiment, one block has a size of 128 bytes and the data with the main storage device is transferred. With a transfer width of 16 bytes or the like, reply data from the main storage device is returned 16 times in 16-byte units.

At this time, the requested 16-byte data of one block of data is sent from the main memory as the first reply data.

For example, as shown in FIG. 3, when the fourth data "3" is requested from the reply data of one block from the main memory, the data "3" → the data "4" is requested from the main memory. The reply data is transmitted in the order of → data '5' → data '6' → data '7' → data '0' → data '1' → data '2' and sequentially registered in the bypass buffer 13.

Therefore, the transfer of data from the bypass buffer 13 to the data array 10 is performed in the same order as above.

The first reply data from the main storage device is registered in the bypass buffer 13 and returned to the request source via the switching circuit 14. Further, the reply data from the second time onward is registered in the bypass buffer 13.

As described above, the read request from the request source is processed. However, when there are continuous read requests from the request source, first, the first read request (request code register 1 and request address register 3) (request code And the request address), the cache access control circuit 16 checks the FDB signal from the detection circuit 6.

When this FDB signal is off, a block read request is sent from the memory access control circuit 17 to the main memory, the request code of the read request is held in the request code register 2, and the request address is the request address register. 4 and block address register 8.

At this time, the cache access control circuit 16 uses the request code register 1 and the request address register 3
It is detected whether or not there is a subsequent access request, and when there is no subsequent access request, the request acceptance inhibit signal sent to the request source via the signal line 123 is turned on, and the 1 The acceptance of subsequent access requests is suppressed until the reply data for the second time is returned.

If a subsequent access request exists in the request code register 1 and the request address register 3, the cache access control circuit 16 checks the type of the access request, and if the access request is other than the read request, the request code register 1 And the execution of the access request is waited in the request address register 3 until the first reply data is returned from the main memory.

If the access request is a read request, the cache access control circuit 16 checks the FDB signal from the detection circuit 6 and the bypass buffer match signal from the detection circuit 11.

When either one of the FDB signal and the bypass buffer match signal is on, execution of the read request is waited until the first reply data is returned from the main memory.

When the first reply data is returned from the main memory, the request address held in the request address register 3 is transferred to the request address register 4, so if the FDB signal is on, the request address The data is read from the data array 10 by the data array address from the register 4, and the switching circuit 14
Return to the requester via.

When the bypass buffer match signal is on, the data is read from the bypass buffer 13 by the in-block data array address from the request address register 4 and returned to the request source via the switching circuit 14.

When both the FDB signal and the bypass buffer match signal are off, the cache access control circuit 16 checks the match signal from the detection circuit 15 and holds the request address existing in the request address register 3 and the request address register 4. Check for a match with the request address.

When the coincidence signal from the detection circuit 15 is ON, the read request is a request for the same block address as the first read request, and therefore the read request is executed for the first time from the main memory device. Wait until the data is returned. After that, the reply data from the main storage device is registered in the bypass buffer 13 and then read and returned to the request source through the switching circuit 14, or the bypass buffer 13 is bypassed and the request source is passed through the switching circuit 14. Return to.

When the coincidence signal from the detection circuit 15 is OFF, the block read request is sent from the memory access control circuit 17 to the main memory device after the first read request.

At this time, the cache access control circuit 16 turns on the request acceptance inhibit signal for the request source, and accepts subsequent access requests until the first reply data from the main memory for the second read request is returned. Deter.

Further, since the memory access control circuit 17 continuously sends block read requests to the main storage device, it indicates that block read requests are continuously sent.
And the cache access control circuit 16 via the signal line 124
Turn on the display signal output to.

In this case, when the first reply data is returned from the main storage device in response to the first read request, the reply data is returned from the main storage device in response to the second read request. Since the first reply data is not registered in the bypass buffer 13, it bypasses the bypass buffer 13 and is returned to the request source via the switching circuit 14, and the data array 10 is also sent via the switching circuit 7. Register with. The second and subsequent reply data are also bypassed by the bypass buffer 13 and registered in the data array 10 via the switching circuit 7.

A normal operation is performed for reply data from the main storage device in response to the second read request, and
The reply data of the second time is registered in the bypass buffer 13, and is returned to the request source via the switching circuit 14,
The reply data after the second time is registered in the bypass buffer 13.

FIG. 2 is a time chart showing an operation when both consecutive read requests result in a cache miss in one embodiment of the present invention.

The operation when both consecutive read requests result in a cache miss in one embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

When there are continuous read requests from the request source, both the FDB signal from the detection circuit 6 and the bypass buffer match signal from the detection circuit 11 for these read requests are off and the match signal from the detection circuit 15 If is also OFF, the block read requests corresponding to these read requests are continuously transmitted from the memory access control circuit 17 to the main memory device.

At this time, the request code register 1 holds the request code of the read request, and the request code register 2 holds the request code of the read request. The request address register 3 holds the request address of the read request, and the request address register 4 holds the request address of the read request.

Further, the cache access control circuit 16 turns on the request acceptance inhibition signal for the request source and accepts subsequent access requests until the first reply data b1 from the main memory for the second read request is returned. Deter.

At this time, since the memory access control circuit 17 continuously sends block read requests to the main memory,
A display signal to the cache access control circuit 16 indicating that block read requests are continuously transmitted is turned on.

In this case, when the first reply data a1 is returned from the main memory in response to the first read request, 2
Since it is clear that the reply data b1 to b8 are returned from the main memory in response to the second read request,
The first reply data a1 is not registered in the bypass buffer 13 but bypasses the bypass buffer 13 to switch the circuit.
The data is returned to the request source via 14 and registered in the data array 10 via the switching circuit 7. The second and subsequent reply data a2 to a8 are also bypassed by the bypass buffer 13 and registered in the data array 10 via the switching circuit 7.

Normal operation is performed on the reply data b1 to b8 from the main memory device by the second read request, and the first reply data b1 from the main memory device is the bypass buffer 13
The reply data b2 to b8 from the second time onward are registered in the bypass buffer 13 while being returned to the request source via the switching circuit 14.

When the first reply data b1 is returned from the main storage device in response to the read request, the cache access control circuit 16 releases the request acceptance inhibition signal to the request source, and the access request from the request source can be accepted. .

When the FDB signal from the detection circuit 6 for this access request is ON, the data c is read from the data array 10 and returned to the request source via the switching circuit 14. Bypass buffer while this access request is being processed
Reply data b2 to b8 from the main storage device in response to the read request are registered in 13.

That is, as shown in FIG. 4B, when block access requests corresponding to read requests are continuously sent from the memory access control circuit 17, as shown in FIG. Compared to the case where the block read request corresponding to the read request is sent after the first reply data for the block read request corresponding to the request is transferred from the main storage device, 1 for the block read request corresponding to the read request is sent. Time T3, which is the sum of the transfer time T1 of the first reply data and the access time T2 of the block read request corresponding to the read request to the main memory, and the timing for returning the first reply data to the block read request corresponding to the read request. Can be faster.

Therefore, it is possible to reduce the return waiting time of the access request until the first reply data for the block read request corresponding to the read request is returned, and to shorten the memory access waiting time of the access request.

Thus, when both consecutive read requests result in a cache miss, the memory access control circuit
Block read requests corresponding to these read requests are continuously sent from the main memory device 17 and the reply data transferred from the main memory device by the block read request corresponding to the read request is bypassed to the bypass buffer 13. By directly writing to the data array 10 and temporarily storing the reply data transferred from the main storage device by the block read request corresponding to the read request in the bypass buffer 13 and then writing to the data array 10, the subsequent process is performed. It is possible to reduce the waiting time for returning reply data from the main storage device in the access request and shorten the memory access waiting time.

Therefore, it is possible to improve the performance when the block read requests are continuously issued to the main storage device.

EFFECTS OF THE INVENTION As described above, according to the present invention, the main storage device corresponding to the first and second read requests when both consecutive first and second read requests result in a cache miss. Continuously send first and second block read requests to the cache memory, and write the block data transferred from the main storage device by the first block read request to the cache memory by bypassing the bypass buffer.
By temporarily storing the block data transferred from the main storage device in response to the second block read request in the bypass buffer and then writing the block data in the cache memory, the waiting time for returning the block data is reduced and the memory access This has the effect of reducing the waiting time for requests.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention, and FIG. 2 is a time chart showing an operation when both consecutive read requests result in a cache miss in the embodiment of the present invention. FIG. 4 is a diagram showing the registration order of reply data in the bypass buffer of FIG. 1, and FIG. 4 is a schematic time chart showing the memory access operation of the memory access control circuit of FIG. Explanation of main part code 1,2 ...... Request code register 3,4 ...... Request address register 5 ...... Address array 6,11,15 ...... Detection circuit 7,9,14 ...... Switching circuit 8 ...... Block address Register 10 …… Data array 13 …… Bypass buffer 16 …… Cache access control circuit 17 …… Memory access control circuit

Claims (1)

[Claims] 1. A data processing device in which, when a read request from a higher-level device results in a cache mishit, block data transferred from the main storage device is temporarily stored in a bypass buffer and then written to the cache memory. Then, when both the consecutive first and second read requests result in a cache miss, the first and second read requests are made.
Sending request for continuously sending the first and second block read requests to the main storage device corresponding to the read request, and the sending means continuously sending the first and second block read requests. Then, the block data transferred from the main memory device by the first block read request is written into the cache memory by bypassing the bypass buffer, and the block data is transferred from the main memory device by the second block read request. And a means for controlling so that the transferred block data is temporarily stored in the bypass buffer and then written in the cache memory.