JPH0769802B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a data processing device which realizes high processing capacity by an advanced pipeline processing mechanism.

[Prior Art] As a prior art, there is a stack pointer circuit shown in Japanese Patent Application No. 62-145852.

FIG. 33 is a block diagram of a conventional stack pointer calculator. The data processing device shown in the conventional example executes an instruction by pipeline processing and executes an instruction fetch stage (IF
Stage), instruction decode stage (D stage), operand address calculation stage (A stage), operand fetch stage (F stage), and execution stage (E stage). 61 is a stage stack pointer (AS
P), 62 is an ASP output latch, and 63 is a stage stack pointer (FS) managed by the operand fetch stage.
P), 64 is the FSP output latch, 65 is the stage stack pointer (CSP) managed by the execution stage, 66, 67, 68
Is the stack pointer (SP
I, SP0, SP1).

Figure 34 shows an instruction that includes stack push, for example, the MOV instruction (MOV: R that writes the register value to the stack top (where the value decremented the stack pointer value points).
n-> @-SP Rn represents the nth register, and @ -SP represents the address indicated by the value obtained by decrementing the stack pointer.) is a flowchart showing the operation of the stack pointer in each stage. ASP 61 before command execution
It is assumed that the value of is the initSP and that it is consistent with the stack pointer value at the time of the end of the instruction immediately before this instruction.

First, since the source of this instruction is a register, the register designation signal is sent to the next stage F stage in the A stage. The value of ASP61 is decremented (initSP-4), and the value of ASP61 decremented in synchronization with the flow of instructions (ini
tSP-4) is transferred to FSP63.

The F stage receives the register designation signal and sends a register access signal to the next E stage. When the instruction reaches the E stage, the value of FSP63 (initSP-4) is also sent to the CSP65 of the E stage at the same time.

At the E stage, the instruction is executed using the value of CSP65 (initSP-4) as the destination address. That is, the value of the specified register is written to the data register, and the CSP61
The value of is written to the address register, and the value of the data register is stored at the address indicated by the address register.

Regarding SPI 66, SP0 67, and SP1 68, these stack pointers retain the previous values during instruction execution, and at the end of the processing of each instruction, the CSP65 value is the stack pointer (SPI , SP0, SP1).

Figure 35 shows the case of an instruction that loads data by looking at the stack pointer as a general-purpose register (MOV: "100"-> SP "10.
0 "is an immediate value, SP is a stack pointer).

In the A stage, the immediate value "100" is sent to the next F stage. ASP61 is transferred unchanged to FSP63.

In this instruction, stack pointer of A stage (ASP61)
The value of is kept at the previous value until the instruction ends and the value is written to the stack pointer, so if the later instruction is an instruction that refers to the stack pointer (when a conflict regarding the stack pointer occurs). , If you calculate the address by referring to ASP61, an incorrect value will be generated. Therefore, the stack pointer write reservation is made until the instruction ends and the stack pointer value is rewritten, and when the subsequent instruction refers to the stack pointer, A is written until the write reservation is released. Waiting without performing address calculation on stage. Then, after the write reservation is released, the address calculation in the A stage is started.

In the F stage, the immediate value "100" is received and it is "100" as it is.
To the next E stage.

FSP63 is transferred to CSP65.

At the E stage, the data “100” is ASP6 through the DO bus 85.
It is written to 1, CSP65 at the same time.

If the instruction after this instruction references the stack pointer, the stack pointer (ASP61), which is the resource at the A stage, has not been rewritten, and the stack pointer cannot be referenced, so the address is calculated. I'm waiting on the A stage. Then, when the write reservation is released and the address calculation is started, the correct value is
Since it is in ASP61, it has the correct stack pointer value when it reaches the E stage, and that value is written to either SPI 66, SP0 67, or SP1 68.

However, if the subsequent instruction does not use the stack pointer, it is not necessary to wait without performing address calculation in the A stage even if the stack pointer is reserved for writing. Therefore, the previous instruction is processed in E stage and AS
By the time P61 is rewritten, the processing in the address calculation stage or the operand fetch stage may have already been completed. This would cause the instruction to reach the execute stage with an incorrect stack pointer value, which would transfer the incorrect value to the CSP65, and at the end of the instruction the incorrect value to either SPI 66, SP0 67, or SP1 68. Will be written.

Therefore, in order to avoid this, when the value of the stack pointer is rewritten in the E stage, all stage stacks must be set so that the stage stack pointer of the stage in which each instruction is processed always indicates the value associated with that instruction. Either write a value to the pointer and each stack pointer output latch at the same time, or make sure that the next instruction always stops at the address calculation stage when the stack pointer is reserved for writing, and the value of ASP61 is rewritten. Then, the next instruction must start processing in the A stage 33.

[Problems to be Solved by the Invention]

As described above, in the conventional stack pointer processing during pipeline processing, when the stack pointer value is updated in the execution stage, the value of the stage stack pointer of the execution stage is attached to the instruction when the next instruction is executed. In order to obtain the correct value, there is a problem that it is necessary to write the values to all the stage stack pointers and the stage stack pointer output latches, or be sure to stop the next instruction at the address calculation stage.

The present invention has been made to solve the above-mentioned problems. Even when the instruction next to the instruction that rewrites the value of the stack pointer in the execution stage with less hardware does not cause a conflict regarding the stack pointer,
It is an object to obtain a data processing device which manages a stack pointer correctly without stopping the instruction at the address calculation stage.

[Means for Solving the Problems]

The data processing device according to the present invention is provided with a stage stack pointer for work in the address calculation stage in the pipeline, and updates the updated value only when the stack pointer managed in the address calculation stage is updated in the address calculation stage. Transfer to the stack pointer managed by the execution stage.

[Action]

The data processor according to the present invention executes the value of the stack pointer in synchronization with the instruction flow in the pipeline only when the stage stack pointer (ASP) of this stage is updated at the time of address calculation in the address calculation stage. It is transferred to the stack pointer managed by.

Example of Invention

Hereinafter, the present invention will be described in detail with reference to the drawings showing an embodiment thereof.

(1) "Instruction format of data processing device of the present invention" The instruction of the data processing device of the present invention has a variable length in units of 16 bits, and an instruction of odd byte length is not used.

The data processing apparatus of the present invention has an instruction format system devised especially for the purpose of making a high-frequency instruction into a short format. For example, with respect to a two-operand instruction, it has a general format of "4 bytes + extended part" and all addressing modes can be used, and only frequently used instructions and addressing modes can be used. There are two formats, a shortened format.

The meanings of the symbols appearing in the instruction format of the data processor of the present invention are as follows.

-: Operation code entry part #: Literal or immediate value entry part Ea: Part that specifies operand in 8-bit general addressing mode Sh: Part that specifies operand in 6-bit compact addressing mode Rn: Register In the partial format in which the upper operand is designated by the register number, the right side is the LSB side and the high address as shown in FIG. Address N and address N +
The instruction format cannot be identified unless the 2 bytes of 1 are seen.
This is because it is premised on fetching and decoding in units of 16 bits (2 bytes = halfword).

In the data processor of the present invention, the extension of Ea or Sh of each operand is always
It is located immediately after the halfword containing the base of Ea or Sh. This takes precedence over immediate data implied by the instruction or the extension of the instruction. Therefore, for an instruction of 4 bytes or more, the operation code of the instruction may be divided by the extension part of Ea.

Further, as will be described later, even when the extension part of Ea is further provided with the extension part by the multistage indirect mode, that part has priority over the next instruction operation code. For example, consider the case of a 6-byte instruction that includes Ea1 in the first halfword, Ea2 in the second halfword, and up to the third halfword. Since the multistage indirect mode is used for Ea1, assuming that a multistage indirect mode extension is added in addition to the normal extension, the actual instruction bit pattern is the first halfword of the instruction (including the basic part of Ea1), The extension part of Ea1, the multi-stage indirect mode extension part of Ea1, the second halfword of the instruction (including the basic part of Ea2), the extension part of Ea1, and the third halfword of the instruction are in this order.

(1.1) "Short form 2-operand instruction" FIGS. 4 to 7 are schematic diagrams showing a short form of a 2-operand instruction.

FIG. 4 is a schematic diagram showing a format of a memory-register operation instruction. This format includes an L-format in which the source operand side is a memory and an S-format in which the destination operand side is a memory.

In the L-format, Sh represents the designation field of the source operand, Rn represents the designation field of the register of the destination operand, and RR represents the designation of the operand size of Sh. The size of the destination operand located in the register is fixed at 32 bits. When the size of the register side is different from that of the memory side and the size of the source side is small, sign extension is performed.

In S-format, Sh represents the designation field of the destination operand, Rn represents the register designation field of the source operand, and RR represents the designation of the operand size of Sh. The size of the source operand located on the register is fixed to 32 bits. When the size of the register side is different from that of the memory side and the size of the source side is large, the overflow portion is truncated and the overflow check is performed.

FIG. 5 is a schematic diagram showing a format (R-format) of a register-register arithmetic instruction. Rn is a designation field of the destination register, and Rm is a designation field of the source register. Operand size is only 32 bits.

FIG. 6 is a schematic diagram showing the format (Q-format) of a literal-memory operation instruction. MM is a destination operand size specification field, ## is a literal source operand specification field, and Sh is a destination operand specification field.

Figure 7 shows the format of the immediate-memory operation instruction (I-fo
FIG. MM is an operand size specification field (common to the source and destination), and Sh is a destination operand specification field. The size of the immediate value of I-format is 8, 16 or 32 bits in common with the size of the operand on the destination side, and zero extension and sign extension are not performed.

(1.2) "General-type 1-operand instruction" Figure 8 shows the general-format of 1-operand instruction (G1-f
FIG. MM is a field for specifying the operand size. Ea for some G1-format instructions
There is an extension part other than the extension part. Also, some instructions do not use MM.

(1.3) "General type two-operand instruction" FIGS. 9 to 11 are schematic diagrams showing a general type format of a two-operand instruction. Included in this format are instructions that have up to two operands in the general addressing mode specified by 8 bits. The total number of operands themselves may be three or more.

FIG. 9 is a schematic diagram showing a format (G-format) of an instruction in which the first operand requires memory reading.
EaM is the destination operand specification field, MM is the destination operand size specification field, EaR is the source operand specification field, RR
Is a source operand size specification field. Some G-format instructions have extensions other than EaM or EaR extensions.

FIG. 10 is a schematic diagram showing the format (E-format) of an instruction whose first operand is an 8-bit immediate value. EaM is the destination operand specification field, MM is the destination operand size specification field, # #
... is the source operand value.

Although E-format and I-format are functionally similar, they differ greatly in terms of thinking. Specifically, E-format
Is a derivative of the 2-operand general type (G-format), and the size of the source operand is fixed at 8 bits and the size of the destination operand is selected from 8/16/32 bits. That is, the E-format is premised on an operation between different sizes, and the 8-bit source operand is zero-extended or sign-extended according to the size of the destination operand. On the other hand, the I-form is a shortened form of an immediate value pattern that is frequently used especially for transfer instructions and comparison instructions, and the source operand and the destination operand have the same size.

FIG. 11 is a schematic diagram showing a format (GA-format) of an instruction whose first operand is only address calculation. EaW is a destination operand specification field, WW is a destination operand size specification field, and EaA is a source operand specification field.
The execution address calculation result itself is used as the source operand.

FIG. 12 is a schematic diagram showing the format of a short branch instruction. cccc is the branch condition specification field, di
sp: 8 is a displacement designation field with the jump destination, and when the displacement is designated by 8 bits in the data processing apparatus of the present invention, the designated value in the bit pattern is doubled to obtain the displacement value.

(1.4) "Addressing Mode" The addressing mode designating method of the data processing device of the present invention includes a short form designating in 6 bits including a register and a general form designating in 8 bits.

If an undefined addressing mode is specified, or if a combination of addressing modes that is apparently improper in meaning is specified, a reserved instruction exception is generated as if an undefined instruction was executed. , Exception processing is started.

This corresponds to the case where the destination is the immediate mode, the case where the immediate mode is used in the addressing mode designation field which should accompany the address calculation, and the like.

The meanings of the symbols used in the format diagrams are as follows.

Rn: Register specification mem EA: Memory content of the address indicated by EA (Sh): Specification method in 6-bit compact addressing mode (Ea): Specification method in 8-bit general type addressing mode Dashed line in format diagram The part surrounded by indicates the expanded part.

(1.4.1) "Basic Addressing Mode" The data processing device of the present invention supports various addressing modes. Among them, basic addressing modes supported by the data processing device of the present invention include register direct mode, register indirect mode, register relative indirect mode, immediate value mode, absolute mode, PC (program counter) relative indirect mode, and stack pop mode. And there is a stack push mode.

In the register direct mode, the contents of the register are directly used as the operand. A schematic diagram of the format is shown in FIG. Rn
Indicates the general register number.

In the register indirect mode, the contents of the memory whose address is the contents of the register are the operands. A schematic diagram of the format is shown in FIG. Rn indicates the general register number.

In the register relative indirect mode, the displacement value is 16
There are two types depending on whether it is bit or 32 bit.
Each of them uses the contents of the memory whose address is a value obtained by adding a displacement value of 16 bits or 32 bits to the contents of the register as an operand. A schematic diagram of the format is shown in FIG. Rn indicates the general register number. dis
p: 16 and disp: 32 respectively indicate a displacement value of 16 bits or a displacement value of 32 bits. The displacement value is treated as signed.

In the immediate mode, the bit pattern specified in the instruction code is regarded as a binary number as it is and used as an operand. A schematic diagram of the format is shown in FIG. imm-data indicates an immediate value. The size of imm-data is specified in the instruction as the operand size.

There are two types of absolute modes depending on whether the address value is indicated by 16 bits or 32 bits. The contents of the memory whose address is the 16-bit or 32-bit bit pattern specified in the instruction code are used as operands. A schematic diagram of the format is shown in FIG. abs: 16 and ab
s: 32 indicates a 16-bit or 32-bit address value, respectively. When the address is indicated by abs: 16, the specified address value is sign-extended to 32 bits.

There are two types of PC relative indirect mode depending on whether the displacement value is 16 bits or 32 bits. The contents of the memory whose address is a value obtained by adding a displacement value of 16 bits or 32 bits to the contents of the program counter are used as operands. A schematic diagram of the format is shown in FIG. disp: 16 and disp: 32 represent a displacement value of 16 bits or a displacement value of 32 bits, respectively. The displacement value is treated as signed. In the PC relative indirect mode, the value of the referenced program counter is the start address of the instruction containing the operand. Even when the value of the program counter is referenced in the multi-stage indirect addressing mode, the start address of the instruction is used as the PC relative reference value in the same manner.

In the stack pop mode, the content of the memory whose address is the content of the stack pointer (SP) is the operand. After accessing the operand, increment the stack pointer by the operand size. For example, when handling 32-bit data, SP is updated (incremented) by +4 after operand access. It is also possible to specify the stack pop mode for operands of B and H (byte, halfword) size, and SP is updated (incremented) by +1 and +2, respectively. A schematic diagram of the format is shown in FIG. If the stack pop mode has no meaning for the operand, a reserved instruction exception is generated. Specifically, the reserved instruction exception is the stack pop mode specification for the write operand and the read-modify-write operand.

In the stack push mode, the contents of the memory whose address is the contents of the stack pointer decremented by the operand size are the operands. In stack push mode, the stack pointer is decremented before operand access. For example, when handling 32-bit data, SP is updated (decremented) by -4 before operand access. It is also possible to specify stack push mode for operands of sizes B and H, and SP is updated (decremented) by -1 and -2, respectively.
Figure 20 shows a schematic diagram of the format. If the stack push mode has no meaning for the operand, a reserved instruction exception is generated. Specifically, reserved instruction exceptions are read operands and read-modify-write.
It is a stack push mode specification for the operand.

(1.4.2) “Multistage indirect addressing mode” Basically, even complicated addressing is decomposed into a combination of addition and indirect reference. Therefore, if the operations of addition and indirect reference are given as addressing primitives and they can be arbitrarily combined, any complicated addressing mode can be realized. The multi-stage indirect addressing mode of the data processor of the present invention is an addressing mode based on such a concept. Complex addressing modes are especially useful for data references between modules or AI (artificial intelligence) language processors.

When specifying the multi-stage indirect addressing mode, in the basic addressing mode specification field, select one of three types of register-based multi-stage indirect mode, PC-based multi-stage indirect mode, and absolute base multi-stage indirect mode.
Specify one.

The register-based multistage indirect mode is an addressing mode in which the value of a register is used as a base value for multistage indirect addressing. A schematic diagram of the format is shown in FIG. Rn indicates the general register number.

The PC-based multi-stage indirect mode is an addressing mode that uses the base value of multi-stage indirect addressing that extends the value of the program counter. A schematic diagram of the format is shown in FIG.

The absolute base multistage indirect mode is an addressing mode that uses zero as a base value for multistage indirect addressing. A schematic diagram of the format is shown in FIG.

The multi-stage indirect mode specification field to be expanded has 16 bits as a unit, and this is repeated any number of times. Addition of displacement, scaling (× 1, × 2, × 4, × 8) and addition of index register, and indirect reference of memory are performed by the one-stage multi-stage indirect mode. A schematic diagram of the format of the multistage indirect mode is shown in FIG. Each field has the following meaning.

E = 0: Multi-stage indirect mode continued E = 1: Address calculation end tmp ==> address of operand I = 0: No memory indirect reference tmp + disp + Rx * Scale ==> tmp I = 1: Memory indirect reference mem tmp + disp + Rx * Scale = => Tmp M = 0: Use <Rx> as index M = 1: Special index <Rx> = 0 Do not add index value (Rx = 0) <Rx> = 1 Use program counter as index value (Rx = PC) <Rx> = 2 to reserved D = 0: The value of the 4-bit field d4 in the multi-stage indirect mode is multiplied by 4 to make a displacement value, and this is added. D4 is treated as a signed value, and the operand size Always use 4 times regardless of D = 1: dispx (16 /
(32 bits) is used as the displacement value, and the size of the extension to be added is specified in the d4 field. D4 = 0001 dispx is 16 bits d4 = 0010 dispx is 32 bits xx: Index scale (scale = 1/2/4 / 8) When the program counter is scaled by x2, x4, x8, an indeterminate value is entered as the intermediate value (tmp) after the processing of that stage. Although the effective address obtained by this multistage indirect mode has an unpredictable value,
No exception is raised. Do not specify scaling for the program counter.

25 and 26 show variations of the instruction format in the multi-stage indirect mode.

FIG. 25 shows a variation in which the multistage indirect mode continues or ends.

FIG. 26 shows variations in displacement size.

If the multi-stage indirect mode with an arbitrary number of stages can be used, it is not necessary to divide the case depending on the number of stages in the compiler, which has the advantage of reducing the load on the compiler. This is because the compiler must be able to generate correct code even if the frequency of multiple indirect references is extremely low. Therefore, an arbitrary number of stages is possible in the format.

(1.5) "Exception Processing" The data processing device of the present invention has abundant exception processing functions to reduce software load. In the data processing device of the present invention, the exception processing is divided into three types, that is, one that re-executes instruction processing (exception), one that completes instruction processing (trap), and interrupt. Further, in the data processing device of the present invention, these three types of exception processing and system failure are collectively referred to as EIT.

(2) "Functional Block Configuration" FIG. 1 is a block diagram showing the configuration of the data processing apparatus of the present invention.

Functionally roughly dividing the inside of the data processing device of the present invention, an instruction fetch unit 101, an instruction decoding unit 102, a PC calculation unit 10
3, it is divided into an operand address calculation unit 104, a micro ROM unit 105, a data operation unit 106, and an external bus interface unit 107.

In FIG. 1, an address output circuit 108 for outputting an address to the outside of the CPU and a data input / output circuit 109 for inputting / outputting data to / from the outside of the CPU are shown separately from the other functional block parts.

(2.1) "Instruction Fetch Unit" The instruction fetch unit 101 has a branch buffer, an instruction queue and its control unit, etc., determines the address of the instruction to be fetched next, and fetches the instruction from the branch buffer or a memory outside the CPU. To do. It also registers instructions in the branch buffer.

Since the branch buffer is small, it operates as a selective cache. Details of the operation of the branch buffer are described in detail in Japanese Patent Application No. 61-202041.

The address of the instruction to be fetched next is calculated by a dedicated counter as the address of the instruction to be input to the instruction queue. When a branch or jump occurs, the address of the new instruction is transferred from the PC calculation unit 103 or the data calculation unit 106.

When fetching an instruction from the memory outside the CPU, the address of the instruction to be fetched is output from the address output circuit 108 to the outside of the CPU through the external bus interface unit 107, and the instruction code is fetched from the data input / output circuit 109. Then, of the buffered instruction codes, the instruction code to be decoded next is output to the instruction decoding unit 102.

(2.2) "Instruction Decoding Unit" The instruction decoding unit 102 basically decodes the instruction code in 16-bit (halfword) units. This block includes an FHW decoder that decodes the operation code included in the first halfword, an NFHW decoder that decodes the operation code included in the second and third halfwords, and an addressing mode decoder that decodes the addressing mode. The FHW decoder, NFHW decoder, and addressing mode decoder are collectively referred to as the first decoder.

A second decoder that further decodes the output of the FHW decoder or the NFHW decoder to calculate the entry address of the micro ROM, a branch prediction mechanism that performs branch prediction of conditional branch instructions, and an address that checks pipeline conflicts when calculating operand addresses. A calculation conflict check mechanism is also included.

The instruction decoding unit 102 decodes the instruction code input from the instruction fetch unit 101 by 0 to 6 bytes every 2 clocks (1 step). Among the decoding results, the information related to the calculation in the data calculation unit 106 is stored in the micro ROM unit 105, the information related to the operand address calculation is stored in the operand address calculation unit 104, and the information related to the PC calculation is stored in the PC calculation unit 103.
Are output respectively.

(2.3) "Micro ROM section" The micro ROM section 105 stores a micro ROM that mainly stores a micro program for controlling the data calculation section 106,
A micro sequencer, a micro instruction decoder, etc. are included. Micro instructions are read from the micro ROM once every two clocks (one step). In addition to the sequence processing indicated by the microprogram, the microsequencer accepts processing of exception, interrupt and trap (these three are collectively called EIT) by hardware. Also micro
The ROM unit 105 also manages the store buffer. Micro ROM
The flag information based on an interrupt or an operation execution result that does not depend on the instruction code and the output of the instruction decoding unit such as the output of the second decoder are input to the unit 105. The output of the microdecoder is mainly output to the data operation unit 106, but some information such as other preceding process stop information due to execution of the jump instruction is also output to other blocks.

(2.4) "Operand Address Calculation Unit" The operand address calculation unit 104 is hard-wired controlled by the information related to the operand address calculation output from the address decoder of the instruction decoding unit 102.
In this block, most of the processing for calculating the address of the operand is performed. It is also checked whether the memory access address and the operand address for the memory indirect addressing enter the I / O area mapped in the memory.

The address calculation result is sent to the external bus interface unit 107. The values of the general-purpose register and the program counter required for address calculation are input from the data calculation unit.

When performing memory indirect addressing, the memory address to be referred to outside the CPU is output from the address output circuit 108 through the external bus interface unit 107, and the indirect address value input from the data input / output unit 109 is output to the instruction decoding unit 1.
Fetch through 02.

(2.5) "PC Calculation Unit" The PC calculation unit 103 is hard-wired controlled by the information related to the PC calculation output from the instruction decoding unit 102, and calculates the PC value of the instruction. The data processor of the present invention has a variable length instruction set, and the length of the instruction cannot be known unless the instruction is decoded. Therefore, the PC calculation unit 103 creates the PC value of the next instruction by adding the instruction length output from the instruction decoding unit 102 to the PC value of the instruction being decoded. When the instruction decoding unit 102 decodes a branch instruction and instructs branching at the decoding stage, the PC value of the branch destination instruction is calculated by adding the branch displacement instead of the instruction length to the PC value of the branch instruction. To do. In the data processing apparatus of the present invention, branching a branch instruction at the instruction decoding stage is called pre-branch.

This pre-branching method is described in detail in Japanese Patent Application Nos. 61-204500 and 61-200557.

The calculation result of the PC calculation unit 103 is output as the PC value of each instruction together with the instruction decoding result, and at the time of pre-branching,
The address of the next instruction to be decoded is output to the instruction fetch unit 101. Further, it is also used as an address for branch prediction of an instruction decoded next by the instruction decoding unit 102.

The branch prediction method is described in detail in Japanese Patent Application No. 62-8394.

(2.6) "Data operation unit" The data operation unit 106 is controlled by a micro program, and executes the operations required to realize the functions of the respective instructions by the register and the operation unit according to the output information of the micro ROM unit 105. When the operand to be operated is an address or an immediate value, the address or immediate value calculated by the operand address calculation unit 104 is used as the external bus interface unit.
Get through 107. If the operand to be operated is in the memory outside the CPU, the address calculation unit 104
The bus interface unit outputs the address calculated in step 1 from the address output circuit 108, and the operand fetched from the memory outside the CPU is obtained from the data input / output circuit 109.

The arithmetic unit includes an ALU, barrel shifter, priority encoder or counter, shift register, and the like. The registers and main arithmetic units are connected by three buses, and one microinstruction for instructing one inter-register operation is processed in two clocks (one step).

When it is necessary to access the memory outside the CPU during data calculation, the address is output from the address output circuit 108 to the outside of the CPU through the external bus interface unit 107 according to the instructions of the microprogram, and the target data is output through the data input / output circuit 109. To fetch.

When the data is stored in the memory outside the CPU, the address output circuit 108 is passed through the external bus interface unit 107.
Data output circuit 10
Outputs data from 9 to outside the CPU. In order to perform the operand store efficiently, the data operation unit 106 is provided with a 4-byte store buffer.

When the data operation unit 106 obtains a new instruction address by performing a jump instruction process or an exception process, it outputs this to the instruction fetch unit 101 and the PC calculation unit 103.

(2.7) “External Bus Interface Unit” The external bus interface unit 107 controls communication on the external bus of the data processing device of the present invention. All memory accesses are performed in clock synchronization, and can be performed in a minimum of 2 clock cycles (1 step).

The memory access request is independently generated from the instruction fetch unit 101, the operand address calculation unit 104, and the data calculation unit 106. The external bus interface unit 107 arbitrates these memory access requests. Furthermore, access to data at a memory address that crosses a 32 bit (1 word) alignment boundary, which is the data bus size connecting the memory and the CPU,
In this block, it is automatically detected that a word boundary is crossed, and the memory access is decomposed into two memory accesses.

A conflict prevention process and a bypass process from the store operand to the fetch operand when the prefetch operand and the store operand overlap each other are also performed.

(3) "Pipeline mechanism" The pipeline processing function of the data processing device of the present invention is the second
It is as shown in the figure.

Instruction fetch stage (IF stage) 201 that prefetches instructions, decode stage (D stage) 202 that decodes instructions, operand address calculation stage (A stage) 203 that performs operand address calculation, micro ROM access (especially R stage) Operand fetch stage (F stage) 204, which is composed of a portion for performing an instruction (206) and a portion for performing an operand prefetch (specifically, OF stage 207), and an execution stage (E) for executing an instruction.
The five stages of stages 205 are the basics of pipeline processing.

In the E stage 205, there is a one-stage store buffer, and since some high-performance instructions pipeline the instruction execution itself, there is actually a pipeline processing effect of five or more stages.

Each stage operates independently of the other stages, and theoretically five stages operate completely independently. Each stage is 1
It is possible to perform the processing twice with a minimum of 2 clocks (1 step). Therefore, ideally, pipeline processing progresses one after another every two clocks (one step).

The data processing device of the present invention has some instructions that cannot be processed by only one basic pipeline process such as memory-memory operation or memory indirect addressing. It is also designed so that balanced pipeline processing can be performed as much as possible. An instruction having a plurality of memory operands is decomposed into a plurality of pipeline processing units (step codes) in the decoding stage based on the number of memory operands and pipeline processing is performed.

Regarding the method of disassembling pipeline processing units, Japanese Patent Application No. 61-2
It is described in detail in No. 36456.

The information passed from the IF stage 201 to the D stage 202 is the instruction code 211 itself. The information passed from the D stage 202 to the A stage 203 is related to an operation designated by an instruction (called a D code 212) and information related to operand address calculation (called an A code 213).
There is one.

Information passed from the A stage 203 to the F stage 204 is an R code 214 including an entry address of a microprogram or a parameter of the microprogram, and an F code 215 including an operand address and access method instruction information. .

The information passed from the F stage 204 to the E stage 205 includes an E code 216 including operation control information and a literal and an S code 217 including an operand or an operand address.
And two.

The EIT detected in a stage other than the E stage 205 does not start the EIT processing until the code reaches the E stage 205. This is because only the instruction processed in the E stage 205 is the instruction in the execution stage, and the instruction processed in the IF stage 201 to the F stage 204 has not reached the execution stage yet. Therefore, the EIT detected in other than the E stage 205 is only recorded in the step code and transmitted to the next stage.

(3.1) "Pipeline processing unit" (3.1.1) "Instruction code field classification" The pipeline processing unit of the data processing device of the present invention is determined by utilizing the characteristics of the format of the instruction set.

As described in section (1), the instruction of the data processing device of the present invention is a variable length instruction in units of 2 bytes, and basically, "2 byte instruction basic part + 0 to 4 byte addressing extension part" is 1 An instruction is constructed by repeating ~ 3 times.

In many cases, the basic instruction section has an operation code section and an addressing mode designating section. When index addressing or memory indirect addressing is required, a “2-byte multi-stage indirect mode designating section is used instead of the addressing extension section. An arbitrary number of +0 to 4 bytes of addressing extension part "is attached. In addition, depending on the instruction, a 2-byte or 4-byte extension section peculiar to the instruction is added at the end.

The instruction basic part includes an operation code of the instruction, a basic addressing mode, a literal, and the like. Addressing extensions are displacements, absolute addresses,
It is either an immediate value or a displacement of a branch instruction. The instruction-specific extension part includes a register map, immediate value specification of an I-format instruction, and the like. FIG. 27 is a schematic diagram showing characteristics of the basic instruction format of the data processing device of the present invention.

(3.1.2) “Decomposition of instruction into step code” In the data processing device of the present invention, pipeline processing is performed by making the most of the characteristics of the above instruction format.

In the D stage 202, "2-byte instruction basic part + 0 to 4-byte addressing extension part", "multistage indirect mode designation +
The addressing extension unit "or the instruction-specific extension unit is processed as one decoding unit. The decoding result of each time is called a step code, and after the A stage 203, this step code is a unit of pipeline processing. Is unique to each instruction, and if the multi-stage indirect mode is not specified, one instruction is at least 1 and maximum is 3
It is divided into individual step codes. If the multi-stage indirect mode is specified, the step code increases accordingly. However, this is only the decoding stage as described later.

(3.1.3) “Management of program counter” All step codes existing on the pipeline of the data processing device of the present invention may be for different instructions, and therefore the value of the program counter is different for each step code. Managed. Every step code has the program counter value of the instruction that caused the step code. The program counter value that is attached to the step code and flows through each stage of the pipeline is called a step program counter (SPC). SPCs are passed between pipeline stages one after another.

(3.2) “Processing of each pipeline stage” The input / output step code of each pipeline stage is named for convenience as shown in FIG. In addition, the step code performs processing related to the operation code, and becomes a sequence such as an entry address of the microprogram and parameters for the E stage 205
There are two series, a series that becomes an operand for the micro instruction of the stage 205.

(3.2.1) “Instruction Fetch Stage” The instruction fetch stage (IF stage) 201 fetches an instruction from the memory or branch buffer, inputs it to the instruction queue, and outputs an instruction code to the D stage 202. Input to the instruction queue is performed in aligned 4-byte units. When fetching an instruction from memory, a minimum of 2 clocks (1 step) is required for each aligned 4 bytes. When the branch buffer is hit, it is possible to fetch in 1 clock for each aligned 4 bytes. The output unit of the instruction queue is variable every 2 bytes, and up to 6 bytes can be output during 2 clocks. Immediately after branching, it is possible to bypass the instruction queue and directly transfer the 2 bytes of the basic instruction portion to the instruction decoder.

Control such as registering and clearing instructions in the branch buffer,
The IF stage 201 also manages the addresses of prefetch destination instructions and controls the instruction queue.

The EIT detected in the IF stage 201 includes a bus access exception when fetching an instruction from memory or an address translation exception due to a memory protection violation.

(3.2.2) "Instruction decode stage" The instruction decode stage (D stage) 202 is the IF stage 2
Decode the instruction code input from 01. Decoding is performed once every 2 clocks (1 step) using the first decoder that combines the FHW decoder, NFHW decoder and addressing mode decoder of the instruction decoding unit 102, and 0 to 6 bytes in one decoding process. Consume the instruction code (does not consume the instruction code in the output processing of the step code including the return address of the RET instruction).
Control code and address modification information which are A code 213 as address calculation information for A stage 203 in one decoding, control code which is D code 212 as an intermediate decoding result of operation code, and 8-bit literal information. And output.

The D stage 202 also performs control of the PC calculation unit 103 for each instruction, branch prediction processing, pre-branch processing for pre-branch instructions, and instruction code output processing from the instruction queue.

The EIT detected by the D stage 202 includes a reserved instruction exception and an odd address jump trap at the time of pre-branch.
In addition, various EITs transferred from the IF stage 201 are processed to be encoded in the step code and the A stage 20
Transfer to 3.

(3.2.3) “Operand address calculation stage” The operand address calculation stage (A stage) 203 is roughly divided into two processing functions. One is a process of performing the subsequent decoding of the operation code using the second decoder of the instruction decoding unit 102, and the other is a process of calculating the operand address in the operand address calculation unit 104.

D-code 21 for the subsequent decoding of the operation code
2 is input, and the R code 214 including the register reservation of the memory and the memory, the entry address of the microprogram and the parameters for the microprogram is output. In addition, write reservation of register or memory is
This is to prevent erroneous address calculation by rewriting the contents of the register or memory referred to in the address calculation by a preceding instruction on the pipeline. In order to avoid deadlock, write reservation of the register or memory is performed not for each step code but for each instruction. The reservation of writing to the register and the memory is described in detail in Japanese Patent Application No. 62-144394.

In the operand address calculation process, the A code 213 is input, the address calculation is performed by the operand address calculation unit 104 according to the A code 213 in combination with the memory indirect reference, and the calculation result is output as the F code 215.
At this time, a conflict check is performed at the time of reading the register and the memory associated with the address calculation, and if the conflict is instructed because the preceding instruction has not finished the writing process to the register or the memory, the preceding instruction causes the E stage 205.
Wait until the writing process is completed with. Further, it is also checked whether the operand address and the memory indirect reference address enter the I / O area mapped in the memory.

The EIT detected by the A stage 203 includes a reserved instruction exception, a privileged instruction exception, a bus access exception, an address translation exception, and a debug trap due to an operand breakpoint hit during indirect memory addressing. If the D code 212 or the A code 213 itself indicates that the EIT has occurred, the A stage 203 does not perform the address calculation process on the code, and transmits the EIT to the R code 214 and the F code 215.

(3.2.4) “Micro ROM access stage” The operand fetch stage (F stage) 204 is also roughly divided into two processes. One of them is a micro ROM access process, which is particularly called an R stage 206. The other is the operand prefetch process, especially the OF stage 207.
Called. The R stage 206 and the OF stage 207 do not always operate simultaneously, but operate independently depending on whether or not a memory access right can be acquired.

The micro ROM access process, which is the process of the R stage 206, is the micro ROM access and the micro instruction decoding for generating the E code 216 which is the execution control code used for the execution of the next E stage 205 for the R code 214. Processing. When the processing for one R code 214 is decomposed into two or more microprogram steps, the micro ROM is used in the E stage 205 and the next R code 214 is used.
Waits for micro ROM access. The micro ROM access to the R code 214 is performed at the last micro instruction execution in the E stage 205 before that. In the data processor of the present invention, most of the basic instructions are executed in one microprogram step, so in practice R
Micro ROM access to code 214 is often made one after another.

There is no EIT newly detected in the R stage 206. R code 21
When 4 indicates an EIT of instruction processing re-execution type, that EIT
Since the microprogram for processing is executed, R
The stage 206 fetches the micro instruction according to the R code 214. If R-code 214 indicates an odd address jump trap, R-stage 206 signals it by E-code 216. This is for a pre-branch, and in the E stage 205, if no branch occurs in the E code 216, the pre-branch is validated and an odd address jump trap is generated.

(3.2.5) "Operand fetch stage" The operand fetch stage (OF stage) 207 performs the operand prefetch process of the above two processes performed in the F stage 204.

In the operand prefetch, the F code 215 is input, and the fetched operand and its address are output as the S code 217. One F code 215 may cross word boundaries, but an operand fetch of 4 bytes or less is designated. The F code 215 also includes designation of whether or not to access the operand. The operand address itself or the immediate value calculated in the A stage 203 is used in the E stage 205.
When transferring to, do not perform operand prefetch
The contents of the F code 215 are transferred as the S code 217. When the operand to be prefetched matches the operand to be written by the E stage 205, the operand prefetch is bypassed from the memory. Also, the operand prefetch is delayed for the I / O area, and the operand fetch is performed after waiting for the completion of all the preceding instructions.

The EIT detected in the OF stage 207 includes a bus access exception, an address translation exception, and a debug trap due to a breakpoint hit for operand prefetch. When the F code 215 indicates an EIT other than the debug trap, it is transferred to the S code 217 and operand prefetch is not performed. When the F code 215 indicates a debug trap, the same processing as in the case where EIT is not indicated for the F code 215 is performed and the debug trap is transmitted to the S code 217.

(3.2.6) "Execution Stage" The execution stage (E stage) 205 operates by inputting the E code 216 and the S code 217. The E stage 205 is a stage for executing instructions, and all the processes performed in the stages before the F stage 204 are pre-processes for the E stage 205. If a jump instruction is executed in the E stage 205 or EIT processing is activated, the IF
All the processes from stage 201 to F stage 204 are invalidated. The E stage 205 is controlled by the microprogram and executes instructions by executing a series of microprograms from the microprogram entry address indicated by the R code 214.

The reading of the micro ROM and the execution of the micro instructions are pipelined. Therefore, when a branch occurs in the microprogram, there is a space of 1 microstep. Further, the E stage 205 can use the store buffer in the data operation unit 106 to pipeline the operand store within 4 bytes and the next microinstruction execution.

In the E stage 205, the write reservation for the register and the memory made in the A stage 203 is canceled after writing the operand.

When the conditional branch instruction causes a branch at the E stage 205, the branch prediction for the conditional branch instruction was incorrect, and the branch history is rewritten.

The EIT detected by the E stage 205 includes bus access exception, address translation exception, debug trap, odd address jump trap, reserved function exception, illegal operand exception, reserved stack format exception, divide by zero trap, unconditional trap, and condition trap. , Delayed context trap, external interrupt, delayed interrupt, reset interrupt, system failure.

All EITs detected by E stage 205 are processed by EIT, but IF stages 201 to 204 before E stage are processed.
The EIT detected between the R code 214 and the S code 217 is not always subjected to the EIT process. Detected between IF stage 201 and F stage 204, but the preceding instruction did not reach E stage 205 due to a jump instruction being executed at E stage 205.
All IT will be canceled. The instruction that caused the EIT was not executed in the first place.

External interrupts and delayed interrupts are E-stage 205 at instruction breaks.
Is directly received by the microprogram and the required processing is executed by the microprogram. The processing of other various EITs is performed by the microprogram.

(3.3) "State control of each pipeline stage" Each stage of the pipeline basically has an input latch and an output latch and operates independently of other stages. Each stage completes the previous processing, transfers the processing result from the output latch to the input latch of the next stage, and when all the input signals necessary for the next processing are available in the input latch of the own stage, The process of is started.

In other words, in each stage, all the input signals for the next processing output from the previous stage become valid, the current processing result is transferred to the input latch of the subsequent stage, and the next processing is performed when the output latch becomes empty. To start.

It is necessary that all input signals be completed at the clock timing immediately before the start of operation of each stage. If the input signals are not complete, the stage enters the waiting state (waiting for input). When transferring from the output latch to the input latch of the next stage, the input latch of the next stage must be empty.The pipeline stage waits even if the input latch of the next stage is not empty. The status (waiting for output) is entered. If the necessary memory access right cannot be acquired, a wait is inserted in the memory access being processed, or another pipeline conflict occurs, the processing itself of each stage is delayed.

(3.4) Operation of Stack Pointer FIG. 28 is a block diagram showing an embodiment of the present invention.
61 is an operand address calculation stage (A stage 20
It is the work stage stack pointer ASP of 3) and indicates the value of the stack pointer associated with the instruction being executed in the A stage 203. 63 is a work stage stack pointer (FSP) of the operand fetch stage (F stage 204),
Reference numeral 65 is a work stage stack pointer CSP for the execution stage (E stage 205). 66 is a stack pointer group of the level seen from software (a plurality of stack pointers exist due to rings, interrupts, etc.), 62 is an ASP output latch, 64 is an FSP output latch, and ASP61 and FSP respectively.
This is a latch that holds the output data of 63.

72 is the address register (AA register) of the E stage 205, 73 is the data register (DD register) of the E stage 205 for data exchanged with the outside, 75 is the address adder of the A stage 203, and 80 to 87 are internal It is a data bus. 106 is a data operation unit of the E stage 205, and 90a to 90e are ASP update signals indicating that the ASP 61 has been updated in the A stage 203. Reference numeral 91 is an ASP increment signal in the A code 213, and 92 is an ASP decrement signal in the A code 213.
611,621,631,641 are ASP61, ASP output latch 62, FSP6 respectively
3. A latch that transfers the ASP update signal 90a as part of the FSP output latch 64.

FIG. 29 and FIG. 30 are diagrams showing processing relating to the stack pointer in each stage of some instructions executed in the data processing device of the present invention. (A) shows the processing of the A stage 203, (f) shows the processing of the F stage 204, and (e) shows the processing of the E stage 205.

FIGS. 31 and 32 are diagrams showing the states of pipeline processing when the step code next to the instruction of FIG. 30 refers to the stack pointer and when it does not. Is "100"
To the stack pointer, a step code to be processed next to, a step code to be processed next to, a step code to be processed next to,
203, (f) is F stage 204, (e) is E stage 205
Shows the processing of the stack pointer, and the horizontal axis shows the passage of time.

Next, the processing relating to the stack pointer will be described with reference to FIG. The A code 213 includes an ASP61 increment signal 91 and a decrement signal 92, and these signals 91 and 92 control the ASP61. Also, an ASP update signal 90a is generated by ORing the increment signal 91 and the decrement signal 92.

When the increment signal 91 or the decrement signal 92 is "1", that is, when the ASP61 is updated in the A stage 203, the AS
The P update signal 90a becomes "1". Then, the ASP update signal 90a is transferred together with the value of the stack pointer in synchronization with the flow of step code in the pipeline. In the E stage 205, only when the transferred ASP update signal 90e is "1"
Transfer the value of FSP63 to CSP65.

An instruction that includes the operand specification of the stack push / addressing mode, for example, the MOV instruction that writes the register value to the stack top (where the decrement value points to the stack pointer value) (MOV: Rn-> @-SP Rn is the nth 29, and @ -SP indicates the address indicated by the decremented value of the stack pointer). FIG. 29 shows the processing relating to the stack pointer of each stage. First, the D stage 202 generates an A code 213 including update control of the ASP 61 and the like.

The A stage 203 outputs an R code 214 including register designation. Also, based on the A code 213, ASP61 is decremented by the size of the operand, and the updated value is FSP63.
Transferred to. At this time, the ASP update signal 90a indicating that the ASP 61 has been updated at the A stage 203 becomes "1", and this signal is
Transferred with the value of ASP61. If the F stage 204 is not processing the previous step code and cannot immediately transfer the value of ASP61, the ASP output latch 62 waits until transfer becomes possible. In the data processing device of the present invention, in order to make the processes of the stack push addressing mode and other addressing modes common, the address addition unit 75 also executes (ASP value-operand size) together with the decrement of ASP61. Then, the result is transferred to the F stage 204 as an operand address.

In the F stage 204, the E code 216 including the register access signal is generated from the R code 214, and the E code 216 including the E address 216 and the operand address value is added to the E stage 2
Transfer to 05. It also detects that the ASP update signal 90e is "1" and transfers the value of FSP63 to CSP65. If it cannot transfer to CSP65 immediately as before, wait until transfer is possible with FSP output latch 64.

In the E stage 205, the value of the specified register is read from the data calculation unit 106 via the DO bus 85 and the DD register 73
Write in. The operand address transferred from the F stage 204 is written in the AA register 72. At the end of this instruction, the value of the CSP 65 is transferred to one of the stack pointer group 66 viewed from the software, and the value of the stack pointer after the execution of the instruction is set correctly from the outside. The value of the DD register 73 is stored in the address indicated by the AA register 72.

Since the stack pointer value at the end of this instruction is stored in ASP61 when this instruction finishes processing at the A stage 203, a later instruction includes an addressing mode in which the stack pointer is referenced. Also, the correct address can be obtained by referring to the value of ASP61.

Next, FIG. 30 shows a process relating to the stack pointer of an instruction (MOV: "100"-> SP "100" is an immediate value, SP is a stack pointer) for writing "100" to the stack pointer.

With this instruction, the value of ASP61 does not change during the processing in the A stage 203. The value of this ASP61 is transferred to FSP63. In addition, a stack pointer write reservation is made to indicate that the value of the stack pointer is rewritten in the E stage 205 so that the subsequent instruction does not reference the wrong value when the stack pointer is referenced. At this time, the ASP update signal 90a is "0".

The F stage 204 outputs an E code 216 including stack pointer write control and the like, and an S code 217 including immediate data “100”. At this time, since the ASP update signal 90e is "0", the value of FSP63 is not written to CSP65.

The E stage 205 reads the immediate data "100" based on the E code 216 and transfers it to the ASP 61 and CSP 65 through the data operation unit 106 and the DO bus 85. And at the end of the command CS
The value of P65 is transferred to the SP group 66.

Here, FIG. 31 shows the case where the step code after this instruction uses the stack pointer in the address calculation.
At this time, in the next step code, since the stack pointer write reservation is made in the step code, the step code is processed in the E stage 205, a value is written in the stack pointer, and the stack pointer write reservation is released. Waits after interrupting the processing at the A stage 203. Then, after the step code is processed in the E stage 205 and the ASP 61 is rewritten, the processing of the step code in the A stage 203 is started. The step code transfers the value of FSP63 to CSP65.

On the other hand, FIG. 32 shows the case where the subsequent step code does not refer to the stack pointer. At this time, the next step code does not refer to the stack pointer, so the A stage 203
It is not necessary to wait at, and the processing in the A stage 203 is started when the step code finishes the processing in the A stage 203. With regard to this step code, the value of ASP61 is different from the value of the stack pointer that should be originally attached when the instruction is executed. But in the step code AS
The P update signal is “0”, and the value of FSP63 is not written to CSP65. Therefore, the step code is E stage 205
The correct stack pointer value (the value written to CSP65 in the step code) is processed by CSP65.
It is in. Then, at the end of the instruction, the value of CSP65 is written to the stack pointer 66 viewed from software.

If the step code does not use the stack pointer, the process in the A stage 203 is started when the step code finishes the process in the A stage 203. Similarly to the step code, the ASP update signal 90 is "0", and the value transfer from the FSP63 to the CSP65 is not performed.

In this way, when each step code updates the stack pointer value in the A stage 203,
The value of the stack pointer at the end of this instruction is written in ASP61 when the processing is completed at. Therefore, when the step code of the subsequent instruction refers to the stack pointer at the A stage 203, the correct address can be obtained by referring to ASP61. For example, if the addressing mode of the next instruction is (SP + disp), (ASP + d
By executing isp) in the address adder 75, the correct address can be obtained without waiting for the end of the previous instruction.

When updating the value of the stack pointer in the processing of the E stage 205, a stack pointer write reservation is made. When the next step code refers to the stack pointer at the A stage 203, the processing of the next step code waits until the stack pointer write reservation is released at the A stage 203. On the other hand, if the next step code does not refer to the stack pointer, the A stage 20
You don't have to wait in 3
F when the step code is sent to the E stage 205
Disable transfer of stack pointer value from SP63 to CSP65. In this way, an incorrect value is prevented from being transferred to the CSP 65, and the value of the stack pointer 66 seen from the software transferred at the end of the instruction is kept correct.

As described above, according to the present invention, the address calculation stage has the stack pointer, and the transfer of the value to the stack pointer managed by the execution stage is performed by the address calculation by the stack pointer managed by the address calculation stage. By controlling depending on whether or not the stage is updated, there is an effect that high-speed and accurate instruction execution can be performed with less hardware.

[Brief description of drawings]

FIG. 1 is an overall block diagram of a data processing device according to an embodiment of the present invention, FIG. 2 is a schematic diagram of a pipeline of a data processing device according to an embodiment of the present invention, and FIGS. FIG. 28 is a diagram showing characteristics of an instruction format of a data processing device according to an embodiment, FIG. 28 is a configuration diagram of a stack pointer related portion of a data processing device according to an embodiment of the present invention, and FIG.
FIG. 30 is an execution flowchart of some instructions executed in the data processor of the present invention, FIG. 31, FIG.
Figure is an execution flow chart including the next step code of the instruction shown in Figure 30, Figure 33 is a block diagram showing a conventional example,
34 and 35 are execution flow charts of conventional push instructions. 203 …… Address calculation stage (A stage), 205 ……
Execution stage (E stage), 212 to 217 ... Step code, which is a unit of pipeline processing, 61 ... A stage
203 working stage stack pointer (ASP), 63 ……
E-stage 205 work stage stack pointer (CS
P), 75 ... A stage 203 address adder, 90 ... A
ASP update signal indicating that ASP is updated in stage 203 Note that the same reference numerals in the drawings indicate the same or corresponding portions.

Claims (1)

[Claims] 1. An addressing mode for designating an operand of an instruction by a stack pointer and at the same time an updating method of the stack pointer is provided, and instruction processing is sequentially performed by pipeline processing in a first stage and a second stage. A first stack pointer that can be referenced in the first stage, a second stack pointer that can be referenced in the second stage, and a first stack pointer that is controlled in the first stage First updating means for updating, second updating means controlled by the second stage for updating the first stack pointer, and second controlling means for updating the second stack pointer by the second stage. Third updating means for updating, and transfer means for transferring the value of the first stack pointer to the second stack pointer In the data processing device, the first stack pointer is synchronized with the transfer of the instruction to the second stage only when the first stack pointer is an instruction updated under the control of the first stage. And a transfer control means for transferring from the stack pointer to the second stack pointer.