JPH0766801A - Transmission data synchronizing system - Google Patents

Abstract

PURPOSE:To avoid in advance a data error attended by unestablishment of frame synchronization by controlling the start/stop of a sweep operation of a clock phase and a logic discrimination level based on the result of monitoring a line error rate with respect to the transmission data synchronizing system establishing frame synchronization of input transmission data to detect transmis sion data by a clock. CONSTITUTION:A frame synchronization detection section 11 detects establishment of frame synchronization and a bit error number included on a frame synchronization code based on a clock from a phase sweep section 15 to provide an output of the bit error number. An error rate calculation section 12 integrates the bit error number and estimates and calculates a line error rate based thereon. A sweep control section 14 controls the start and stop of the sweep operation of the phase sweep section 15 and a level sweep section 16 in response to the comparison result between the line error rate and a setting value obtained from an error rate setting section 13. The level sweep section 16 sweeps a threshold level used for logical discrimination of each input circuit of the frame synchronization detection section 11 and the phase sweep section 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission data synchronization system, and more particularly to a transmission data synchronization system for establishing frame synchronization of input transmission data in order to detect transmission data by a clock.

[0002]

2. Description of the Related Art Conventionally, when the phase of the transmission data and the transmission clock input in parallel is not appropriate and the frame synchronization is not established, the phase of the clock is varied to establish the frame synchronization. There is known a transmission data synchronization method for detecting transmission data received using a clock (for example, Japanese Patent Laid-Open No. 62-76338).

FIG. 3 is a block diagram showing an example of a conventional transmission data synchronization system. In the figure, transmission data is input to the input terminal 1 and a transmission clock is input to the input terminal 2. This input transmission data is, for example, pulse code modulation (PC
For each predetermined number of words of the M) data, a frame synchronization code of a fixed pattern is input at least in units of added frames and input to the frame synchronization detection unit 3.

On the other hand, a transmission clock for detecting the transmission data is input to the phase sweep section 4 through the input terminal 2 in parallel with the transmission data. The phase sweep unit 4 supplies a clock according to the input transmission clock to the frame synchronization detection unit 3.
The frame synchronization detector 3 synchronizes the frames of the input transmission data according to the input clock. The frame synchronization detection unit 3 outputs a synchronization detection signal indicating whether frame synchronization has been established to the sweep control unit 5.

The sweep control section 5 controls the phase sweep operation of the output clock of the phase sweep section 4 based on this synchronization detection signal. That is, when the transmission state on the transmission path is normal, the phase relationship between the transmission data input to the input terminal 1 and the transmission clock input to the input terminal 2 is appropriate, so the frame synchronization detection unit 3 performs Has been established. At this time, the phase sweep unit 4 does not perform the phase sweep operation, and outputs the clock fixedly at the phase at that time.

However, when the phase relationship between the transmission data and the transmission clock is not appropriate, the frame synchronization detection unit 3 has not established frame synchronization. The sweep control section 5 outputs a control signal for starting the sweep operation to the phase sweep section 4 in response to the input of the sync detection signal indicating that the frame synchronization has not been established. Therefore, the phase sweep section 4 inputs it to the frame sync detection section 3. Sweep the clock phase.

As a result, the phase of the input clock of the frame sync detector 3 gradually changes, and the frame sync detector 3 latches the input transmission data using this clock,
The frame sync code is detected. If the phase relationship between the transmission data and the clock is not appropriate, the synchronization is not established, so the phase sweeping operation of the phase sweeping unit 4 is continued.

Then, in the frame synchronization detecting section 3, synchronization is established when the phase relationship between the transmission data and the clock becomes appropriate. As a result, this synchronization establishment detection signal is input to the sweep control unit 5, and the sweep control unit 5 stops the sweep operation of the phase sweep unit 4. In this way, the data can be detected by latching the input transmission data with the output clock of the phase sweeping unit 4 when the frame synchronization is established.

[0009]

However, in the above-mentioned conventional method, only the phase of the clock with respect to the transmission data is swept, and the threshold level of the logic judgment of the input circuit of the frame synchronization detection section 3 is fixed. Figure 4
If the waveform of the data fluctuates due to common mode noise as indicated by a, it is impossible to suppress erroneous detection of the logic judgment of 1 and 0 due to the deterioration of the eye pattern that occurs during propagation of the transmission path. Is.

Further, since the clock phase is swept according to the presence / absence of frame synchronization establishment, the conventional method always causes data loss due to the establishment of frame synchronization when the phase relationship between the transmission data and the clock becomes unsuitable. There is a problem that the phase sweeping will not start until later.

The present invention has been made in view of the above points,
An object of the present invention is to provide a transmission data synchronization method that solves the above problems by performing sweep control based on the monitoring result of the line error rate.

[0012]

In order to achieve the above object, the present invention receives transmission data as an input signal, latches the transmission data based on an input clock, establishes frame synchronization, and establishes a frame in the input transmission data. A frame synchronization detection unit that detects the number of bit errors included in the synchronization code,
The number of bit errors detected by the frame synchronization detection unit is integrated for each frame, and an error rate calculation unit that calculates the line error rate and a transmission clock as an input signal are received by the frame synchronization detection unit in synchronization with the transmission clock. Outputs a clock and starts sweeping of the output clock of the phase sweeping unit whose phase is swept by a control signal and the line error rate from the error rate calculating unit is equal to or more than a predetermined set value. At the same time, a configuration is provided that has a sweep means for starting the logical decision level of each input circuit of the frame synchronization detection section and the phase sweep section, and sweeping the clock phase and the logical decision level so that the line error rate is minimized. It was done.

[0013]

In the present invention, when the line error rate calculated by the error calculating section exceeds a predetermined set value, the sweep means starts the sweep of the output clock of the phase sweep section. By selecting, the phase sweep of the output clock can be performed before the frame synchronization is not established. Further, according to the present invention, when the line error rate calculated by the error calculating section exceeds a predetermined set value, the sweeping means starts sweeping the logical decision level of each input circuit of the frame synchronization detecting section and the phase sweeping section. Therefore, the line error rate can be minimized.

[0014]

1 is a block diagram of an embodiment of the present invention. In the figure, the same components as those in FIG.
The description is omitted. In FIG. 1, the frame synchronization detection unit 11 establishes frame synchronization, detects the number of bit errors included in the frame synchronization code, and outputs the number of bit errors. The error rate calculation unit 12 integrates the number of bit errors in units of a predetermined frame period, and estimates and calculates the line error rate based on the sum.

The error rate setting unit 13 is a threshold value of the line error rate as to whether or not to start the phase sweep of the clock and the threshold level sweep of the logic judgment of each input circuit of the frame synchronization detection unit 11 and the phase sweep unit 15 which will be described later. The line error rate setting value corresponding to is output. The sweep control unit 14 compares the line error rate from the error rate calculation unit 12 with the set value from the error rate setting unit 13, and according to the comparison result, the phase sweep unit 15
Also, the start and stop of the sweep operation of the level sweep unit 16 are controlled.

The phase sweep section 15 outputs a clock for latching the transmission data, the phase of the output clock is controlled by the sweep control section 14, and the logic decision threshold level of the input circuit is swept. It is said that. In addition, the level sweeping unit 16 is provided for each input circuit of the frame synchronization detecting unit 11 and the phase sweeping unit 15.
Sweeps the threshold level for logical judgment of 1 "and" 0 ".

Next, the operation of this embodiment will be described.
The transmission data input to the frame synchronization detector 11 via the input terminal 1 is latched by the clock from the phase sweeper 15 here. The frame synchronization detection unit 11 detects the frame synchronization code, which is a known fixed pattern, added to each frame of the latched input transmission data, and compares the detected frame synchronization code with the correct original frame synchronization code. The number of bits with a bit error (the number of bit errors) is detected and output to the error rate calculation unit 12.

The error rate calculation unit 12 integrates the above-mentioned number of input bit errors in a predetermined frame cycle unit, and estimates and calculates the line error rate from the integrated value. That is, since the integrated value of the number of bit errors is not the integrated value of the number of bit errors of the entire transmission data but the integrated value of the number of bit errors of the frame synchronization code, it cannot be said to be the line error rate accurately, Since the bit error rate of the frame synchronization code and the bit error rate of data are generally almost the same, it can be said that the bit error rate calculated by the error rate calculation unit 12 substantially indicates the line error rate.

The sweep controller 14 includes the error rate calculator 12 described above.
The line error rate calculated by the above is compared with the set value from the error rate setting unit 13, and when the line error rate is equal to or larger than the set value, it is determined that the line quality state is deteriorated and the phase sweep unit 15 A control signal for starting the sweep is output to the level sweep unit 16. In this case, both the phase sweeping unit 15 and the level sweeping unit 16 may start sweeping simultaneously, or may start sweeping sequentially.

The level sweeping section 16 sequentially receives the threshold level of the logic judgment of each input circuit of the frame synchronization detecting section 11 and the phase sweeping section 15 from the minimum value to the maximum value at every unit time in response to the level control signal from the sweep control section 14. Change (sweep). Further, the phase sweep unit 15 sequentially changes the phase of the clock generated in synchronization with the transmission clock input via the input terminal 2 from the minimum value to the maximum value by the phase control signal from the sweep control unit 14 (sweep). Let).

As a result, the latch timing of the transmission data is sequentially changed in the frame synchronization detector 11,
Along with this, the line error rate calculated by the error rate calculation unit 12 also changes sequentially. In this way, the sweep control unit 1
As a result of the above sweep, the line error rate 4 is the error rate setting unit 13
The level control signal and the phase control signal which are less than the set value of and which can obtain the minimum line error rate are detected, and thereafter the detected level control signal and the phase control signal are fixedly output (that is, sweeping). Stop).

As a result, even if the data waveform (envelope) fluctuates due to common mode noise as shown in FIG. 2, the level control signal causes the threshold for logic judgment as shown by the dashed line in FIG. Since the line error rate is set to the minimum level after the level is swept, the synchronization state can be maintained.

When the line error rate calculated by the error rate calculation section 12 becomes equal to or larger than the value set by the error rate setting section 13, the sweep control section 14 again instructs the level sweep section 16 and the phase control section 15. Start the sweep. Then, as a result of the sweep, when the sweep control unit 14 determines that the line error rate is minimized, the sweep is stopped again. Thereafter, the same operation as above is repeated.

As described above, according to this embodiment, the line error rate calculated by the error calculating section 12 is calculated by the error rate setting section 13.
When a predetermined set value is exceeded, the sweep control section 14 sweeps the phase of the output clock of the phase sweep section 15, and the level sweep section 16 switches the input circuits of the frame synchronization detection section 11 and the phase sweep section 15 from each other. By starting the sweep of the logic judgment level, the phase of the output clock and the logic judgment level can be set before the frame synchronization is not established. Further, in the present embodiment, since the above sweep is performed so that the line error rate calculated by the error calculating unit 12 becomes the minimum, the line error rate can always be optimized.

[0025]

As described above, according to the present invention,
When the line error rate calculated by the error calculating section exceeds a predetermined set value, the sweeping means sweeps the output clock of the phase sweeping section and the logical judgment level of each input circuit of the frame synchronization detecting section and the phase sweeping section is changed. By starting the sweep,
Before the frame synchronization becomes unestablished, the optimum data and clock phases and logical decision levels can be set, and thus data loss due to the unestablished frame synchronization can be avoided in advance.

Further, according to the present invention, when the line error rate calculated by the error calculating section exceeds a predetermined set value,
The sweep means starts sweeping the logical judgment level of each input circuit of the frame synchronization detection section and the phase sweep section to minimize the line error rate, so it is optimal for the deterioration of the eye pattern that occurs during transmission of the transmission path. The logical decision level can be set at various positions, and thus the line error rate can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of a main part of FIG.

FIG. 3 is a block diagram of a conventional example.

FIG. 4 is a diagram for explaining the problem of FIG. 3;

[Explanation of symbols]

 1 Transmission Data Input Terminal 2 Transmission Clock Input Terminal 11 Frame Sync Detection Section 12 Error Rate Calculation Section 13 Error Rate Setting Section 14 Sweep Control Section 15 Phase Sweep Section 16 Level Sweep Section

Claims (2)

[Claims] 1. A frame synchronization for receiving transmission data as an input signal, latching the transmission data based on an input clock to establish frame synchronization, and detect the number of bit errors included in a frame synchronization code in the input transmission data. A detection unit, an error rate calculation unit that integrates the number of bit errors detected by the frame synchronization detection unit for each frame, and calculates a line error rate, and receives a transmission clock as an input signal and synchronizes with the transmission clock. A phase sweeping unit that outputs the clock to the frame synchronization detecting unit and the phase of which can be swept by a control signal, and the phase sweeping unit when the line error rate from the error rate calculating unit is a predetermined set value or more. Of the output clock of the frame synchronization detection section and the phase sweep section, the logical judgment level of each input circuit is started to sweep, A transmission data synchronization system characterized by comprising a sweep means for sweeping the clock phase and a logic decision level so that an error rate is minimized. 2. The sweep means sets an error rate setting section for setting a predetermined line error rate, and sets a logical decision level of each input circuit of the frame synchronization detection section and the phase sweep section, and sets the logical decision level to the logical decision level. When the level sweep unit that is capable of sweeping by the control signal is compared with the line error rate from the error rate calculation unit and the set value from the error rate setting unit, and the line error rate is equal to or greater than the set value. Is a sweep control unit that starts the sweep of the level sweep unit and the phase sweep unit, and stops the sweep when the line error rate is less than the set value and is minimum. The transmission data synchronization method according to claim 1.