JPH0766632A - Amplifier circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide an amplifier circuit in which the influence of power supply noise on the value of the differential output is reduced. [Structure] A transistor 230 is arranged between a load element 222 and a power supply terminal V _DD , and a bias voltage (Vb) based on V _SS is applied to the gate terminal of the transistor 230. Therefore, the bias voltage (Vb) does not change even if the potential value of the power supply terminal V _DD (hereinafter simply referred to as V _DD ) changes. Therefore, assuming that the transistor 230 is biased in the saturation region as shown in FIG. 2, even if V _DD fluctuates due to its constant current characteristic, the source potential (V
s) does not change. At this time, since the current flowing through the load element 222 is constant, the voltage across the load element 222 does not change, and as a result, the potential of the positive phase output does not change. That is, the potential of the positive phase output is determined with reference to V _SS as in the case of the negative phase output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier circuit used in an electronic device, and more particularly to an amplifier circuit used in a receiver in the field of optical communication.

[0002]

2. Description of the Related Art In a receiving circuit in the field of optical communication, an input signal is a single-phase signal accompanied by a change in DC level, and therefore, a single-ended type amplifying circuit is generally used as a preamplifying circuit. . A preamplifier equipped with such a single-ended type amplifier circuit is commercially available and widely used (for example, FMM321CP manufactured by Fujitsu Ltd.).

On the other hand, the main amplifier and the identification circuit used in the subsequent stage of the preamplifier circuit often have a differential circuit configuration. An example of such a differential circuit configuration is "MSAcarlar
et al .: Use of Low Cost Plastic DIPs and Injectio
n Molded Parts in Packaging of Optical Data Links,
Proceedings of ECTC '92 ”. When using a post-stage circuit having such a differential circuit configuration, when the output signal of the pre-amplifier circuit is in a differential format, the effective output amplitude value is doubled, so It has the advantage of being strong.

Therefore, it is desirable for the preamplifier circuit to have a function of amplifying an input single-phase signal and then converting it into a differential signal for output. As a method of designing an amplifier circuit having such a function, A configuration using a phase division circuit is known (supervised by Yoshikazu Kiyasu: "Amplification circuit design method for beginners", Ohmsha). FIG. 9 is a circuit configuration diagram of a preamplifier circuit using this phase division circuit. FIG. 9 (a)
Is a schematic circuit configuration diagram, and FIG. 9B is a circuit configuration diagram showing all the circuits of FIG. 9A at the basic element level. As shown in FIG. 9A, this circuit is an amplification unit 1 that inputs and amplifies a single-phase signal to be amplified and outputs a single-phase signal.
00 and a conversion unit 900 that inputs the single-phase signal output from the amplification unit 100, converts the single-phase signal into a differential signal, and outputs the differential signal. Here, in the conversion unit 900, a transistor 210 having a gate terminal for inputting a single-phase signal output from the amplification unit 100, a drain terminal of the transistor 210 and one terminal are connected, and the other terminal is connected to the V _DD potential. And a load element 221 having one terminal connected to the source terminal of the transistor 210 and the other terminal at the V _SS potential.

In this amplification circuit, the single-phase signal input to the amplification section 100 is amplified and input to the gate terminal of the transistor 210, and the source terminal (reverse-phase output) of the transistor 210 and the drain terminal (normal-phase output) of the transistor 210. )
The differential signal is output from and.

[0006]

Since the conventional amplifier circuit is constructed as described above, when a spike-shaped or sine-wave AC noise signal generated by the power source itself is superimposed on the power source (V _DD ) supply wiring, it is positive. This noise component is output only to the phase output. FIG. 10 is a graph showing changes in the output potential due to fluctuations in the power supply (V _DD ) (sweeping V _DD in the range of 4.5 V to 5.5 V) in the circuit of FIG. 9B. In this circuit, the amplification unit 100 has a transimpedance type circuit configuration, the voltage gain is sufficiently high at about 35 dB, and the output potential of the amplification unit 100 is determined with V _SS as a reference. Figure 10
As shown in, the fluctuation amount of the potential difference between the differential outputs is 0.97.
V, and the variation rate is as large as 97%.

The AC noise signal superimposed on the power source itself is 2 with respect to a DC voltage of 5V when operated in a bad environment.
It reaches as high as 00 mV _PP . Therefore, in the case of a pre-stage amplifier in an optical receiving circuit whose output signal amplitude is often weak, such as several mV to several tens mV, it is necessary to control the offset voltage for amplification by a post-stage comparator circuit to several mV or less. However, there is a problem that the offset voltage equivalently shifts due to power supply noise (see FIG. 11), and the receiver circuit cannot operate correctly.

The present invention has been made to solve this problem, and an object of the present invention is to provide an amplifier circuit in which the influence of power supply noise on the value of the differential output is reduced.

[0009]

SUMMARY OF THE INVENTION An amplifier circuit according to the present invention comprises an amplifier section for receiving and amplifying a first single-phase signal and outputting a second single-phase signal, and a second amplifier section for outputting a second single-phase signal. A conversion circuit for converting a single-phase signal into a differential signal and outputting the differential signal, wherein the output stage of the conversion unit is (a) a first input to the gate terminal of the amplified single-phase signal. A transistor,
(B) a first load element having one terminal connected to the source terminal of the first transistor and the other terminal connected to the first power supply terminal; and (c) a drain terminal of the first transistor. A second load element to which one terminal is connected,
(D) A second terminal whose source terminal is connected to the other terminal of the second load element and whose drain terminal is connected to the second power supply terminal
And (e) a bias circuit that supplies a bias voltage based on the voltage value of the first power supply terminal to the gate terminal of the second transistor, the source terminal of the first transistor and the first The drain terminal of the transistor is used as a differential signal output terminal.

Here, the first and second transistors may be field effect transistors. Further, the first and second load elements can be composed of resistors or field effect transistors.

In addition to the bias voltage generated by the bias circuit, the voltage supplied to the gate terminal of the second transistor is superposed with an AC signal having a phase inverted from the phase of the output signal of the amplifier. It may be characterized by that. Here, the output stage of the amplification section includes a level shift section, and the bias circuit outputs the level shift section, has different DC potentials, and has a DC potential higher than the DC potential of the second single-phase signal. A first buffer circuit for inputting a signal having a higher DC potential of the two signals, a second buffer circuit for inputting a signal having a lower DC potential of the two signals, and a first buffer circuit And the signal output from the second buffer circuit is input,
A phase inversion circuit that generates and outputs a phase-inverted signal,
May be provided.

In this phase inverting circuit, a third transistor for inputting a signal output from the first buffer circuit to a gate terminal and a signal output from a second buffer circuit are input to the gate terminal, and the drain terminal is the above-mentioned. A fourth transistor connected to the source terminal of the third transistor may be provided, and a phase-inverted signal may be output from the source terminal of the third transistor. here,
The gate width of the fourth transistor may be larger than the gate width of the third transistor, and the threshold voltage of the fourth transistor is shallower than the threshold voltage of the third transistor, It may be characterized.

[0013]

In the amplifier circuit of the present invention, when the reference first power supply potential is set to the source side potential (hereinafter referred to as the reference source potential), the amplifier circuit is connected to the first transistor for outputting the differential signal in the output stage. The bias circuit generates a bias voltage applied to the gate of the second transistor connected via the load element connected to the drain terminal of the first transistor, with the reference source potential as a reference.

The first single-phase signal input to the amplifier in this state is amplified by the amplifier and then becomes a second single-phase signal, which is input to the gate terminal of the first transistor. At this time, the bias voltage value does not change even if the potential supplied to the drain side changes. If the voltage gain of the amplification section is sufficiently high, the potential at the output point of the amplification section is determined based on the reference source potential, and the current flowing through the output circuit including the first transistor is constant. Therefore, assuming that the second transistor is biased in the saturation region, even if the drain potential of the second transistor changes due to its constant current characteristic, the potential of the source terminal does not change. At this time, since the current flowing through the second load element is constant, the voltage across the second load element does not change, and as a result, the potential of the positive phase output does not change. That is, the potential of the positive phase output is determined with reference to the reference source potential as in the case of the negative phase output, and the voltage value between the differential signals is not easily influenced by the fluctuation of the potential value supplied to the drain side.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to the description of the embodiments of the amplifier circuit of the present invention, the outline of the amplifier circuit of the present invention will be described. FIG. 1 is a schematic configuration diagram of an amplifier circuit of the present invention. As shown in Figure 1,
This circuit includes a transistor 230 between the load element 222 and the power supply terminal V _DD of the conventional amplifier circuit shown in FIG.
And a bias voltage (Vb) based on the potential value of the power supply terminal V _SS (hereinafter simply referred to as V _SS ) is applied to the gate terminal of the transistor 230. Therefore, the bias voltage (Vb) hardly changes even if the potential value of the power supply terminal V _DD (hereinafter simply referred to as V _DD ) changes. Also,
If the voltage gain of the amplifier 100 is sufficiently high, the amplifier 100
The potential (Va) at the output point is determined with reference to V _SS , and the current flowing through the output circuit including the transistor 210 is substantially constant. Therefore, assuming that the transistor 230 is biased in the saturation region as shown in FIG. 2, even if the drain potential (that is, V _DD ) of the transistor 230 varies due to its constant current characteristic, the source potential (Vs) is almost constant. It does not change. At this time, since the current flowing through the load element 222 is constant, the voltage across the load element 222 hardly changes, and as a result, the potential of the positive phase output hardly changes. That is, V _SS as well as the reverse phase output
The potential of the positive phase output is determined with reference to. FIG. 3 is a graph explaining this differential output operation. Figure 3 (a) shows V _SS
3 is a case where V _DD fluctuates while _keeping V constant, and FIG. 3B shows a case where V _SS fluctuates. In either case, the potential of the positive phase output and the potential of the negative phase output are based on V _SS , so the difference voltage is substantially constant.

(First Embodiment) FIG. 4 is a block diagram of an amplifier circuit according to the first embodiment of the present invention. FIG. 4A is a device-level circuit configuration diagram of this circuit. As shown in FIG. 4A, this circuit includes an amplification unit 100 and a conversion unit 300. Here, the amplification unit 100 has the same configuration as the conventional one.

The conversion unit 300 has a FET 210 for inputting a single-phase signal output from the amplification unit 100 to a gate terminal.
And a resistance element 221 having one terminal connected to the source terminal of the FET 210 and the other terminal connected to V _SS ,
A resistance element 222 having one terminal connected to the drain terminal of the FET 210, a FET 230 having a source terminal connected to the other terminal of the resistance element 222 and a drain terminal connected to V _DD , and a FET 3 forming a bias circuit.
10 and a resistance element 320.

A bias voltage based on V _SS generated by the FET 310 and the resistance element 320 is supplied to the gate terminal of the FET 230. FE with this bias voltage
The operation of T230 is a saturated region operation. Therefore, as described above, the potential of the positive phase output and the potential of the negative phase output are V _SS
Is determined based on. FIG. 4B is an explanatory diagram of the operation of this circuit. As shown in Fig. 4 (b), _VDD is 4.5V
When swept in the range of up to 5.5 V, the fluctuation rate of the output-to-output potential difference is 2.6%, which is a significant improvement over the prior art.

(Second Embodiment) FIG. 5 is a block diagram of an amplifier circuit according to a second embodiment of the present invention. FIG. 5A is a device-level circuit configuration diagram of this circuit. As shown in FIG. 5A, this circuit includes an amplification unit 100 and a conversion unit 400. Here, the amplification unit 100 has the same configuration as the conventional one.

The conversion unit 400 has a FET 210 for inputting the single-phase signal output from the amplification unit 100 to a gate terminal.
And a resistance element 221 having one terminal connected to the source terminal of the FET 210 and the other terminal connected to V _SS ,
A resistance element 222 having one terminal connected to the drain terminal of the FET 210, a FET 230 having a source terminal connected to the other terminal of the resistance element 222 and a drain terminal connected to V _DD , and an FET group forming a bias circuit. And a resistance element group.

The circuit of this embodiment obtains Vb as a DC potential generated from the output of the amplifier 100. Note that Vb needs to be generated from the output of the level shift stage having a higher potential than Va of the amplification unit 100. Here, if a large capacitance is connected to the output of the level shift stage, the operating band is deteriorated. Therefore, a buffer circuit using a source follower is added in the bias circuit. Furthermore, the output of the level shift stage has the same phase as Va, so V
When applied to b, the signal output from the positive phase output terminal and the signal output from the negative phase output terminal have the same phase, so that the original intended differential signal cannot be obtained. Therefore, a phase inverting circuit is formed by the FET 410 and the FET 420, and the output of the level shift stage passes through this phase inverting circuit to generate Vb and obtain a differential signal output. At this time, the gate width of the FET 420 is set to FE
Make it wider than the gate width of T410 or FET420
By making the threshold voltage of the FET 410 shallower than the threshold voltage of the FET 410, the input potential (V
c) and the input potential (V
The phases of d) and Vb can be inverted.

In this way, the bias voltage Vb based on V _SS is supplied to the gate terminal of the FET 230. The operation of the FET 230 by this bias voltage is a saturation region operation. Therefore, as described above, the positive-phase output potential and the negative-phase output potential are determined with V _SS as a reference. Further, when the phase inverting circuit as described above is used, the output circuit performs the push-pull operation, so that there is an effect of improving the gain with respect to the input signal to the amplifying unit 100. FIG. 5B is an explanatory diagram of the operation of this circuit. As shown in FIG. 5B, V
_{When DD} is swept in the range of 4.5 V to 5.5 V, the fluctuation rate of the output-to-output potential difference is 0.3%, which is improved compared to the first embodiment.

(Third Embodiment) FIG. 6 is a block diagram of an amplifier circuit according to a third embodiment of the present invention. As shown in FIG. 6, in this circuit, in the converter 500, the formation of the load element by the resistance element of the second embodiment shown in FIG. 5 is the formation of the load element by the FETs 223 and 224 in which the gate and the source are short-circuited. Only the points differ.

The circuit of the present embodiment operates in the same manner as the circuit of the second embodiment, but since the FET having the gate and the source short-circuited is used as the load element, the amount of attenuation in the output circuit where the impedance of the output load is high. Is less. Specifically, according to an experiment by the inventor, the output load resistance is 1.5
In the case of kΩ, it was confirmed that the gain of the entire circuit is improved by 0.6 dB as compared with the circuit of the second embodiment.

(Fourth Embodiment) FIG. 7 is a block diagram of an amplifier circuit according to a fourth embodiment of the present invention. As shown in FIG. 7, the circuit of the present embodiment is the same as the conversion unit 600 shown in FIG.
An output buffer circuit of a source follower is further added to the output of the circuit of the embodiment.

The circuits of the first to third embodiments are very effective circuits when the terminating resistance on the output load side is terminated to the potential with reference to V _SS . However, the terminating resistance on the output load side may not be terminated to a potential based on V _SS depending on the usage of the amplifier circuit.

Since the differential signal outputs of the amplifier circuit of the present invention have different DC potentials, they are AC-connected to the circuit in the subsequent stage. FIG. 8 is an explanatory diagram of an output circuit including a terminating resistor in a frequency region higher than the time constant of this AC coupling. Figure 8
FIG. 8A is an equivalent circuit diagram when terminated with V _SS , and FIG. 8B is an equivalent circuit diagram when terminated with V _DD . Here, Va and Vb are
Both are completely based on V _SS , and are grounded when V _SS = GND. AC component superimposed on V _DD terminal is v
Assuming that dd is the positive-phase output noise AC component and v2 is the negative-phase output noise AC component, in the case of FIG. 8A, v1 = v2 = 0 (1) The fluctuation rate of the potential difference is 0.
However, in the case of FIG. 8B, v1 = 2Gl / (Gb + Gl) .vdd (2) v2 = Gl / (gma + Ga + Gl) .vdd (3) where Gl: conductance of the terminating resistor Ga: antiphase output Side load element conductance Gb: Positive phase output side load element conductance gma: Mutual conductance of output transistor (Qa). As a general value, for example, Gl = 0.67m
S, Ga = 2.9 mS, Gb = 5.0 mS, gma = 2
Assuming 5 mS, v1 = 0.24 vdd and v2 = 0.023 vdd, and the fluctuation rate of the potential difference between the differential outputs reaches about 20%.

Therefore, the circuit of this embodiment is a circuit in which the output transistor 210 and the terminating resistor are separated by a buffer circuit. The circuit of this embodiment operates similarly to the second embodiment up to the differential output from the FET 210, and the differential output from the FET 210 outputs a differential signal to the outside through the buffer circuit of the source follower. Therefore, regardless of whether the termination end of the termination resistor is based on V _SS or V _DD , the effect is exhibited regardless of that. Note that the addition of a source follower buffer circuit causes an increase in power consumption and a decrease in total gain. Therefore, regarding the addition of this buffer circuit,
It is necessary to make a comprehensive decision in consideration of the actual usage mode.

The present invention is not limited to the above embodiment, but can be modified. For example, the change of the configuration of the load element as in the third embodiment with respect to the second embodiment is also possible in the first embodiment and the fourth embodiment, and the same effect is obtained. Further, the addition of the output buffer circuit as in the fourth embodiment to the second embodiment can be similarly changed in the first and third embodiments, and the same effect can be obtained.

[0030]

As described in detail above, according to the amplifier circuit of the present invention, a transistor is arranged in series at the output stage on the side opposite to the reference potential side of the signal output transistor, and the gate terminal of this transistor is provided. Since the bias voltage to be supplied is generated with reference to the reference potential, both signals of the differential signal output of the output transistor are not easily affected by potential fluctuations other than the reference potential, and the fluctuation of the reference potential , The voltage value between the differential signals that is stable with respect to the power supply noise can be output.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an amplifier circuit of the present invention.

FIG. 2 is an operation explanatory diagram of the FET.

FIG. 3 is an explanatory diagram of an operation outline of an amplifier circuit of the present invention.

FIG. 4 is a configuration diagram of an amplifier circuit according to a first embodiment of the present invention.

FIG. 5 is a configuration diagram of an amplifier circuit according to a second embodiment of the present invention.

FIG. 6 is a configuration diagram of an amplifier circuit according to a third embodiment of the present invention.

FIG. 7 is a configuration diagram of an amplifier circuit according to a fourth embodiment of the present invention.

FIG. 8 is an equivalent circuit diagram of an output circuit having a terminating resistor.

FIG. 9 is a configuration diagram of a conventional amplifier circuit.

FIG. 10 is an operation explanatory diagram of a conventional amplifier circuit.

FIG. 11 is an explanatory diagram of the influence of offset in a conventional amplifier circuit.

[Explanation of symbols]

100 ... Amplifying unit, 200, 300, 400, 500, 6
00,900 ... Converter, 210, 223, 224, 31
0,410,420 ... FET, 221,222,320
... resistive element.

Claims (9)

[Claims] 1. An amplifying unit for inputting and amplifying a first single-phase signal to output a second single-phase signal, and converting the second single-phase signal output from the amplifying unit into a differential signal. And a conversion unit that outputs the first output signal of the conversion unit, wherein the output stage of the conversion unit includes a first transistor that inputs an amplified single-phase signal to a gate terminal, and a source terminal of the first transistor. A first load element having one terminal connected to the first power supply terminal and the other terminal connected to the first power supply terminal, and a second load element having one terminal connected to the drain terminal of the first transistor A second transistor having a source terminal connected to the other terminal of the second load element and a drain terminal connected to a second power supply terminal; and a voltage value of the first power supply terminal as a reference. Bias voltage is applied to the gate terminal of the second transistor A bias circuit for supplying the child to the child, and a source terminal of the first transistor and a drain terminal of the first transistor as differential signal output terminals. 2. The first and second transistors are field effect transistors.
The described amplifier circuit. 3. The amplifier circuit according to claim 1, wherein the first and second load elements are resistors. 4. The amplifier circuit according to claim 1, wherein the first and second load elements are field effect transistors. 5. A voltage supplied to the gate terminal of the second transistor, in addition to the bias voltage generated by the bias circuit, an AC signal having a phase inverted with respect to the phase of the output signal of the amplification unit. 2. The amplifier circuit according to claim 1, wherein is superimposed. 6. The output stage of the amplification section includes a level shift section, and the bias circuit outputs different DC potentials from the level shift section and has a DC potential higher than that of the second single-phase signal. A first buffer circuit for inputting a signal having a higher DC potential of two signals having a high DC potential, and a second buffer circuit for inputting a signal having a lower DC potential of the two signals And a phase inverting circuit that inputs signals output from the first buffer circuit and the second buffer circuit, generates a phase-inverted signal, and outputs the phase-inverted signal. The described amplifier circuit. 7. The phase inverting circuit inputs a signal output from the first buffer circuit to a gate terminal of a third transistor, and a signal output from the second buffer circuit to a gate terminal, A fourth transistor whose drain terminal is connected to the source terminal of the third transistor; and outputting the phase-inverted signal from the source terminal of the third transistor. The described amplifier circuit. 8. The gate width of the fourth transistor is
8. The amplifier circuit according to claim 7, wherein the gate width of the third transistor is larger than that of the third transistor. 9. The threshold voltage of the fourth transistor is
The amplifier circuit according to claim 7, wherein the amplifier circuit is shallower than a threshold voltage of the third transistor.