JPH0766625B2 - Disk interface circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a disk interface circuit.

[Technical background of the invention and its problems]

Mini floppy disks have been rapidly spreading as external memories for personal computers or desktop type computers since they were announced in 1976.

FIG. 1 shows a configuration example of this type of floppy disk control system. In the figure, 11 is a processor unit (CPU), 1
2 is a memory unit, 13 is a floppy disk controller (FDC), 14 is a disk drive mechanism (FDD) in which a floppy disk is loaded, 15 is another input / output controller (I / OC), 16 is input / output such as keyboard and display Is a device. 11/12/13/15 above is system bus 17
Commonly connected to. An oscillator 131, a frequency divider circuit 132, and a VFO are provided around the FDC 13 as an FDD interface circuit.
(Variable Frequency Oscillator) circuit 133 is connected.

In the above configuration, the READ data (▲ ▼) obtained via the FDD14 is FM when using a single-density floppy disk.
Since it is modulated, a clock pulse is inserted at each bit break (data "1" has a pulse, data "0" has no pulse). Also, the read data (▲ ▼) is
Due to the fluctuation of rotation of the FDD mechanism (± 2%) and the peak shift when converting from magnetic to electric signals, the output is slightly different from the normal timing. Therefore, this read data is supplied to the FDC 13 via the VFO circuit 133.

The VFO circuit 133 corrects the phase of the read data, generates the data to the FDC 13 as a window signal synchronized with the deviation of the read data (▲ ▼), and
The FDC 13 according to this window signal by sending to 3 samples the read data, converts it into parallel data, and outputs it to the processor unit 11 or the memory unit 12 via the system bus 17.

By the way, in the standard mini floppy disk drive mechanism (mini FDD), the mini floppy disk is 300
It rotates at r.p.m, and regular data read / write is performed based on this number of rotations. On the other hand, some mini FDDs that read / write data at a different rotation speed from this standard, for example, 288r · p · m are also used.

Hereinafter, the former will be referred to as a standard mini FDD and the latter will be referred to as a specific mini FDD.

Floppy disk formatted and written in a specific mini FDD is loaded into a standard mini FDD and data is read.
In addition to the timing error of READ data due to the above rotation fluctuation and peak shift, the rotation difference of -4%
Is superimposed, the timing of the read data (▲ ▼) will be significantly different from the standard. For this reason,
The VFO circuit 133 cannot generate the window signal synchronized with the read data (▲ ▼), so that the correctly recorded data cannot be read correctly. In order to solve this, it is conceivable to switch the motor speed of the standard FDD according to the specific mini FDD, but it requires a special motor and drive circuit, and it is not preferable to apply it to this type of system aiming at cost reduction. Inconvenience occurs.

[Object of the Invention]

The present invention has been made based on the above circumstances, and FDD
It is an object of the present invention to provide a disk interface circuit that realizes data read / write of a floppy disk that is formatted or written at different rotation speeds by adopting a configuration in which the basic timing signal is switched while keeping the rotation speed of the disk constant. .

[Outline of Invention]

In order to achieve the above object, the present invention operates a VFO circuit that performs a floppy disk controller that performs format control of a floppy disk and read / write control of data and a phase correction of READ data, and that supplies the floppy disk controller to the VFO circuit. A plurality of oscillators that generate and output the basic timing signal, a selector that selectively outputs one of the oscillator outputs, and an instruction setting for this selector under the control of the processor unit. The flip-flop circuit is added as a part of the disk interface circuit.

This allows the standard mini FDD to perform data read / write of mini floppy disks formatted and written at different speeds by switching the basic timing signal while keeping the speed of mini floppy disk constant. Therefore, a flexible floppy disk control system can be provided.

Example of Invention

Hereinafter, the embodiment of the present invention will be described in detail with reference to FIG.

FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, blocks designated by the same numbers as in FIG. 1 are the same as those in FIG. The difference from the conventional example shown in FIG. 1 is that one more oscillator is added, and this oscillator 301, 302
Get the output and the one specified by the processor unit 11,
The point is that a selector 303 for selecting and outputting one of the inputs via the flip-flop 304 is added. Oscillator 3
01 generates clock to control standard mini FDD,
The oscillator 302 generates a clock for controlling a specific mini FDD.

3 and 4 show the read data (▲ ▼) from the data written on the mini-floppy disk by the VFO circuit 133.
And the window pulse (WINDOW) are separated. The former is an example where the synchronization is successful, the latter is the synchronization (▲ ▼ and WINDOW) is not successful and the data recorded on the floppy disk is An example of unreadable data is shown.

The operation of the embodiment of the present invention shown in FIG. 2 will be described below with reference to the timing charts shown in FIGS. First, in a standard floppy disk read operation, the flip-flop 304 is set to “0”, the clock generated and output from the oscillator 301 is selected by the selector 303, and the selected clock is supplied to the frequency dividing circuit 132. Here, the clock is divided into an appropriate value and supplied to the VFO circuit 133.
The output signal of the frequency divider circuit 132 is set so as to be synchronized with the average bit period of the standard floppy disk data (▲ ▼) read via the FDD 14, and the VFO circuit 1
33 performs phase correction of the read data (▲ ▼ ₀ ) by this, and the read data (▲ ▼) corrected here
And a window pulse (WINDOW) to FDC13. This situation is shown in the timing chart of FIG.

Here, the VFO circuit 133 uses the read data to
, ▲ ▼ has a clock pulse at each bit break, and has a data pulse indicating "1" of data in the middle. A standard floppy disk has a clock pulse interval of about 8 μs and a clock pulse and data pulse interval of about 4 μs. Also, the WINDOW signal is output in 8 μs, which is the same cycle as ▲ ▼.

Note that the internal operations of the FDC 13 and the VFO circuit 133 are generally known and are not directly related to the gist of the present invention, so the description thereof is omitted here. Read data is FDD14
It is affected by fluctuations in rotation of the motor and peak shifts when converting magnetic signals to electrical signals.
The O circuit 133 absorbs this to some extent and corrects the phase.
Supply to FDC13. This tolerance is generally about ± 2%.

However, a standard floppy disk with a standard FDD14 (300
When read out at (rpm), data will appear in a relatively short cycle (about 4% in this example). If rotation fluctuations are further added to this, the fluctuation allowable value of the VFO circuit 133 will be far exceeded as described above, and as a result, the synchronized ▲ ▼ and WINDOW signals cannot be supplied to the FDC 13, and the floppy disk This causes a situation in which the data recorded in can not be read. This situation is shown in the timing chart of FIG. This example shows the timing when the synchronization becomes short by about 6%, and it can be seen that the synchronization deviation between ▲ ▼ and the WINDOW signal becomes remarkable from the vicinity of the fourth data bit.

Therefore, in the present invention, the flip-flop 304 is set to "1" when reading a floppy disk formatted and written by a specific FDD. Of course, the processor unit 11 does this via the system bus 17. As a result, the selector 303 selects the clock generated and output by the oscillator 302. This clock is set so that it can be synchronized with the data cycle of the specific FDD, and in this example, it is 4% faster than the clock of the oscillator 301. The clock is divided by the frequency dividing circuit 305 and the VFO circuit 13
Supplied to 3. As a result, the VFO circuit 133 correctly synchronizes the read data of the floppy disk formatted and written by the specific FDD with ▲ ▼ and WI.
NDOW can be supplied to FDC13.

Although the above description has described only the read operation, the same applies to the write operation and the formatting. That is, during the write operation of the standard floppy disk, the clock of the oscillator 301 is selected by setting the flip-flop 304 to “0”, and the frequency dividing circuit 305 is selected.
By passing through it, a write clock synchronized with the standard FDD rotation speed (300 rpm) is generated and supplied to the FDC 13. In addition, the flip-flop 30
The clock of the oscillator 302 is selected by setting 4 to “1”, and the specific FDD rotation speed (288 rpm) is passed through the frequency dividing circuit 305.
It generates a write clock synchronized with and supplies it to the FDC 13. In this way, by switching the value of the flip-flop 304, it is possible to realize a floppy disk read in which data is written in FDDs with different rotation speeds.
Further, it is possible to easily perform control such as writing and formatting data on a floppy disk for reading by FDDs having different rotation speeds.

In the embodiment of the present invention, the number of rotations is limited to two types, but the number of rotations is not limited to this, and three or more types can be similarly realized.

〔The invention's effect〕

As described above, according to the present invention, a floppy disk formatted and written by a floppy disk drive mechanism having a rotation speed different from the standard rotation speed is formatted, written by a disk drive mechanism having a standard rotation speed, and written. A floppy disk control system that can be read and has high flexibility can be provided. Furthermore, the present invention compares the method of directly changing the rotation speed of the floppy disk by DC servo control,
It is cheap and easy to implement.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a conventional floppy disk control system, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIGS. 3 and 4 are VFO based on data written on a floppy disk. 6 is a timing chart showing how the circuit separates the read data and the window signal. The former is shown as an example in which the synchronization is successful, and the latter is shown as an example in the case where the recorded data cannot be read due to the lack of synchronization. 11 …… Processor unit (CPU), 13 …… Floppy disk controller (FDC), 14 …… Floppy disk drive (FDD), 133 …… VFO circuit, 301,302 …… Oscillator (OSC), 303 …… Selector (SEL) , 304 …… Flip-flop (F / F).

Claims (2)

[Claims] 1. A first recording data recorded on a disk medium by a first disk device having a first rotation speed, and a second recording speed having a second rotation speed different from the first rotation speed. The second recorded on the disk medium by the disk device
In a disk interface circuit for reading the recorded data of 1. by a single disk device, a clock generating means for generating a first basic clock and a second basic clock different from the first basic clock, and the first and second Input the basic clock of
A selector for selectively outputting one of the first and second basic clocks in accordance with identification data indicating whether to read the first recording data or the second recording data, and the selector outputs the selector clock. A disk interface circuit comprising: means for reading data from a disk medium according to a basic clock. 2. A disk interface circuit for reading recorded data recorded on a disk medium by three or more kinds of disk devices each having a different rotation speed by a single disk device, the disk interface circuit corresponding to each disk device having a different rotation speed. The clock generation means for generating a plurality of basic clocks each having a different cycle, and the plurality of basic clocks generated by the clock generation means are input to the identification data indicating which disk device is to read the recorded data. Accordingly, the disk interface circuit comprises: a selector for selectively outputting one of the plurality of basic clocks; and means for reading data from the disk medium according to the basic clock output from the selector.