[go: up one dir, main page]

JPH0766355A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0766355A
JPH0766355A JP5237394A JP23739493A JPH0766355A JP H0766355 A JPH0766355 A JP H0766355A JP 5237394 A JP5237394 A JP 5237394A JP 23739493 A JP23739493 A JP 23739493A JP H0766355 A JPH0766355 A JP H0766355A
Authority
JP
Japan
Prior art keywords
die pad
semiconductor device
slits
slit
longitudinal direction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5237394A
Other languages
Japanese (ja)
Inventor
Kazuaki Ishida
和明 石田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP5237394A priority Critical patent/JPH0766355A/en
Publication of JPH0766355A publication Critical patent/JPH0766355A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To provide a semiconductor device wherein the dimensioned accuracy of depression processing of a die pad is stabilized and any stay shift is scarcely generated at the time of molding. CONSTITUTION:A semiconductor device 10 has a die pad 12 which is fixed to a lead frame by suspension parts 18, 20 stretching from a peripheral part. Slits 14 arranged in the length direction and slits 16 arranged in the width direction are formed in the die pad. The suspension parts 18, 20 stretch outward from the peripheral part isolated from die pad regions 15, 22 in the length direction virtual extension parts of the respective slits 14, 16.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置に関し、更
に詳細には、大型の半導体装置であっても必要なデップ
レス加工精度を維持し、樹脂封止時にステイシフトが発
生し難いようなダイパッド構造を備えた半導体装置に関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a die pad which maintains a necessary precision of a deep press even in a large semiconductor device and is less likely to cause a stay shift during resin sealing. The present invention relates to a semiconductor device having a structure.

【0002】[0002]

【従来の技術】近年生産量が増大して来た樹脂封止型の
薄型パッケージ(TSOP TQFP)において、パッ
ケージ構造の加工精度及び品質を向上させるには、リー
ドフレームの加工精度を許容値以内に収め、その後の樹
脂封止工程等での加工精度を維持することが重要であ
る。よって、リードフレームの加工精度の管理は、半導
体装置の品質管理上で大変重要なウェイトを占めて来て
いる。ところで、リードフレームの加工精度を向上させ
るには、リードフレームの要部を構成するダイパッド構
造を検討することが重要である。
2. Description of the Related Art In a resin-sealed thin package (TSOP TQFP) whose production has been increasing in recent years, in order to improve the processing accuracy and quality of the package structure, the processing accuracy of the lead frame is set within an allowable value. It is important to keep the processing accuracy in the resin encapsulation process after the packaging. Therefore, control of the processing accuracy of the lead frame has become a very important weight in quality control of semiconductor devices. By the way, in order to improve the processing accuracy of the lead frame, it is important to study the die pad structure that constitutes the main part of the lead frame.

【0003】図6(a)は半導体装置の従来のダイパッ
ド構造を示す平面図、及び図6(b)はその斜視図を示
している。従来のダイパッド構造60では、図6
(a)、(b)に示すように、ダイパッド62にスリッ
ト64(この場合2個のスリット)が長手方向に配列さ
れた、またスリット66(この場合2個のスリット)が
幅方向に配列されている。ダイパッド62の四辺からそ
れぞれ対向して吊り部が延出しており、ダイパッド62
は、長手方向には対の吊り部68、幅方向には対の吊り
部70により支えられている。また、図6(b)に示す
ように、ダイパッド62の周囲には多数のインナーリー
ド72が外方に向け延びていて、ダイパッド62にダイ
ボンドされた半導体チップ(図示せず)は、金線(図示
せず)によりそれらインナーリード72に接続される。
FIG. 6A is a plan view showing a conventional die pad structure of a semiconductor device, and FIG. 6B is a perspective view thereof. In the conventional die pad structure 60, as shown in FIG.
As shown in (a) and (b), slits 64 (in this case, two slits) are arranged in the die pad 62 in the longitudinal direction, and slits 66 (in this case, two slits) are arranged in the width direction. ing. The hanging portions extend from the four sides of the die pad 62 so as to face each other.
Are supported by a pair of hanging portions 68 in the longitudinal direction and a pair of hanging portions 70 in the width direction. Further, as shown in FIG. 6B, a large number of inner leads 72 extend outward around the die pad 62, and the semiconductor chip (not shown) die-bonded to the die pad 62 is a gold wire ( These are connected to the inner leads 72 by (not shown).

【0004】尚、図7(a)、(b)、(c)及び
(d)は、それぞれ図6に示す吊り部とスリットとの配
置とは異なる配置のダイパッド構造又は大型ダイパッド
のスリットと吊り部の配置を示す。
7 (a), 7 (b), 7 (c) and 7 (d) respectively show a die pad structure or a large die pad slit and suspension which are different from the suspension portion and slit arrangement shown in FIG. The arrangement of parts is shown.

【0005】ダイパッド62に設けたスリット64、6
6は、基板実装時のリフローによる熱応力を分散させ、
これにより封止樹脂にクラックが発生するのを抑制して
いる。従って、スリットは、薄型の樹脂封止型パッケー
ジにおいてクラックの発生を防止して製品歩留りを向上
させるのに必須なものである。また、近年の半導体チッ
プの大型化により、ダイパッドの長手方向の対の吊り部
68だけでは、大型のダイパッド構造を支えきれず、後
の工程である金線を接続するワイヤボンディング工程、
或いは樹脂封止工程での精度保証が難しくなったため、
ダイパッドの幅方向端縁にも対の吊り部70を設けて、
ダイパッド構造の吊り強度を補強している。
Slits 64, 6 provided in the die pad 62
6 is to disperse the thermal stress due to reflow at the time of board mounting,
This suppresses the occurrence of cracks in the sealing resin. Therefore, the slit is indispensable for preventing the occurrence of cracks in the thin resin-sealed package and improving the product yield. Also, due to the recent increase in the size of semiconductor chips, the pair of hanging portions 68 in the longitudinal direction of the die pad cannot support the large die pad structure, and a wire bonding step for connecting a gold wire, which is a later step,
Or because it became difficult to guarantee accuracy in the resin encapsulation process,
Providing a pair of hanging portions 70 also on the widthwise edge of the die pad,
The suspension strength of the die pad structure is reinforced.

【0006】[0006]

【発明が解決しようとする課題】しかし、半導体装置の
大型化に伴い、ダイパッド自体が益々大型化すると共
に、上述の従来のダイパッド構造では、必要なダイパッ
ド強度及びデップレス加工精度を維持することが困難に
なり、そのためモールド成形時にステイシフトが発生す
ると言う問題が生じていた。
However, as the size of the semiconductor device increases, the size of the die pad itself becomes larger and larger, and it is difficult to maintain the required die pad strength and the precision of the depth pressing with the above-mentioned conventional die pad structure. Therefore, there has been a problem that a stay shift occurs during molding.

【0007】ここで、デップレス加工とは、リードフレ
ームの吊り部にプレスによるスタンピング加工により施
されていて、デップレスの加工位置は、ダイパッドを吊
る吊りの位置に応じて決められるものである。デップレ
ス加工精度とは、デップレス加工の寸法精度を意味す
る。また、ステイシフトとは、モールド樹脂をモールド
金型に注入して、モールド成形する時、モールド樹脂の
注入圧力によりリードフレームがモールド金型の当初設
定位置より上下方向に移動する現象を言う。
The term "depressing" means that the hanging portion of the lead frame is stamped by a press, and the processing position of the depressing is determined according to the hanging position of hanging the die pad. The accuracy of deep pressing means the dimensional accuracy of deep pressing. The stay shift refers to a phenomenon in which, when a molding resin is injected into a molding die and molding is performed, the lead frame moves vertically from an initial setting position of the molding die due to the injection pressure of the molding resin.

【0008】以上の問題に鑑み、本発明の目的は、必要
なデップレス加工精度を維持して、モールド成形時にス
テイシフトが発生し難いように改良されたダイパッド構
造を備えた半導体装置を提供することである。
In view of the above problems, it is an object of the present invention to provide a semiconductor device having an improved die pad structure which maintains the required precision of the depression process and is less likely to cause a stay shift during molding. Is.

【0009】[0009]

【課題を解決するための手段】本発明者等は、大型半導
体装置、即ち大型ダイパッド構造のデップレス加工精度
について研究し、次の知見を得た。第1として、デップ
レス加工時に発生する応力は、主として吊り部70に発
生する引張応力等であって、図4(a)を参照して説明
すると、吊り部70を介して吊り部基端のダイパッド部
分(図4(a)に示すA領域)に集中する。従来の半導
体装置では、ダイパッド領域B(スリット66の長手方
向仮想延長部分)から吊り部70が延出しているため、
その部分にデップレス加工による応力が集中し、しかも
その部分は、スリットの開口により強度が低下している
ため、変形が生じ易く、よってデップレス加工の精度が
低下する。また、ダイパッドのスリットと吊り部との位
置関係によりダイパッド側の応力集中状態、従って変形
程度が異なることを見い出した。
Means for Solving the Problems The inventors of the present invention have studied the precision of a large semiconductor device, that is, the precision of a large die pad structure, and obtained the following findings. Firstly, the stress generated during the deep pressing is mainly a tensile stress generated in the hanging portion 70, and will be described with reference to FIG. 4A. The die pad at the base end of the hanging portion via the hanging portion 70 will be described. It concentrates on a part (A area shown in FIG. 4A). In the conventional semiconductor device, since the hanging portion 70 extends from the die pad region B (the virtual extension of the slit 66 in the longitudinal direction),
Stress due to the deep pressing is concentrated on that portion, and since the strength of the portion is reduced due to the opening of the slit, deformation is likely to occur, and thus the precision of the deep pressing is reduced. It was also found that the stress concentration state on the die pad side, and hence the degree of deformation, differ depending on the positional relationship between the slit of the die pad and the hanging portion.

【0010】第2として、ステイシフトの現象を研究し
た。以下に添付図面を参照してステイシフトの現象を説
明する。図5(a)は半導体装置の斜視図、図5(b)
は図5(a)の半導体装置のY−Y′断面の断面図及び
図5(c)は図5(a)の半導体装置のX−X′断面の
断面図である。図5(b)及び(c)に示すように、半
導体装置ではダイパッド70上に半導体素子72が固定
されており、半導体チップ72は金線74によりインナ
ーリード76に接続され、その周囲はアウターリード7
8を露出するようにして封止用樹脂80で被覆されてい
る。尚、82は、吊り部を示す。このようなパッケージ
構造を生成するに際し、ステイシフトの発生を抑制する
には、図5(c)に示すa寸法とb寸法がa≒bである
ことが必要であり、ステイシフトは、b側にダイパッド
70が移動してa>bになったり、a側にダイパッド7
0が移動してa<bになったりして、aとbとの寸法が
異なると発生する。
Second, the phenomenon of stay shift was studied. The phenomenon of stay shift will be described below with reference to the accompanying drawings. FIG. 5A is a perspective view of the semiconductor device, and FIG.
5A is a cross-sectional view of the semiconductor device of FIG. 5A taken along the line YY ′, and FIG. 5C is a cross-sectional view of the semiconductor device of FIG. 5A taken along the line XX ′. As shown in FIGS. 5B and 5C, in the semiconductor device, the semiconductor element 72 is fixed on the die pad 70, the semiconductor chip 72 is connected to the inner lead 76 by the gold wire 74, and the periphery thereof is the outer lead. 7
8 is exposed and is covered with a sealing resin 80. In addition, 82 shows a hanging part. In order to suppress the occurrence of stay shift when generating such a package structure, it is necessary that the a dimension and the b dimension shown in FIG. 5C be a≈b, and the stay shift is on the b side. The die pad 70 moves to a> b, or the die pad 7 is moved to the a side.
It occurs when 0 moves and becomes a <b, and the dimensions of a and b are different.

【0011】上述の図5において、リードフレームのダ
イパッド70のc寸法、即ちデップレス加工の寸法が許
容加工精度内にあれば、a≒bになり、ステイシフトは
殆ど発生しない。ところが、デップレス加工精度がバラ
ツキ、リードフレームのダイパッド70のc寸法の誤差
が指定公差以上になるとaとbとが異なって、モールド
金型内において上下のバランスが崩れる。それにより、
モールド樹脂を注入した時、注入圧力が隙間の大きい側
に強く働いて隙間の少ない側にリードフレームを押しつ
け、ステイシフトが生じる。
In FIG. 5 described above, if the c dimension of the die pad 70 of the lead frame, that is, the dimension of the deep pressing is within the allowable working accuracy, a≈b, and the stay shift hardly occurs. However, when the precision of the depth processing is varied and the error in the c dimension of the die pad 70 of the lead frame exceeds the specified tolerance, a and b are different and the vertical balance is lost in the molding die. Thereby,
When the molding resin is injected, the injection pressure acts strongly on the side with a large gap and presses the lead frame against the side with a small gap, causing a stay shift.

【0012】以上の知見に基づいて、目的を達成するた
めに、本発明に係る半導体装置は、側周部から延びる吊
り部によってリードフレームに固定されたダイパッドを
有し、ダイパッドにはスリットが長手方向及び幅方向に
配列されている半導体装置において、吊り部が、スリッ
トの長手方向仮想延長部分の領域から離隔したダイパッ
ド側周部から外方に延びていることを特徴としている。
In order to achieve the object based on the above findings, the semiconductor device according to the present invention has a die pad fixed to a lead frame by a hanging portion extending from a side peripheral portion, and a slit is formed in the die pad. In the semiconductor devices arranged in the horizontal direction and the width direction, the hanging portion extends outward from a die pad side peripheral portion that is separated from a region of a virtual extension portion in the longitudinal direction of the slit.

【0013】本発明の改変例では、上述の半導体装置に
おいて、スリットが並列で複数列に配列されており、吊
り部がスリットの長手方向仮想延長部分の領域から離隔
したダイパッド側周部から外方に延びていることを特徴
としてる。
According to a modified example of the present invention, in the above-mentioned semiconductor device, the slits are arranged in parallel in a plurality of rows, and the hanging portion is outward from the die pad side peripheral portion separated from the region of the virtual extension portion in the longitudinal direction of the slit. It is characterized by extending to.

【0014】[0014]

【作用】請求項1及び2の発明では、従来のダイパッド
構造と異なり、図4(b)に示すようにスリット66の
仮想延長部分の領域Bには吊り部70が存在していない
ので、吊り部70に生じた応力はその基端を介して広い
領域(図4(b)のbは図4(a)のaより長い)に分
散される。よって、デップレス加工による応力集中の程
度が従来のものに比べて小さく、従ってその領域に変形
が殆ど発生せず、加工精度が大幅に改善される。
In the inventions of claims 1 and 2, unlike the conventional die pad structure, as shown in FIG. 4 (b), since the suspending portion 70 does not exist in the region B of the virtual extension portion of the slit 66, the suspending portion 70 is suspended. The stress generated in the portion 70 is dispersed through its base end into a wide region (b in FIG. 4B is longer than a in FIG. 4A). Therefore, the degree of stress concentration due to the deep pressing is smaller than that of the conventional one, and therefore, the deformation is hardly generated in the region, and the working accuracy is significantly improved.

【0015】[0015]

【実施例】以下、添付図面を参照し、実施例に基づいて
本発明をより詳細に説明する。図1(a)は本発明に係
る半導体装置の実施例のスリットと吊り部の配置を示す
ダイパッドの平面図、図1(b)は図1(a)に示す半
導体装置要部の斜視図である。本実施例の半導体装置1
0のダイパッド12は、図1(a)に示すように、ダイ
パッド12の長手方向中心線に沿って配置されたスリッ
ト列14、幅方向に2列並列に配列されたスリット列1
6、長手方向端部に対向して設けられた2個の吊り部1
8及び幅方向端縁に対向して設けられた2個の吊り部2
0を備えている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in more detail based on embodiments with reference to the accompanying drawings. FIG. 1A is a plan view of a die pad showing the arrangement of slits and suspension parts of an embodiment of a semiconductor device according to the present invention, and FIG. 1B is a perspective view of the main part of the semiconductor device shown in FIG. 1A. is there. Semiconductor device 1 of the present embodiment
As shown in FIG. 1A, the die pad 12 of 0 has a slit row 14 arranged along the longitudinal center line of the die pad 12, and two slit rows 1 arranged in parallel in the width direction.
6, two hanging portions 1 provided to face the end in the longitudinal direction
8 and two hanging portions 2 provided so as to face the widthwise end edges.
It has 0.

【0016】長手方向のスリット列14は、長手方向に
一列に配置された3個のスリット14A、14B及び1
4Cからなり、幅方向のスリット列16は、2個づつ2
列並列に配置されたスリット16A及び16Bと、16
C及び16Dとからなっていて、それぞれの幅方向スリ
ット列は、長手方向スリット14の丁度中間にあるよう
に配置されている。
The slit array 14 in the longitudinal direction includes three slits 14A, 14B and 1 arranged in a line in the longitudinal direction.
The slit rows 16 in the width direction are made of 4C, and each two slit rows 16 are 2
16 slits 16A and 16B arranged in parallel with each other,
C and 16D, and each width direction slit row is arranged so as to be in the middle of the longitudinal direction slit 14.

【0017】ダイパッド12の長手方向端部から外方に
延びる長手方向の吊り部18は、その基端22が二股に
形成されていて、それによって長手方向スリット14の
仮想延長部分のダイパッド領域15から離隔するよう形
成されている。一方、ダイパッド12の幅方向側縁から
外方に延びる幅方向の吊り部20は、2列並列に配置さ
れた幅方向のスリット16列の丁度中間に位置する。換
言すれば、スリット14の長手方向仮想延長部分のダイ
パッド領域22から離隔した端縁から外方に延出してい
る。尚、72はインナーリードである。
The longitudinal suspension 18 extending outwardly from the longitudinal end of the die pad 12 is bifurcated at its proximal end 22 so that it extends from the die pad area 15 of the virtual extension of the longitudinal slit 14. It is formed to be separated. On the other hand, the width-direction suspending portion 20 extending outward from the width-direction side edge of the die pad 12 is located just in the middle of the width-direction slits 16 arranged in two rows. In other words, the slit 14 extends outward from the edge of the slit 14 that is virtually extended in the longitudinal direction and is separated from the die pad region 22. Reference numeral 72 is an inner lead.

【0018】以上の構成により、従来の半導体装置に比
べて、幅方向の吊り部20の基端は幅方向のスリット1
6から遙に離隔した位置にあり、また長手方向の吊り部
18の基端も長手方向のスリット14から離隔してい
る。これによって、以下にその理由を説明するように、
リードフレームのデップレス加工の必要な精度が維持さ
れ、モールド成形時のステイシフトが抑制される。即
ち、図4(b)を参照し、図4(a)に示す従来のダイ
パッド構造に比較して説明すると、本実施例では、図4
(b)に示すようにスリット66の仮想延長部分の領域
Bには吊り部70が存在していないので、吊り部70に
生じた応力はその基端を介して広い領域(図4(b)の
bは図4(a)のaより長い)に分散される。よって、
デップレス加工による応力集中の程度が従来のものに比
べて小さく、従って変形が殆ど発生せず、加工精度が大
幅に改善される。
With the above configuration, the base end of the hanging portion 20 in the width direction has the slit 1 in the width direction as compared with the conventional semiconductor device.
6, and the base end of the suspending portion 18 in the longitudinal direction is also separated from the slit 14 in the longitudinal direction. As a result, as explained below,
The required precision of the lead frame deep pressing is maintained, and the stay shift during molding is suppressed. That is, referring to FIG. 4B, the description will be made in comparison with the conventional die pad structure shown in FIG. 4A.
As shown in (b), since the suspending portion 70 does not exist in the region B of the virtual extension portion of the slit 66, the stress generated in the suspending portion 70 has a wide region via its base end (FIG. 4 (b)). 4b is longer than a in FIG. 4A). Therefore,
The degree of stress concentration due to the deep-press processing is smaller than that of the conventional one, so that there is almost no deformation and the processing accuracy is greatly improved.

【0019】図2(a)、(b)及び(c)並びに図3
(d)、(e)及び(f)は、図1の改変例であって、
図7に示した従来のスリットと吊り部との位置関係とは
異なる種々のスリットと吊り部との配置を示す。いずれ
の配置においても、吊り部は、スリット列の長手方向仮
想延長部分のダイパッド領域から離隔したダイパッド側
縁から延出している。
2 (a), 2 (b) and 2 (c) and FIG.
(D), (e) and (f) are modified examples of FIG.
The arrangement of various slits and suspension portions different from the conventional positional relationship between slits and suspension portions shown in FIG. 7 is shown. In either arrangement, the hanging portion extends from the side edge of the die pad that is separated from the die pad region of the virtual extension in the longitudinal direction of the slit row.

【0020】[0020]

【発明の効果】請求項1及び2の発明によれば、吊り部
が、スリットの長手方向仮想延長部分の領域から離隔し
たダイパッド側周部から外方に延びていることにより、
デップレス加工時に発生する応力が広い領域に分散して
集中することなく、また吊り部基端近傍のダイパッド領
域が変形しない。よって、大型半導体装置であっても、
必要なデップレス加工精度を維持することが可能にな
り、かつ樹脂封止時にもステイシフトが発生しない。本
発明に係る半導体装置を製造することにより、大型半導
体パッケージの歩留りが向上する。
According to the first and second aspects of the present invention, the hanging portion extends outward from the die pad side peripheral portion which is separated from the region of the virtual extension portion in the longitudinal direction of the slit.
The stress generated during the deep pressing is not dispersed and concentrated in a wide area, and the die pad area near the base end of the hanging portion is not deformed. Therefore, even for large semiconductor devices,
It is possible to maintain the required precision of the depth processing, and the stay shift does not occur even during resin sealing. By manufacturing the semiconductor device according to the present invention, the yield of large semiconductor packages is improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】図1(a)は本発明に係る半導体装置の実施例
のスリットと吊り部の配置を示すダイパッドの平面図、
図1(b)は図1(a)に示す半導体装置要部の斜視図
である。
FIG. 1A is a plan view of a die pad showing an arrangement of slits and suspensions of an embodiment of a semiconductor device according to the present invention;
FIG. 1B is a perspective view of the main part of the semiconductor device shown in FIG.

【図2】図2(a)、(b)及び(c)は、それぞれ図
1の半導体装置の改変例のスリットと吊り部の配置を示
す。
2 (a), (b) and (c) show arrangements of slits and suspensions in a modified example of the semiconductor device of FIG. 1, respectively.

【図3】図3(d)、(e)及び(f)は、それぞれ図
1の半導体装置の改変例のスリットと吊り部の配置を示
す。
3 (d), (e) and (f) show the arrangement of slits and suspensions in a modification of the semiconductor device of FIG. 1, respectively.

【図4】図4(a)、(b)及び(c)は、それぞれ樹
脂封止型半導体装置の斜視図及び断面図を示す。
FIG. 4A, FIG. 4B and FIG. 4C are a perspective view and a sectional view of a resin-sealed semiconductor device, respectively.

【図5】図5(a)及び(b)はデップレス加工による
応力集中を説明する図である。
5 (a) and 5 (b) are diagrams for explaining stress concentration due to deep pressing.

【図6】図6(a)は従来の半導体装置ののスリットと
吊り部の配置を示すダイパッドの平面図、図6(b)は
図6(a)に示す半導体装置要部の斜視図である。
6A is a plan view of a die pad showing the arrangement of a slit and a hanging portion of a conventional semiconductor device, and FIG. 6B is a perspective view of a main part of the semiconductor device shown in FIG. 6A. is there.

【図7】図7(a)、(b)及び(c)は、それぞれ従
来の半導体装置のスリットと吊り部の別の配置を示す。
7 (a), (b) and (c) show another arrangement of slits and suspensions of a conventional semiconductor device, respectively.

【符号の説明】[Explanation of symbols]

10 本発明に係る半導体装置 12 ダイパッド 14 ダイパッドの長手方向中心線に沿って配置された
スリット列 16 ダイパッドの幅方向に2列並列に配列されたスリ
ット列 18 ダイパッドの長手方向端部に対向して設けられた
吊り部 20 ダイパッドの幅方向端縁に対向して設けられた吊
り部
10 Semiconductor device according to the present invention 12 Die pad 14 Slit row arranged along the longitudinal centerline of the die pad 16 Slit row arranged in two rows in parallel in the width direction of the die pad 18 Opposed to the longitudinal end of the die pad Suspended part provided 20 Suspended part provided so as to face the widthwise end edge of the die pad

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 側周部から延びる吊り部によってリード
フレームに固定されたダイパッドを有し、ダイパッドに
はスリットが長手方向及び幅方向に配列されている半導
体装置において、 前記吊り部が、前記スリットの長手方向仮想延長部分の
領域から離隔したダイパッド側周部から外方に延びてい
ることを特徴とする半導体装置。
1. A semiconductor device having a die pad fixed to a lead frame by a suspending portion extending from a side peripheral portion, wherein slits are arranged in a longitudinal direction and a width direction on the die pad, wherein the suspending portion is the slit. A semiconductor device, which extends outward from a die pad side peripheral portion separated from a region of a virtual extension portion in the longitudinal direction.
【請求項2】 前記スリットが並列で複数列に配列され
ており、吊り部が前記スリットの長手方向仮想延長部分
の領域から離隔したダイパッド側周部から外方に延びて
いることを特徴とする請求項1記載の半導体装置。
2. The slits are arranged in parallel in a plurality of rows, and the suspending portion extends outward from a die pad side peripheral portion which is separated from a region of a virtual extension portion in the longitudinal direction of the slit. The semiconductor device according to claim 1.
JP5237394A 1993-08-30 1993-08-30 Semiconductor device Pending JPH0766355A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5237394A JPH0766355A (en) 1993-08-30 1993-08-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5237394A JPH0766355A (en) 1993-08-30 1993-08-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0766355A true JPH0766355A (en) 1995-03-10

Family

ID=17014747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5237394A Pending JPH0766355A (en) 1993-08-30 1993-08-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0766355A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010111767A (en) * 2000-06-13 2001-12-20 마이클 디. 오브라이언 Leadframe for manufacturing semiconductor package
US6953987B2 (en) 2002-07-31 2005-10-11 Denso Corporation Composite integrated circuit device having restricted heat conduction

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010111767A (en) * 2000-06-13 2001-12-20 마이클 디. 오브라이언 Leadframe for manufacturing semiconductor package
US6953987B2 (en) 2002-07-31 2005-10-11 Denso Corporation Composite integrated circuit device having restricted heat conduction

Similar Documents

Publication Publication Date Title
US6246110B1 (en) Downset lead frame for semiconductor packages
WO2004093128A3 (en) Lead frame structure with aperture or groove for flip chip in a leaded molded package
KR970008520A (en) Semiconductor device assembled with semiconductor chip and semiconductor chip and method of manufacturing the same
US6639306B2 (en) Semiconductor package having a die pad with downward-extended tabs
KR20030052502A (en) Lead-frame strip and process for manufacturing semiconductor packages using the same
US20050017332A1 (en) Asymmetric partially-etched leads for finer pitch semiconductor chip package
JPH0766355A (en) Semiconductor device
US5920113A (en) Leadframe structure having moveable sub-frame
US5914528A (en) Thermally-enhanced lead frame with reduced thermal gap
US6897549B2 (en) Frame for semiconductor package
JPH09139455A (en) Lead frame and semiconductor device using the lead frame
JPH0233961A (en) Lead frame
US5283466A (en) Lead frame for semiconductor device of the resin encapsulation type
JPS60161646A (en) Lead frame for semiconductor device
JP4455166B2 (en) Lead frame
JPH0661289A (en) Semiconductor package and semiconductor module using same
JP3305981B2 (en) Semiconductor device
KR0167292B1 (en) Semiconductor multipin package and method of making the same
JPH0529525A (en) Semiconductor package
JPH03296253A (en) Lead frame
JPH1154685A (en) Semiconductor device and lead frame used therein
KR100819794B1 (en) Lead frame and semiconductor package manufacturing method using the same
JPS60234335A (en) Semiconductor device
JPH06196609A (en) Lead frame and semiconductor device using the same
KR0137068B1 (en) Lead frame

Legal Events

Date Code Title Description
FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 6

Free format text: PAYMENT UNTIL: 20071221

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 7

Free format text: PAYMENT UNTIL: 20081221

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081221

Year of fee payment: 7

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091221

Year of fee payment: 8

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101221

Year of fee payment: 9

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101221

Year of fee payment: 9

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111221

Year of fee payment: 10

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111221

Year of fee payment: 10

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121221

Year of fee payment: 11

LAPS Cancellation because of no payment of annual fees