JPH0764804A - Interrupt control circuit - Google Patents

Abstract

PURPOSE:To provide an interrupt control circuit which reduces the number of signal lines to raise the mounting density by giving plural meanings to one signal line to multiplex them. CONSTITUTION:Interrupt output means 1, 2, 3, and 4 which output plural interrupt signals onto the same interrupt signal line 13 on a bus in accordance with prescribed timings, a taking-in timing generating means 5 which generates timings for taking-in of plural interrupt signals on the interrupt signal line 13, and plural latch means 7 which separate, take in, and store plural interrupt signals on the interrupt signal line 13 in accordance with timings generated by the taking-in timing generating means 5 are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt control circuit,
In particular, wired OR (Wir) used in buses and logic circuits used in microcomputers and computer systems.
ed-OR) connected interrupt control circuit.

[0002]

2. Description of the Related Art In a conventional interrupt control circuit constituted by a wired-OR connection, for example, only one kind of interrupt signal output on the same interrupt signal line on a bus can be connected. For example, an interrupt line of a bus used in an SBC (single board computer system) is wired from a plurality of boards that configure the system.
An interrupt signal is output by OR connection. At this time, one signal line was required for interrupt level 1. Therefore, when there are a plurality of interrupt levels, as many signal lines as the interrupt levels are required.

[0003]

As described above, in the conventional interrupt control circuit, only one meaning can be assigned to one interrupt signal line, and the mounting area is increased due to the increase of the signal line at the time of system design. There was a big problem in mounting such as pressure.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to increase the packaging density by reducing the number of signal lines by giving multiple meanings to one signal line and multiplexing them. It is an object to provide an interrupt control circuit.

[0005]

According to the present invention, there are provided an interrupt output means for outputting a plurality of interrupt signals on the same interrupt signal line on a bus at a predetermined timing, and a plurality of interrupt signals on the interrupt signal line. The capture timing generating means for generating the capture timing and the plurality of latch means for separately capturing and storing a plurality of interrupt signals on the interrupt signal line according to the timing generated by the capture timing generating means are provided. It is a thing.

[0006]

According to the present invention, a plurality of interrupt signals are output on the same interrupt signal line on the bus at a predetermined timing. Then, the plurality of interrupt signals on the interrupt signal line are fetched into the latch means at a predetermined timing by the fetch timing generating means. The latch means is provided with a timing generating means for fetching the interrupt signal, and the plurality of interrupt signals on the interrupt signal line are separated according to the timing generated by the fetch timing generating means, and the plurality of corresponding interrupt signals are respectively separated. It is taken in by the latch means. As a result, even if a plurality of signals having different meanings are output from the wired-OR, the signals can be output in a time-sharing manner and can be taken out by the meaning by latching each output. Therefore, one Wired-OR
Since signals having different meanings can be output in a time-division manner in connection, signals can be multiplexed.

[0007]

FIG. 1 shows a circuit diagram of an embodiment of the present invention.

In the present embodiment, the interrupt control circuit is divided into boards 1 to 3, and each board is divided into one board.
It is indicated by 0, 20, and 30. The board 1 has an interrupt signal line 1 according to the timing clock of the system clock 12.
Timing generating circuit 5 for generating a timing for fetching the interrupt signal on 3 at a predetermined timing, a bus buffer 6 for inputting the interrupt signal, and an interrupt signal fetched from the bus buffer 6 for the timing generating circuit 5. A latch circuit 7a and a latch circuit 7b for separately capturing according to the timing are mounted.

The boards 2 and 3 are prepared according to the number of interrupt signals. In the case of this embodiment, 2 boards are provided.
Two interrupt signals are generated. Each board has a frequency divider circuit 1 and a frequency divider circuit 3 for dividing the system clock 12 to generate an interrupt output enable signal for each board. The interrupt signal is output on the interrupt signal line 13 via the three-state buffer 2 and the three-state buffer 4, respectively. In this embodiment, the interrupt signals from the boards 2 and 3 are wired-OR.
It is connected to the interrupt signal line 13 in a connected state.

FIG. 2 is a timing chart showing the operation of FIG. 1, and shows the signal waveforms of the respective parts in FIG. a) and b) are enable signals for the three-state buffer 2 and the three-state buffer 4, and interrupt signals c) and d) for the boards 2 and 3 are on the bus when the buffer enable signals a) and b) are High Level. It is output to the interrupt signal line 13.

The interrupt signal e) output on the interrupt signal line 13 passes through the bus buffer 6 on the board 1 and is separated into a latch circuit 7a and a latch circuit 7b in accordance with the timing generated by the timing generation circuit 5 and latched. To be done. The timing generation circuit 5 creates interrupt signal capture clocks f) and g) that determine the timing for capturing the interrupt signal of each board based on the system clock and the interrupt signal, and inputs them to the latch circuits 7a and 7b to generate an interrupt. Hold the signal for each board. At this time, the interrupt of the board 2 becomes the signal h) and the interrupt of the board 3 becomes the signal i). In this way, one Wired-O
It is possible to give two kinds of meanings to the R signal, that is, the interrupt of the board 2 and the interrupt of the board 3.

FIG. 3 is a circuit diagram of another embodiment of the present invention, showing an embodiment in which the number of boards for generating interrupts is increased. The circuit configuration of the embodiment shown in FIG. It is similar to the case of. In the embodiment shown in FIG. 3, a board 40 and a board 50 are added and quadruple multiplexing is performed. At this time, four latch circuits are required to be mounted on the board 1, and these are indicated by the latch circuits 7a to 7d. Further, the frequency divider circuit 8, the frequency divider circuit 10, the three-state buffer 9, and the three-state buffer 1 are provided on each board.
1 is required. Such a quadrupled Wired-
In the case of OR connection, the timings of the interrupt output three-state buffers 2, 4, 9, 11 and the interrupt fetch latch 6 are changed.

FIG. 4 is a timing chart showing the operation of FIG. 3 and shows the timing when the board 2 and the board 4 generate an interrupt. As is apparent from the figure, an interrupt signal is output to the interrupt signal line 13 on the bus only when the respective buffers are enabled and is input to the latch group 7 of the board 1. Then, each board interrupt clock j), k) generated by the timing generation circuit 5,
l) and m) are input to the respective latch circuits 7a, 7b, 7c and 7d. At this time, no latch clock is generated for a board that has not generated an interrupt.

[0014]

As described above in detail with reference to the embodiments, according to the present invention, a signal having a plurality of meanings can be multiplexed on one Wired-OR connection line.
It is possible to realize an interrupt control circuit which can reduce the number of wirings of the system and enable higher density mounting.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a timing diagram showing the operation of FIG.

FIG. 3 is a circuit diagram of another embodiment of the present invention.

FIG. 4 is a timing diagram showing the operation of FIG.

[Explanation of symbols]

 1 divider circuit 2 three-state buffer 3 divider circuit 4 three-state buffer 5 timing generator circuit 6 bus buffer 7a, 7b, 7c, 7d latch circuit 8 divider circuit 9 three-state buffer 10 divider circuit 11 three-state buffer 12 system Clock 13 Interrupt signal line

Claims (1)

[Claims] 1. An interrupt output means for outputting a plurality of interrupt signals on the same interrupt signal line on a bus in accordance with a predetermined timing, and a fetch timing for generating timing for fetching a plurality of interrupt signals on the interrupt signal line. An interrupt control circuit comprising: a generating means; and a plurality of latch means for separately capturing and storing a plurality of interrupt signals on the interrupt signal line according to the timing generated by the fetch timing generating means. .