JPH0757068A - Semiconductor memory card - Google Patents

Abstract

PURPOSE:To provide the inexpensive card which is both nonvolatile and fast in access. CONSTITUTION:An inexpensive dummy SRAM 2 and a ROM 3 which is a kind of nonvolatile memory are mounted. A host device accesses the dummy SRAM 2 and ROM 3 through a decoder circuit 8. Through this decoder circuit 8, the dummy SRAM 2 or ROM 3 can optionally be accessed according to an address as an object of access. In this case, the host device uses an area of addresses assigned to the dummy SRAM 2 as a work memory area and accesses this area at a high speed to increase a data processing speed. Further, an area assigned to the ROM 3 is used as an area where, for example, a program, an font, etc., are stored to guarantee the nonvolatileness of the storage contents.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory card used as a memory by being connected to an electronic device such as a computer.

[0002]

2. Description of the Related Art Conventionally, along with the progress of semiconductor integrated circuit technology, data storage means for electronic equipment such as computers and I
Semiconductor memory cards used as D cards and the like are becoming popular. Regarding such a semiconductor memory card, for example, the length is 85.6 mm, the width is 54.0 mm, and the thickness is 3.3.
A guideline ("IC memory card guideline", Japan Electronics Industry Promotion Association) to be formed in a small size of mm has been proposed. There are also proposals for specifications thicker than 3.3 mm. Based on such guidelines, semiconductor memory cards of various specifications have been proposed.

A semiconductor memory card embodied is an SRAM card having an SRAM mounted thereon, a mask ROM
There are a mask ROM card equipped with a memory card, an EPROM card equipped with an EPROM, an OTPROM card equipped with an OTP (one-time programmable) ROM, and a flash memory card equipped with a flash memory.
Each of these semiconductor memory cards has advantages and disadvantages.

For example, the mask ROM card has the advantage that the price per bit is relatively low, but it is read-only and cannot be written. Further, the SRAM card has an advantage that it can be arbitrarily written, but has a high price per bit. The EPROM card is writable and the price per bit is lower than that of the SRAM card, but it has a drawback that the memory cell portion must be irradiated with ultraviolet rays to erase the previous data before rewriting, and Writing (called programming) requires a high voltage. The OTPROM card cannot be erased by ultraviolet rays, and once written, it cannot be rewritten. The flash memory card has the advantage that the price per bit is low and rewriting is possible, but since it is a batch erasing method, even if only one bit is rewritten, all bits of one flash memory are erased and rewritten. I have to Therefore, rewriting takes time and effort. Further, the contents written in the SRAM are volatilized when the power is turned off. Therefore, if it is necessary to keep the data even if the power supply from the system side is cut off after being taken out from the host system, SR
A battery must be installed in the AM card.

On the other hand, a DRAM card equipped with a DRAM has a relatively low price per bit and has an advantage of being able to read and write arbitrarily. However, as disclosed in Japanese Utility Model Laid-Open No. 3-116459, an address is designated. RA
Two timing signals, an S (row address strobe) signal and a CAS (column address strobe) signal, are required. Therefore, the access procedure is complicated and the access time is long. Further, in the DRAM, even if the power supply voltage is applied, the contents of the memory will be lost unless refreshed frequently. Also,
The above guidelines standardize the terminal arrangements and terminal shapes of the various types of semiconductor memory cards described above to be common. Therefore, as far as the physical interface is concerned, various kinds of semiconductor memory cards can be inserted and used in one slot for the card of the host device.

Since each memory card is used in a different manner depending on the mounted memory device or the specific condition setting within the memory card, it is often necessary to inform the host device of the attributes of the card. That is what is called card attribute information. The above-mentioned guidelines describe in detail the rules regarding card attribute information. Various attributes can be described in the card attribute information, and these card attribute information are described for each item unit called a tuple. The card attribute information is stored in the attribute memory and is distinguished from the common memory. The interface signals of the memory card standardized in the above-mentioned documents are 16-bit data bus, address and card enable signals CE1 and CE.
2, output enable signal OE, write enable signal W
E, and the attribute memory space select signal REG and the like. When REG is at H level, the common memory is accessed, while when REG is at L level, the attribute memory is accessed.

[0007]

By the way, the semiconductor memory card as described above may be used as a data storage means for programs, fonts, and the like. In such a case, the semiconductor memory card must retain information even when the power supply voltage is not applied. That is, it must be a non-volatile semiconductor memory card. In addition, the semiconductor memory card as described above,
It may be used as a working memory of a higher level system. In such a case, the semiconductor memory card must be able to write and read frequently and at high speed during the processing operation inserted in the host system.

However, there is currently no inexpensive memory device that satisfies these two requirements at the same time. JP-A-61-160185 and JP-A-1-160185
As disclosed in Japanese Unexamined Patent Publication No. 128110, an SRAM card that has a built-in battery and is configured to back up when the power supply from the host system is cut off is non-volatile in the memory content and high in access speed. However, there is a problem that the price per bit is high.

In addition, in the memory card having the above-mentioned card attribute information, a dedicated attribute memory for storing the card attribute information is required in addition to the common memory. Therefore, depending on the nature of the card attribute information. There was a problem that the dedicated attribute memory had to be changed. For example, if the SRAM card has a fixed card attribute, SRA which is a common memory
In addition to M, ROM is required as an attribute memory. Further, in order to realize a ROM card having a changeable card attribute, it is necessary to have an EEPROM as an attribute memory in addition to the ROM which is a common memory. The present invention has been made in order to solve the above-mentioned problems, and is an inexpensive semiconductor memory card capable of changing the storage location of card attribute information while simultaneously satisfying the two requirements of nonvolatility and high-speed access. It is intended to provide.

[0010]

A semiconductor memory card according to a first aspect of the present invention holds one or more pseudo SRAMs that can be accessed by an access method similar to that of SRAMs, and retains stored contents even if power is not supplied. And a decoder circuit that outputs an enable signal that enables access to either the pseudo SRAM or the nonvolatile memory according to an address output from the host device. is there.

The semiconductor memory card of the second invention comprises one or more common memories for storing data, one or more attribute memories for storing attribute information indicating the type of the common memory, and the attribute. A data bus switching circuit for switching a data bus connected to the memory and the common memory, a chip select circuit for selecting one of the attribute memory and the common memory, and a setting on a board for setting a selection state of the chip select circuit. It is characterized in that it is composed of parts.

[0012]

In the semiconductor memory card of the first invention,
An inexpensive pseudo SRAM and a non-volatile memory are mounted. The host device accesses these memories via the decoder circuit in this semiconductor memory card. As a result, the pseudo SR is generated according to the address to be accessed.
The AM or non-volatile memory can be accessed.
The host device uses the area of the address assigned to the pseudo SRAM as a working memory area and the area assigned to the non-volatile memory as an area for storing programs, font fonts, and the like.

In the semiconductor memory card of the second invention, the memory chip selected by the chip select circuit is changed by changing the setting of the on-board setting unit, and the attribute information to be stored in the attribute memory is stored in the common memory. can do. Thereby, for example, a semiconductor memory card in which the common memory is a ROM can be used as follows. That is, by storing the attribute information in the common memory including the ROM, a semiconductor memory card that does not require the attribute memory can be obtained.
Further, by storing the attribute information in the attribute memory composed of the EEPROM, a semiconductor memory card having a changeable card attribute can be obtained.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. (First Invention) FIG. 1 shows a first embodiment of a semiconductor memory card of the first invention. In FIG. 1, the lower address 1 has 19 bits, and each bit is A18 to A0.
This lower address 1 is input to the address input terminal of the pseudo SRAM 2 and the address input terminal of the ROM 3. The pseudo SRAM 2 is a RAM that has the same configuration as the DRAM but can be accessed similarly to the SRAM. That is, it is not necessary to take the access procedure by the RAS signal and the CAS signal as disclosed in Japanese Utility Model Laid-Open No. 3-116459, and the address can be input and accessed at one timing. The ROM 3 is a read-only semiconductor memory, as is well known.

The data bus 4 has 8 bits, and each bit is D7 to D0. This data bus 4 is a pseudo S
It is connected to the data input / output terminal of the RAM 2 and the data output terminal of the ROM 3. The output enable signal 5 is a signal for permitting the data bus 4 to output the pseudo SRAM 2 and the ROM 3. That is, the output enable signal 5 is connected to the output enable terminal of the pseudo SRAM 2 and the output enable terminal of the ROM 3. The write enable signal 6 is a signal for controlling whether or not writing is performed in the pseudo SRAM 2, and the pseudo SRAM 2
2 is input to the write enable terminal.

The card enable signal 7 is a signal for enabling the operation of the memory card, and the decoder circuit 8
Is input to the first input terminal of. Upper address A1
9 is input to the second input terminal of the decoder circuit 8. The decoder circuit 8 is the simplest decoder circuit, and when A19 is at the L level, permits the write or read operation to the pseudo SRAM 2 and, conversely, A19.
Is at the H level, it operates to permit the read operation to the ROM 3. That is, the first output signal 10 of the decoder circuit 8 is connected to the chip enable terminal of the pseudo SRAM 2, while the second output signal 11 of the decoder circuit 8 is input to the chip enable terminal of the ROM 3.

FIG. 2 is a truth table for explaining the operation of the decoder circuit 8. Here, the case where each signal is L active is illustrated. First, when the card enable signal 7 is at H level, regardless of the higher address A19,
Since the output signals 10 and 11 are at the H level, the pseudo SR
Both AM2 and ROM3 are inactive, and neither writing nor reading is possible. Next, when the card enable signal 7 is at L level, only one memory device selected by the upper address A19 becomes active.

FIG. 3 is a memory map diagram for supplementarily explaining the operation of FIG. In FIG. 1, as a whole, a 1-Mbyte memory space can be accessed with a 20-bit address of A19 to A0. If this address is expressed in hexadecimal, it is "00000h" to "FFFFFh". Of these, A19 is in the L level range from "00000h" to "7FFFF
It corresponds to 512 Kbytes of h ". In the embodiment of FIG.
A pseudo SRAM is assigned to this range as shown in FIG. The range of A19 H level is from "80000h" to "FFFF
It corresponds to 512 Kbytes of Fh ”. In the embodiment shown in FIG.
The ROM is assigned to this range as shown in FIG. When a memory card as shown in FIG. 1 is accessed from the host system, fixed information such as programs, dictionaries, and character fonts is stored in the ROM 3 and is simulated in an area such as a working memory that requires frequent and high-speed reading and writing. It is configured to allocate SRAM.

Next, referring to FIG. 2 described above, the pseudo SRAM is used.
The operation and function of will be described. The pseudo SRAM has a refresh mode for automatically refreshing.
As shown in FIG. 2, when the chip enable terminal CE is set to H level and the output enable terminal OE is set to L level, the refresh operation is executed. Chip enable terminal CE
When the output enable terminal OE is at the L level, the memory read operation is performed, and when the write enable terminal WE is at the L level, the memory write operation is performed.

The pseudo SRAM can be read and written at a high speed at the same simple timing as the SRAM during normal memory access. In addition, the chip size per unit memory capacity is a fraction of that of SRAM, and the price is about 1/4 that of SRAM. Alternatively, when compared with a chip size that can be realized on an industrial level as a reference, a memory capacity of about 4 times can be realized. As described above, in the memory card as illustrated in FIG. 1, if fixed information such as programs, dictionaries, and character fonts is stored in the ROM 3 and the pseudo SRAM 2 is assigned to the working memory area, the fixed information is fixed. While the temporary information is held in a nonvolatile manner, a temporary storage information area that needs to be read and written frequently and at high speed is also secured in the memory card.

FIG. 4 shows a second embodiment according to the first invention. In FIG. 4, the lower address 21 has 19 bits, and each bit is A18 to A0 as in FIG. The lower address 21 is input to the address input terminal of the pseudo SRAM 22 and the address input terminals of the two ROMs 23-1 and 23-2. The data bus 24 has 8 bits, and each bit is D7 to D0. The data bus 24 is connected to the data input / output terminal of the pseudo SRAM 22 and 2
It is connected to the data output terminals of the individual ROMs 23-1 and 23-2.

The output enable signal OE is applied to the data bus 2
4, the output of the pseudo SRAM 22 and the two ROMs 2
This is a signal for permitting the outputs of 3-1 and 23-2.
That is, the output enable signal OE is output to the output enable terminal of the pseudo SRAM 22 and the two ROMs 23-1, 23-.
2 is connected to the output enable terminal OE. The write enable signal WE is a signal for controlling whether to write in the pseudo SRAM 22, and the pseudo SRA is used.
It is input to the write enable terminal WE of M22.
The card enable signal CE is a signal for enabling the operation of the memory card, and is input to the first input terminal of the decoder circuit 28.

The upper addresses A19 and A20 are input to the second and third input terminals of the decoder circuit 28.
The decoder circuit 28 has a slightly more complicated configuration than the decoder circuit 8 in the first embodiment, and has A20, A1.
When both 9 are L level, write or read operation to the pseudo SRAM 22 is permitted. When A20 is L level and A19 is H level, read operation to ROM 23-1 is permitted, A20 is H level and A19 is L level. At the time of, it operates to permit the read operation to the ROM 23-2.

That is, the first output signal 30 of the decoder circuit 28 is the chip enable terminal CE of the pseudo SRAM 22.
The second output signal 31-1 of the decoder circuit 28 is connected to the chip enable terminal CE of the ROM 23-1.
To the third output signal 31- of the decoder circuit 28.
2 is input to the chip enable terminal CE of the ROM 23-2. As a result, the decoder circuit 28 decodes the 2-bit addresses A19 and A20.

FIG. 5 is a truth table for explaining the operation of the decoder circuit 28. Here again, the case where each signal is L active is illustrated. First, the card enable signal C
When E is at H level, upper addresses A20 and A19
Output signals 30, 31-1 and 31-2,
Since it becomes the H level, the pseudo SRAM 22 and the ROM 23
-1, 23-2 are both inactive, and neither writing nor reading is possible. Next, when the card enable signal CE is at L level, the upper addresses A20, A
Only one memory device selected by 19 is active.

FIG. 6 is a memory map diagram for supplementarily explaining the operation of FIG. In FIG. 4, as shown in FIG. 6, as a whole, a 21-Mbit address of A20 to A0 can access a memory space of 1.5 Mbytes.
Expressing this address in hexadecimal, "000000h" ~
It is "17FFFFh". Of these, the range where both A20 and A19 are at L level is 5 from "000000h" to "07FFFFh".
It corresponds to 12K bytes. In the embodiment of FIG. 4, the pseudo SRAM is assigned to this range as shown in FIG. A
The range of 20 for L level and A19 for H level is "0800".
This corresponds to 512 Kbytes of 00h "to" 0FFFFFh ". In the embodiment of Fig. 4, the ROM 23-1 is assigned to this range as shown in Fig. 6. A20 is H level, A
The range of 19 for L level is "100000h" to "17FFFFh"
Corresponding to 512 Kbytes. In the embodiment of FIG. 4, FIG.
The ROM 23-2 is assigned to this range as shown in FIG.

According to the second embodiment, the number of each of a plurality of types of memory devices mounted on the memory card depends on the required total memory capacity.
It can be understood that the case where the number is plural is also allowed. In the second embodiment, only one pseudo SRAM is used for RO
Although only an example is given for the case where M is two, it can be easily developed even when the number of pseudo SRAMs is increased or the number of those is three or more. Of course.

FIG. 7 is a circuit diagram of the third embodiment according to the first invention. In FIG. 7, the lower address 41 is 19
There are bits, and each bit is set to A18 to A0 as in FIG. The lower address 41 is input to the address input terminal of the pseudo SRAM 42 and the address input terminal of the ROM 43. The data bus 44 has 8 bits, and each bit is D7 to D0. The data bus 44 is connected to the data input / output terminal of the pseudo SRAM 42 and the data output terminal of the ROM 43.

The output enable signal OE is supplied to the data bus 4
4 is a signal for permitting the output of the pseudo SRAM 42 and the output of the ROM 43. That is, the output enable signal OE is connected to the output enable terminal of the pseudo SRAM 42 and the output enable terminal of the ROM 43.
The write enable signal WE is a signal for controlling whether or not writing is performed in the pseudo SRAM 42, and is input to the write enable terminal of the pseudo SRAM 42. The card enable signal CE is a signal for enabling the operation of the memory card, and is input to the first input terminal of the decoder circuit 48.

The upper addresses A19 and A20 are input to the second and third input terminals of the decoder circuit 48.
The decoder circuit 48 has a slightly more complicated configuration than the decoder circuit 8 in the first embodiment, and has A20 and A1.
When both 9 are at the L level, the write or read operation to the pseudo SRAM 42 is permitted, and when the A20 is at the H level and A19 is at the L level, or when A20 is at the H level and A19 is at the H level, the read operation to the ROM 43 is permitted. Works like. That is, the decoder circuit 4
8 is connected to the chip enable terminal of the pseudo SRAM 42, while the second output signal 51 of the decoder circuit 48 is input to the chip enable terminal of the ROM 43. As a result, the decoder circuit 48
Decodes the 2-bit address signals A19 and A20.

FIG. 8 is a truth table for explaining the operation of the decoder circuit 48. Here again, the case where each signal is L active is illustrated. First, the card enable signal C
When E is at H level, upper addresses A20 and A19
Regardless of the above, since the output signals 50 and 51 are at the H level, both the pseudo SRAM 42 and the ROM 43 are inactive, and neither writing nor reading is possible. Next, when the card enable signal CE is at L level, only the memory device selected by the upper address A20, A19 becomes active.

FIG. 9 is a memory map diagram for supplementarily explaining the operation of FIG. In FIG. 7, as a whole, a 2 Mbyte memory space can be accessed by 21-bit addresses A20 to A0. However, of these, 5
12K bytes are blank. Of these, A20 and A19
, The L level range is "0000" when expressed in hexadecimal.
Corresponding to 512 Kbytes of 00h "to" 07FFFFh ". In the embodiment of Fig. 7, the pseudo SRAM is assigned to this range as shown in Fig. 9. A20 is at the L level and A19 is at the H level. 51 from 080000h ”to“ 0FFFFFh ”
It corresponds to 2K bytes. In the embodiment shown in FIG. 7, both the pseudo SRAM and the ROM are inactive blank areas as shown in FIG. The range where A20 is at H level and A19 is at L or H level corresponds to 1 Mbyte of "100000h" to "1FFFFFh". In the embodiment shown in FIG. 7, as shown in FIG.
The OM is assigned to this range. Pseudo SRAM mounted on a semiconductor memory card according to the third embodiment
The present invention can be applied even when the memory capacities of the ROM and ROM are different.

FIG. 10 shows a fourth embodiment according to the first invention. In FIG. 10, the same parts as those in FIG. 1 are designated by the same reference numerals, and duplicated description will be omitted. In FIG. 10, an EPROM 63 is provided. EPROM 63 has a normal power supply voltage VCC
In addition to (usually 5.0 V), a high voltage VPP is applied for programming. In FIG. 10, the VPP voltage supply terminal 72 is connected to the VPP terminal of the EPROM 63. The functions of the EPROM 63 vary depending on the manufacturer, but in many cases,
12V is applied as VPP during programming, and 5V is applied as VPP during read operation.

As described above, by mounting the EPROM 63, a temporary storage area capable of reading and writing at high speed and a memory area in which information is nonvolatile while programming is possible can be simultaneously realized on the semiconductor memory card. That is, the effects of the present invention can be obtained even if a non-volatile memory other than the ROM is used. For example, according to this embodiment, EPRO
Obviously, an OTPROM or a flash memory can be adopted instead of the M63.

FIG. 11 shows a fifth embodiment according to the first invention. In FIG. 11, the lower address 81 has 19 bits, and each bit is A18 to A0 as in FIG.
The lower address 81 is two pseudo SRAMs 82-
It is input to the address input terminals of No. 1 and 82-2. Further, the data buses 84-1 and 84-2 have 16 bits in total, and the data bus 84-1 has the lower 8 bits D7 to D.
0, and the data bus 84-2 is the upper 8-bit D1.
5 to D8. The data bus 84-1 is a pseudo SRAM.
82-1 is connected to the data input / output terminal and the ROM 83-1 data output terminal. The data bus 84-2 is
Data input / output terminal of pseudo SRAM 82-2 and ROM 8
It is connected to the data output terminal 3-2.

The output enable signal OE is supplied to the data bus 8
Pseudo SRAMs 82-1 and 8-2 for 4-1 and 84-2
It is a signal for permitting the output of 2-2 and the output of the ROMs 83-1 and 83-2. That is, the output enable signal OE
Are connected to the output enable terminals of the pseudo SRAMs 82-1 and 82-2 and the output enable terminals of the ROMs 83-1 and 83-2. The write enable signal WE is a signal for controlling whether to write in the pseudo SRAMs 82-1 and 82-2, and the pseudo SRAM 82-
1, 82-2 are input to the write enable terminals. The card enable signal CE is a signal for enabling the operation of the memory card, and is input to the first input terminal of the decoder circuit 88.

The upper address A19 is the decoder circuit 88.
Is input to the second input terminal of the. Decoder circuit 88
Has the simplest configuration similar to that of the decoder circuit 8 in the first embodiment. When A19 is at the L level, the write or read operation to the pseudo SRAMs 82-1 and 82-2 is permitted, and conversely, When A19 is at the H level, it operates to permit the read operation to the ROMs 83-1 and 83-2. That is, the first output signal 90 of the decoder circuit 88 is the pseudo SRAMs 82-1 and 82-2.
The second output signal 91 of the decoder circuit 88 is connected to the chip enable terminals of the ROMs 83-1 and 83-.
2 is connected to the chip enable terminal.

FIG. 12 is a truth table for explaining the operation of the decoder circuit 88. Here again, the case where each signal is L active is illustrated. First, when the card enable signal CE is at the H level, the output signals 90 and 91 are at the H level regardless of the higher address A19. Therefore, the pseudo SRAMs 82-1 and 82-2 and the ROMs 83-1 and 8-8 are provided.
Both 3-2 are inactive, and neither writing nor reading is possible. Next, the card enable signal CE
Is at the L level, only the memory device selected by the upper address A19 becomes active. In order to clearly show this operation, the operation content is shown in FIG.

In FIG. 13, CE is at L level and A19
Is at the L level, the output signal 90 is at the L level and the output signal 91 is at the H level.
Are active and the two ROMs are inactive. In other words, the addresses from "00000h" to "7FFFFh" are 51
The pseudo SRAM is mapped to 2K words. On the other hand,
When CE is at L level and A19 is at H level, the output signal 90 is at H level and the output signal 91 is at L level, so that the two pseudo SRAMs are inactive and the two ROMs are active. In other words, the address is "8000
The ROM is mapped to 512 K words of 0h "to" FFFFFh ". Thus, according to the fifth embodiment shown in FIG. Even with a memory card having a width, the effects of the present invention can be obtained.

(Second Invention) FIG. 14 shows a first embodiment according to the second invention. In FIG. 14, the output enable signal 101 is a card output enable signal,
An output enable terminal of a 64K-bit EEPROM (attribute memory) 114 having a K × 8 bit configuration;
It is input to the output enable terminal of the 4M bit ROM 115 having a 6K × 16 bit configuration. The write enable signal 102 is input to the write enable terminal of the EEPROM 114. System data bus 103, 10
Reference numeral 4 connects between a host system (not shown) and the semiconductor memory card (not shown), and consists of 16 bits. Of these, the system data bus 103 uses the lower byte of bit “7” to
Corresponds to bit “0”. The system data bus 104 corresponds to bits “15” to “8” of the upper byte. The system data buses 103 and 104 are connected to the data bus switching circuit 105.

The card enable signals CE1 and CE2 are
Both are input to the first and second input terminals of the data bus switching circuit 105 and the first and second input terminals of the chip select circuit 109. Reference numeral 108 denotes an attribute memory space select signal REG, which is input to the input terminal of the on-board setting unit 110. On the other hand, the output signal of the on-board setting unit 110 is input to the third input terminal of the chip select circuit 109. The third input terminal is pulled up inside the chip select circuit 109 with a resistor having a relatively large resistance value. 19-bit address A18 to A0
Are input to the address input terminals of the 4M bit ROM 115 having a 256K × 16 bit configuration. Further, of the addresses A18 to A0, A13 to A1
64K-bit EEPROM 1 with 8K x 8-bit configuration
It is input to 14 address input terminals. Further, only the least significant bit A0 is input to the third input terminal of the data bus switching circuit 105.

Data bus switching circuit 105 and EEPROM
Between the data input / output terminal 114 and the data output terminal of the ROM 115, the lower byte memory data bus 112 is connected.
Tied by. Further, the data bus switching circuit 105 and the data output terminal of the ROM 115 are connected by an upper memory data bus 113. EEPROM 11
4 has 8 bits of data input / output and is connected only to the lower byte memory data bus. On the other hand, the ROM 115
The data input / output is 16 bits, and 8 bits each are connected to the lower byte memory data bus and the upper byte memory data bus. 2 of chip select circuit 109
Of the two output signals, the first output signal 116 is EEPR
The chip enable terminal of the OM 114 is input, and the second output signal 117 is input to the chip enable terminal of the ROM 115.

The printed circuit board 118 is capable of mounting all the constituent parts and is electrically connected to each other by wiring in the above-mentioned relationship. According to the guidelines of the above-mentioned document, the card enable signals CE1 and CE2 and the least significant bit A0 of the address determine the data transfer mode between the semiconductor memory card shown and the host system (not shown), and the card output enable signal OE and write. It is stipulated that the read operation mode or the write operation mode is determined by the enable signal WE, and in addition, whether the common memory or the attribute memory is accessed is determined by the attribute memory space select signal REG. The second invention is based on the specifications that satisfy these operating standards described in the above-mentioned documents.

These input signals in the above document and FIG.
The input signals in the circuit diagram of the first embodiment of the second invention shown in FIG. 4 are the same. That is, O in the above document
E is the output enable signal 101, WE is the write enable signal 102, and A0 is A0 in the address 111.
Further, CE1 corresponds to the card enable signal 106, CE2 corresponds to the card enable signal 107, and REG corresponds to the attribute memory space select signal 108. CE
FIG. 15 shows the relationship between the signal states of 1, CE2, and A0 and the format of data transfer. In FIG. 15, for example, CE
When both 1 and CE2 are at the H level, the card is not accessed. In the read operation mode, the card is in the output state but the write operation to the memory is not performed.

When both CE1 and CE2 are at L level, the system data bus is connected to the system as an integral 16-bit data bus. Inside the card, the lower byte memory data bus is connected to the system data bus, and the upper byte memory data bus is connected to the system data bus. As described above, the data bus switching circuit 105 controls the way of connecting the system data bus and the memory data bus so as to match FIG. 15 according to the states of the card enable signals CE1 and CE2 and the least significant bit A0 of the address. is there.

FIG. 16 shows a function for explaining the operation of the chip select circuit 109. Chip select circuit 1
09 operates to selectively output the L level to the first output signal 116 and the H level to the second output terminal when CE1 is at the L level and the output terminal of the on-board setting unit 110 is at the L level. . Since the chip enable signals of the EEPROM 114 and the ROM 115 are L active and H inactive, the EEPROM 114 is accessed and the ROM 115 is not accessed in this case. Further, the chip select circuit 109 selectively outputs the second output signal 117 at the L level when at least one of CE1 and CE2 is at the L level and the output terminal of the on-board setting unit 110 is at the H level, The first output terminal operates so as to output H level. Therefore, the ROM 115 is accessed and the EEPROM 114 is not accessed.

The on-board setting unit 110 can set the input terminal and the output terminal in a conductive state or a non-conductive state. When the input terminal and the output terminal of the on-board setting unit 110 are set in the conductive state, the attribute memory space select signal 108 is directly input to the third input terminal of the chip select circuit 109. Conversely, when the input terminal and the output terminal of the on-board setting unit 110 are set to the non-conduction state, the attribute memory space select signal 108 changes to the chip select circuit 10.
9 is not supplied to the third input terminal. The third input terminal of the chip select circuit 109 is the chip select circuit 109.
Since it is pulled up by a resistor having a sufficiently large resistance value inside the substrate, when the input terminal and the output terminal of the on-board setting unit 110 are set to the non-conduction state, the output terminal of the on-board setting unit 110 and the chip select circuit 109 The third input terminal becomes H level.

In FIG. 14, the ROM 115 is a common memory and the EEPROM 114 is an attribute memory. Therefore, various attribute information regarding this semiconductor memory card is stored in the EEPROM 114 as needed, and can be read by the system side as needed. The operation of the embodiment having the circuit configuration as described above will be sequentially described. In the first embodiment, in FIG. 14, the EEPROM 114 and the ROM 115 are provided on the printed circuit board 118.
And a logic circuit including a data bus switching circuit 105 and a chip select circuit 109. The on-board setting unit 110 is set so that its input / output terminals are conductive.

In the semiconductor memory card thus configured, the output enable signal 101, the write enable signal 102, the card enable signals 106, 10
7, the attribute memory space select signal 108, and the operation mode determined by A0 in the 19-bit address 111. Since the input / output terminals of the on-board setting unit 110 are set to be conductive, the attribute memory space select signal 108 remains as it is in the chip select circuit 1.
09 is input to the third input terminal. Due to the function of the chip select circuit 109 as described above, only one of the two types of memory devices is selectively accessed. When the L level is added to the attribute memory space select signal 108, the EEPROM which is the attribute memory
114 is accessed and attribute memory space select signal 1
When the H level is added to 08, the common memory R
The OM 115 is accessed.

As described above, it is possible to control whether the attribute memory or the common memory is accessed by the signal which gives the attribute memory space select signal 108. In another operating environment of the first embodiment, in FIG.
Does not mount M114. Further, the input / output terminals of the on-board setting unit 110 are set to be non-conductive. Other than that, it is the same as the first embodiment described above. Chip select circuit 1
Since the third input terminal of 09 is pulled up, it becomes H level regardless of whether L level or H level is added to the attribute memory space select signal 108. Therefore, the output signal 116 never goes to L level, and the ROM 115, which is a common memory, is always accessed.

At this time, if there is an appropriate agreement between the system and the memory card so that the card attribute information is stored at an appropriate address position in the ROM 115,
Even if the attribute information is arranged in the common memory area, it is possible to avoid confusion with the original common memory area. One example of how to negotiate a system and memory card is to use the device information tuples defined in the references mentioned above. In the device information tuple of the common memory, it is described that there is no common memory at the address where the attribute information is placed, and in the device information tuple of the attribute memory,
Describe that there is an attribute memory at the address where the attribute information is located.

On the system side, before accessing the memory card, first, the attribute memory space select signal 10 is sent.
8 is set to L level, and attribute information is scanned. Even if the attribute memory space select signal 108 is set to the L level, the ROM 115 is accessed in the memory card and the attribute information stored at an appropriate address of the ROM 115 can be read. Thereby, necessary attribute information can be read. Moreover, if the device information tuple is stored in this attribute information, the common memory area and the attribute information area will not be confused. As described above, in the first embodiment, the attribute information can be formed so as to be realized in the EEPROM 114, and in other operating environments, the attribute information dedicated memory device is not required and the attribute information is stored in the common memory. Can be stored.

Therefore, in an application in which it is desired to have a relatively large amount of attribute information, or in an application in which it is desired to describe the attribute information on the system side, the memory to which the first embodiment is set is set. On the other hand, in an application where a card is suitable, and above all, where it is important to reduce the number of parts and to reduce the price, the memory card in which the other operating environment of the first embodiment is set is suitable.

FIG. 17 shows a second embodiment according to the second invention. 17, parts that are the same as those shown in FIG. 14 are given the same reference numerals, and redundant description will be omitted. FIG. 17
In the SRAMs 145-1 and 145-2, 128
This is a first 1 Mbit SRAM having K words × 8 bits. The printed circuit board 148 includes the data bus switching circuit 10
5, chip select circuit 109, EEPROM 114,
The two SRAMs 145-1 and 145-2 and the on-board setting unit 110 are mounted, and a connection between them is formed. In FIG. 17, the data input / output terminal 145-
1 is connected to the lower byte side memory data bus 112, while the data input / output terminal 145-2 is connected to the upper byte side memory data bus 113. With this configuration, it is possible to access with 8 bits.
It is also possible to access with 16 bits.

In the second embodiment, when the card attribute information is stored in the EEPROM 114, in addition to the data bus switching circuit 105, the chip select circuit 109, the SRAMs 145-1 and 145-2 on the printed circuit board 148. The EEPROM 114 is mounted, and the on-board setting unit 110 sets its input terminal and output terminal in a conductive state. According to this structure, by setting the attribute memory space select signal 108 to the L level, the EEPROM
Since 114 is accessed, the EEPROM 114 can be used as an attribute memory that stores attribute information. In the second embodiment, when the attribute information of the card is arranged in the area of the SRAM which is the common memory, the EEPROM 114 is not mounted in FIG. 17 and the on-board setting unit 110 has non-input and output terminals. It is set to be conductive.

According to this structure, even if the attribute memory space select signal 108 is set to L level, the EEPROM 1
14 is never accessed and SRAM 145-1
Is accessed. Therefore, the attribute information can be stored and used in the SRAM which is the common memory. According to the second embodiment, even if the common memory is a memory device other than the ROM, and the data width of the device is not only 16 bits but also 8 bits, the second invention is achieved. The same effect can be obtained by applying.

FIG. 18 shows a third embodiment according to the second invention. 18, parts that are the same as those in FIG. 14 are given the same reference numerals, and overlapping descriptions will be omitted. The attribute memory space select signal 168 is similar to the attribute memory space select signal 108 of FIG. 14, but here it is directly connected to the third input terminal of the chip select circuit 169. The output signal of the on-board setting unit 170 is input to the fourth input terminal of the chip select circuit 169. The printed circuit board 178 is capable of mounting these components, and is provided with wirings between them and wiring to the memory card terminals. The on-board setting unit 170 inputs the L level or the H level to the fourth input terminal of the chip select circuit 169 depending on the setting.

The chip select circuit 169 is an EEPRO.
It operates so as to select either M114 or ROM 115. If the fourth input terminal is set to H level, the attribute memory space select signal 1
When 68 is at L level, the output signal 116 is set at L level to make the EEPROM 114 accessible, and when the attribute memory space select signal 168 is at H level, the output signal 117
To L level to make the ROM 115 accessible.
However, when the fourth input terminal is set to the L level, the signal of the attribute memory space select signal 168 is ignored and only the output signal 117 is set to the L level, so that only the ROM 115 can be accessed. .

As described above, even if the configuration of the on-board setting unit 170, the configuration of the chip select circuit 169, and the connection method thereof are different from those of the first embodiment, the second invention can be applied and the effect can be obtained. be able to. In addition, the above-mentioned first,
In the second and third embodiments, the configuration example in which the EEPROM is used as the attribute memory has been shown, but if the content of the attribute information is fixed, the ROM may be used. Alternatively, if the memory card has a built-in battery, the attribute memory is SRAM.
May be used.

[0060]

As described above, according to the semiconductor memory card of the present invention, the following effects can be obtained. First
In the invention, since the pseudo SRAM and the other memories such as the ROM and the EEPROM are mounted on the same memory card, the nonvolatile information is stored even when the power is turned off, and the reading and writing is performed frequently and at high speed. A semiconductor memory card having a large-capacity temporary storage area can be realized at low cost. In the second invention, the on-board setting unit for selecting either the attribute memory or the common memory and the chip select circuit are provided, so that the storage location of the card attribute information can be arbitrarily set in the common memory or the attribute memory. You can As a result, the attributes of the semiconductor memory card can be fixed or can be freely changed, and the attribute memory can be eliminated.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of a semiconductor memory card of the first invention.

FIG. 2 is a diagram showing a truth table of the operation of the decoder circuit 8 in FIG.

FIG. 3 is a memory map diagram of the semiconductor memory card of FIG.

FIG. 4 is a block diagram of a second embodiment according to the first invention.

5 is a diagram showing a truth table of the operation of the decoder circuit 28 of FIG.

FIG. 6 is a memory map diagram of the semiconductor memory card of FIG.

FIG. 7 is a block diagram of a third embodiment according to the first invention.

8 is a diagram showing a truth table of the operation of the decoder circuit 48 of FIG.

9 is a memory map diagram of the semiconductor memory card of FIG. 7. FIG.

FIG. 10 is a block diagram of a fourth embodiment according to the first invention.

FIG. 11 is a block diagram of a fifth embodiment according to the first invention.

12 is a diagram showing a truth table of the operation of the decoder circuit 88 in FIG.

13 is a diagram showing a state of a data bus in FIG.

FIG. 14 is a block diagram of a first embodiment according to the second invention.

FIG. 15 is a diagram showing a relationship between each signal state and a data transfer format according to the second invention.

16 is a diagram showing a truth table of the operation of the chip select circuit 109 of FIG.

FIG. 17 is a block diagram of a second embodiment according to the second invention.

FIG. 18 is a block diagram of a third embodiment according to the second invention.

[Explanation of Codes] 2, 22, 42, 62, 82-1 and 82-2 Pseudo SR
AM 3, 23-1, 23-2, 43, 83-1, 83-2
ROM (nonvolatile memory) 8, 28, 48, 68, 88 Decoder circuit 63 EPROM (nonvolatile memory) 105 Data bus switching circuit 109, 169 Chip select circuit 110, 170 On-board setting section 114 EEPROM (attribute memory) 115 ROM (Common memory) 145-1, 145-2 SRAM (common memory)

Claims (2)

[Claims] 1. One or more pseudo SRAMs accessible by an access method similar to an SRAM, a non-volatile memory capable of retaining stored contents even when power is not supplied, and an output of a host device. The pseudo SRA according to the address
A semiconductor memory card, comprising: a decoder circuit that outputs an enable signal that enables access to either M or the nonvolatile memory. 2. One or more common memories for storing data, one or more attribute memories for storing attribute information indicating the type of the common memory, and the attribute memory and the common memory. A data bus switching circuit for switching a data bus, a chip select circuit for selecting one of the attribute memory and the common memory, and an on-board setting unit for setting a selected state of the chip select circuit. Semiconductor memory card.