JPH0754894B2 - Pulse width modulation circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width modulation circuit (hereinafter, PW) for converting a digital value into a pulse signal having a width according to the digital value.
Abbreviated as M circuit).

2. Description of the Related Art In recent years, PWM circuits that convert digital values into pulse widths have
It is widely used by digitizing various electronic circuits.

An example of the conventional PWM circuit described above will be described below with reference to the drawings.

FIG. 5 is a block diagram showing a configuration example of a conventional PWM circuit. In FIG. 5, reference numeral 15 is a clock generation circuit, 16 is a latch circuit for holding digital data, 17 is a counter circuit with a load function, 18 is a decoder circuit for decoding the output of the counter circuit, and 19 is set / reset. A flip-flop 20 is a timing generation circuit that outputs a latch timing signal to a latch circuit, a data load timing signal and a clock to a counter circuit, and a timing signal to a flip-flop.

The operation of the PWM circuit configured as above will be described below.

The timing generation circuit 20 receives the output of the clock generation circuit 15 and first outputs a latch timing signal to the latch circuit 16. The latch circuit 16 receives the latch timing signal and holds the digital value. Next, the timing generation circuit 20
Outputs a load signal to the counter circuit 17 and a count clock. The counter circuit 17 receives the load signal, loads the data held in the latch circuit 16, and starts counting with the counter clock.
The decoder circuit 18 outputs a timing pulse to the flip-flop 19 when the count value of the counter circuit 17 reaches the set value. Then, the timing generation circuit 20 receives the output of the clock generation circuit 15 and outputs a timing signal to the flip-flop 19 and stops the counting clock output to the counter circuit 17. The flip-flop 19 is set by the output of the decoder circuit 18 and reset by the output of the timing generation circuit 20. flip flop
The output of 19 becomes a pulse signal having a width according to the digital value held by the latch circuit 16.

(For example, Pulse Circuit Technology Encyclopedia, page 695 by Ohmsha) Problems to be solved by the invention However, in the above configuration, a circuit for holding a digital value and a complicated timing generation circuit are required, so a PWM circuit Had a problem in that it became complicated and the circuit scale also increased.

In view of the above problems, the present invention provides a PWM circuit in which a circuit for holding a digital value is omitted and the circuit scale is reduced.

Means for Solving the Problems In order to solve the above problems, the PWM circuit of the present invention includes a clock generation circuit, a counter circuit with a data load function,
An inverting circuit that selects and outputs the output of the counter circuit or an inverted output, a discrimination circuit that outputs whether the data loaded into the counter is valid, and a counter that receives the output of the clock generation circuit and the output of the discrimination circuit The timing circuit outputs a load signal to the circuit and an inversion signal to the inversion circuit.

According to the present invention, by the above-described configuration, the determination circuit is provided, the load signal input of the counter circuit is masked by this output, and at the same time, the inverting circuit receiving the output of the counter circuit is controlled, whereby the load data holding circuit can be omitted. At the same time, the circuit configuration becomes simple.

Embodiment A PWM circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a PWM circuit according to an embodiment of the present invention. In FIG. 1, 1 is a clock generation circuit, 2 is a counter circuit with a data load function, 3 is an inverting circuit that selects and outputs the output or inverted output of the counter circuit 2, and 4 is a data load input 21 of the counter circuit 2. The discriminating circuit 5 for outputting the validity / invalidity of the data inputted to the terminal receives the output of the clock generating circuit 1 and the output of the discriminating circuit 4,
The timing circuit outputs a load signal to the counter circuit 2 and an inversion signal to the inversion circuit 3.

The operation of the PWM circuit configured as described above will be described below with reference to FIGS. 1, 2, and 3.

FIG. 2 shows a concrete circuit configuration example of the block diagram which is one embodiment shown in FIG. In this example, the load input is a 3-bit binary pulse that generates a pulse having a width corresponding to a digital value of "000" to "111". 3 and 4 are timing charts for explaining the operation of FIG.

In FIG. 2, the output of the clock generation circuit 1 is shown in FIG. The discrimination circuit 4 outputs H if the data input to the load data input 6 of the counter circuit 2 is valid, and outputs L if the data is invalid. First, consider a case where the output of the discrimination circuit 4 is H.

The frequency dividing circuit 7 divides the output of the clock generating circuit 1 into ⅛ and outputs it. This is shown in FIG. 3 (b). Since the output of the discrimination circuit 4 is now H, the output of the inverter 10 is L and the output of the AND circuit 9 is always L. Therefore, the output of the D flip-flop 11 becomes L. On the other hand, the output of the NAND circuit is as shown in FIG.
At the same time as resetting, the load timing is given to the counter circuit 2. The counter circuit 2 is like 74HC161,
Binary synchronous counter with 4-bit data loading function 13
And is operated by receiving the output of the clock generation circuit 1. Now the D0, D1, D2 input values of load data input 6 are
Q0, Q1, Q2, Q3 outputs when L, H, L are shown in Fig. 3 (d),
Shown in (e), (f) and (g). The inverting circuit 3 is composed of an EXOR circuit 14. The output of the T flip-flop is L
Therefore, the output of the EXOR circuit 14 becomes as shown in FIG. 3 (h), and the load data of the binary synchronous counter 13 is L,
It can be seen that the period ratio of L and H is 6: 2 corresponding to H and L.

Next, the output of the discrimination circuit 4 becomes H as shown in FIG.
Consider the case of L.

The output of the clock generating circuit 1 is shown in FIG. 4 (a), and the output of the frequency dividing circuit 7 is shown in FIG. 4 (b). Since the output of the discrimination circuit 4 is L now, the output of the NAND circuit 8 becomes L, the output of the inverter 10 becomes H, and the output of the AND circuit 9 becomes as shown in FIG. 4 (c). The output of the D flip-flop 11 is shown in FIG. 4 (d).
The output of the T flip-flop 12 is shown in FIG. If the load data of the binary synchronization counter 13 before the output of the discrimination circuit 4 becomes L is D0 is L, D1 is H, and D2 is L, Q0, Q1, Q2, Q3, Q4 of the binary synchronization counter 13 is assumed.
Is as shown in FIGS. 4 (f), (g), (h), and (i), and the output of the EXOR circuit 14 has a waveform as shown in FIG. 4 (j). As can be seen from this waveform, when the output of the discrimination circuit 4 becomes L, the binary synchronization counter 13 holds the PWM output created from the load data latched immediately before.

As described above, according to the present embodiment, the discrimination circuit 4 is provided,
By masking the load signal input of the binary sync counter 13 with this output and controlling the other input of the EXOR circuit 14 receiving the output signal of the binary sync counter 13, the load data is valid, that is, the output of the discrimination circuit 4 is H. At this time, load data is loaded as an initial value into the binary synchronization counter 13, and a signal having a pulse width corresponding to the data value is output. When the load data is invalid, that is, when the output of the discrimination circuit 4 is L,
The binary synchronization counter 13 continues to output a signal having a pulse width corresponding to the value loaded immediately before the output of the discrimination circuit 4 becomes L.

Although the binary synchronization counter 13 has 4 bits in the embodiment, the number of bits is not limited.

As described above, according to the present invention, the load signal of the counter circuit is masked by the output of the discriminating circuit, and at the same time, the output of the counter circuit is controlled and the inverting circuit for selecting and outputting the output of the counter circuit is controlled to hold the load data It is possible to omit the circuit, reduce the circuit scale, and simplify the entire circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram of a PWM circuit in an embodiment of the present invention, FIG. 2 is a configuration diagram showing a concrete example of FIG. 1, FIG.
FIG. 4 is a timing chart for explaining the operation of FIG.
FIG. 5 is a block diagram showing a specific configuration example of a conventional PWM circuit. 1 ... Clock generation circuit, 2 ... Counter circuit, 3 ...
Inversion circuit, 4 ... Discrimination circuit, 5 ... Timing circuit.

Claims (1)

[Claims] 1. A clock generation circuit, a counter circuit with a data load function that operates by receiving the output of the clock generation circuit, an inverting circuit that selects and outputs the output of the counter circuit or an inverted output, and the counter. The data output to the circuit receives a determination circuit that outputs whether the data is valid, an output of the clock generation circuit and an output of the determination circuit,
A timing circuit that outputs a load signal to the counter circuit and an inversion signal to the inversion circuit, and receives a pulse having a width according to the value of the data output to the counter in response to the output of the determination circuit. , A pulse width modulation circuit characterized by outputting.