JPH0754639B2 - Semiconductor memory - Google Patents

Description

The present invention relates to a semiconductor memory, and more specifically to a semiconductor memory capable of efficiently relieving a defective bit.

[Prior art]

When a defective bit (element) is detected in a semiconductor memory composed of a large number of memory elements, for example, “Nikkei Electronics” December 7, 1981, pages 219 to 226, “Redundant configuration is adopted” is adopted. As described in "Large-capacity RAM", a word line or a bit line connected to a defective element is entirely replaced with a spare word line or a spare bit line.

FIG. 2 shows an example in which only word lines have redundancy. Row address signals A ₀ , ₀ ... A _n , _n are applied to NOR gates 21, 21 ... And the normal word lines X, X ... Corresponding to the contents thereof are selected. X of word lines X, X ... X ₀
If a defect is detected in the row address signal A ₀ , ₀
... A programming element 22, adapted to give A _n , _n
22 is programmed to access the spare word line X'through the NOR gate 23 when the row address signals A ₀ , ₀ ... _An , _n corresponding to the selection of the word line X ₀ are applied.

Reference numeral 24 is a programming element for enabling a spare word line.

[Problems to be solved by the invention]

In such a conventional structure, one defective word line can be relieved by one spare word line. Therefore, when defects are randomly distributed in a large number of word cleanings, a small number of spare word lines can be used. Can't be rescued. In other words, with such a structure, a large number of spare word lines are required to relieve a chip in which defects are randomly dispersed, and an increase in chip size is inevitable.

[Means for solving problems]

The present invention has been made in order to solve the problems of the prior art, and a single spare word line or a spare bit line is divided so that it can be used for repairing a defective element, and a small number of spare word lines can be used. Another object is to provide a semiconductor memory capable of relieving many defects with spare bit lines.

A semiconductor memory according to the present invention is a semiconductor memory provided with a spare word line or a spare bit line for relieving a defective bit, wherein a memory element group connected to the same word line or bit line is divided into a plurality of blocks. The spare word lines or spare bit lines of the book belonging to the same block can be individually selected.

〔Example〕

Similar to FIG. 2, FIG. 1 is a schematic circuit diagram of a main part in an example in which only one word line has redundancy and one spare word line can repair up to four defective word lines. It is a figure.

Row address signals A ₀ , ₀ ... A _n , _n are NOR gates 11, 11, ...
The regular word line X, X ...
Is selected. X'is a spare word line and is provided at a rate of one for every predetermined number of regular word lines X, X ..., Both the regular word lines X, X ... And the spare word lines X'are 4 in the column direction. Is divided into one block 1,2,3,4,
Each block 1, 2, 3, 4 has a column address signal a ₀ ,
_0, a _1, at _1, block 1 at _{a 0 a 1 = "L"} , a 0 1
= "L" for block 2 ₀ a ₁ = "L" for block 3
Each block 4 is selected when _{0 1} = “L”.

In the memory of the present invention, each block ₁ , ₂ , ₃ , ₄ has a programming section Y ₁ , Y ₂ , Y ₃ , Y ₄ surrounded by a broken line, and its structure is row address signal A _{0. 0} … A _n , _n
, Which are input signals, the NOR gate 13 whose inputs are the outputs of the programming elements 12, 12 ... And the output of the programming element 14 indicating the spare word line enable, and the NOR gate 13 outputs And a transfer gate 15 for supplying the output of the transfer gate 15 to the spare word line X '. Transfer gate 15 programming part Y ₁ But for Y ₂ But for Y ₃ But for Y ₄ Are given as control signals, respectively.

The output of the transfer gate 15 of each programming section is wired-OR connected and given to the spare word line X '.

Now, as shown in FIG. 1, the region X ₁ of the block 1 of the _first word line X and the region 2 of the block 2 of the third word line X
X _2, regions X ₃ blocks 3 of the second word line X, defective region X ₄ blocks 4 of the fourth word line X is assumed that existed dispersed. Then, in all programming sections Y _{1 to} Y ₄ in this case, the spare word line X ′ can be accessed by programming the programming elements 12, 12, ... When the defective word line is selected.

By doing this, the column address signal
When block 1 is selected by a ₀ , ₀ , a ₁ , _{1 and} the first word line is selected by row address signal A ₀ , ₀ ... A _n , _n, the area X ₁ is replaced by The area X ₁ 'of the same block of the spare word line X'is selected. Block 2,
Similarly, when 3, 4 are selected and the third, second and fourth word lines are selected, the same block area X ₂ ′ of the spare word line X ′ is replaced with the areas X ₂ , X ₃ and X _4. , X ₃ ′ and X ₄ ′ are selected respectively.

Needless to say, a spare bit line can be similarly constructed.

〔effect〕

According to the present invention as described above, many defective bits can be relieved with a small number of spare word lines and spare bit lines. Further, when defects are randomly distributed in each part of the chip, there is a great yield improving effect, and the effects become more remarkable as the memory capacity increases. Note that the present invention may be used together with a configuration in which one word line or bit line is entirely replaced with a spare word line or a spare bit line as in the conventional case.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic circuit diagram showing an essential part of a memory of the present invention, and FIG.
FIG. 1 is a schematic circuit diagram showing a main part of a conventional memory. X ... Regular word line, X '... Spare word line Y ₁ , Y ₂ , Y ₃ ,, Y ₄ …… Programming section 1,2,3,4 …… Block

Claims (1)

[Claims] 1. In addition to word lines and bit lines corresponding to each row and each column of a plurality of memory elements arranged in a matrix, defective bits arranged in a row direction or a column direction in parallel with the plurality of memory elements. In a semiconductor memory having a spare word line or a spare bit line corresponding to a plurality of spare memory devices for relief, a group of memory devices connected to the same word line or the same bit line and the same spare word line or the same spare bit line are connected. The spare memory element group and the spare memory element group are divided at the same position to form a plurality of divided spare memory element groups and a plurality of blocks in the memory element group, and the spare memory element and the memory element are arranged in the same block. A semiconductor memory characterized by being selectively replaceable in units or columns.