JPH0752874B2 - Multiplexer - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention includes a primary station (master station) and a plurality of secondary stations (slave stations).
The present invention relates to a multiplex transmission device configured by connecting a core wire in a digital chain type.

[Outline of Invention]

In the multiplex transmission apparatus according to the present invention, the address of the secondary station to be connected to the primary station is set in advance, and a large number of secondary stations are connected to the primary station in a digital chain manner. In addition to the polling signal, an address signal is sequentially sent to each secondary station, the secondary station holds the address signal after receiving the polling signal, and sends the polling signal to the secondary stations in the subsequent order in sequence to the primary station in advance. The addresses stored in are set in all the secondary stations, and thereafter data transmission is performed based on the addresses. With such a configuration, an address can be automatically set for each secondary station, and the secondary station can be easily installed.

[Prior art and its problems]

(Prior Art) Generally, in a multiplex transmission device that configures a data transmission system by connecting a primary station and a plurality of secondary stations with a two-core dedicated line, the secondary transmission is performed at an arbitrary point on a common bus. In many cases, a multi-drop method for connecting stations is adopted, and in this case, it is necessary to set a unique address for each secondary station. Such address setting is usually set by a DIP switch or the like provided in each secondary station.

(Problems to be Solved by the Invention) However, when the secondary station needs to be extremely miniaturized, there is a problem that miniaturization is restricted by the DIP switch. When a large number of secondary stations are installed at a time, it is relatively easy to set the addresses, but when the number of secondary stations is increased or decreased after the system configuration of the multiplex transmission device, the addresses may not be continuous. Moreover, there is a possibility that a plurality of secondary stations may be erroneously set to the same address, resulting in a transmission error.

[Object of the Invention]

The present invention has been made in view of the above problems of the conventional multiplex transmission apparatus, and it is not necessary to set an address to each secondary station by a switch or the like at the time of installation, and the number of secondary stations is increased or decreased. Even in such a case, it is a technical subject to easily change and set the address of the secondary station.

[Constitution and effect of the invention]

(Means for Solving Problems) The present invention is a multiplex transmission apparatus in which a primary station and a plurality of secondary stations are connected in a digital chain in a transmission line. The primary station is shown in FIG. As shown, address input means A for inputting an arbitrary address to each secondary station, address storage means M for storing the input address, and unique address signals for each secondary station are sequentially and intermittently sent out. The address signal sending means S and the polling signal when setting the address
Each of the secondary stations has an input / output terminal, and a polling signal transmitting means P for transmitting to the next station, and a data transmitting means D for transmitting data with the secondary station after transmitting an address signal to each secondary station. Filter means connected in between to pass a data signal and an address signal and block a polling signal, and an address signal holding for holding an address signal received after receiving a polling signal given from a primary station or an upper secondary station Means and a polling signal transmitting means for transmitting a polling signal to a secondary station of a lower rank within a suspension period of the address signal transmission of the primary station after receiving a polling signal from the primary station or an upper secondary station; Data transmission means for transmitting data with the primary station after receiving an address for the secondary station.

(Operation) According to the present invention having such a feature, the address of each secondary station is sequentially set in the primary station by the address input means A in advance. Then, the primary station sends an address signal to the secondary station of the highest order after sending the polling signal after the operation starts, and each secondary station holds the address signal after receiving the polling signal and then the secondary station of the next order. If a polling signal is sent to each of the secondary stations and the address is set to each secondary station and the address is sent to the final secondary station, the address setting process is completed. Then, after sending the address to each secondary station, normal data transmission is performed.

(Effect of the invention) Therefore, according to the present invention, it is not necessary to set an address for each secondary station using a DIP switch or the like, and it is possible to automatically set an address. Therefore, the secondary station can be downsized and the workability at the time of installing the secondary station can be improved. When the number of secondary stations is increased or decreased or different secondary stations are added to the transmission line, the address of each secondary station is set again for the primary station and all the secondary stations have that address. Since it is automatically set to, the address can be set extremely easily.

[Explanation of Examples]

(Structure of Embodiment) FIG. 2 is a schematic block diagram showing an embodiment of the multiplex transmission apparatus according to the present invention. In this figure, the primary station 1 and a plurality of 2
The next stations 2 to 6 are connected by a transmission line 7 in a digital chain. That is, the output terminal 1-o of the primary station is connected to the input terminal 2-i of the secondary station 2 connected in the highest order, and the output terminal 2-o of the secondary station 2 is connected to the next by the transmission line 7. Secondary station 3
Input terminal 3-i. Similarly, the secondary station 3 is connected to the secondary station 4 (not shown), the secondary station 4 is connected to the secondary station 5, and the output terminal 5-o of the secondary station 5 is the secondary station 6 of the last rank.
Input terminal 6-i. The output terminal 6-o of the secondary station 6 is grounded via the terminating resistor 8. The primary station 1 sets an address for each secondary station and performs data transmission with the secondary station based on the address.

(Structure of Primary Station) As shown in the structure of FIG. 3, the primary station 1 is provided with a keyboard 11 and a display 12 which are address input means A for inputting an address.
A central processing unit (hereinafter referred to as CPU) 14 is connected via a controller 13 that controls the device 12. The CPU 14 also has a read-only memory (hereinafter referred to as ROM) 15 for storing the arithmetic processing procedure, and a random access memory (hereinafter referred to as "address storage means M" having a storage area for storing the set secondary station address and the like. 16) is connected. R
As will be described later, the AM 16 is provided with a counter used at the time of address setting and data transmission, a secondary station number area for storing the secondary station number, and a timer area for taking a timing of sequentially transmitting data. The CPU 14 has a function of an address signal transmitting means S for sequentially transmitting the inputted address to each secondary station of an address having a frequency band of 1 MHz or less, and a function of a data transmitting means D for performing data transmission with each secondary station after the address setting. Has been achieved. The output of the CPU 14 is connected to the above-mentioned transmission line 7 via a P / S / S / P converter 17 that alternately converts serial data and parallel data. In addition, the primary station 1 is controlled by the CPU 14 and the secondary station 2 connected to the highest priority when setting the address.
On the other hand, for example, it has a polling signal transmitting circuit 18 for transmitting a polling signal having a frequency of 1 MHz, and its output end is connected to the transmission line 7.

(Structure of Secondary Station) FIG. 4 is a block diagram showing the structure of the secondary station, but the other secondary stations 3 to 6 have the same structure. A low pass filter 21, a data signal transmitting / receiving circuit 22, a polling signal receiving circuit 23, and an address signal receiving circuit 24 are connected to the input terminal 2-i of the secondary station 2. The low-pass filter 21 is a passive filter consisting of LC, and has a frequency of 1M used as a polling signal regardless of the power supply state.
The frequency of 1MHz that is transmitted from the transmission line 7 by cutting off the Hz signal
Address signals and data signals having the following frequency bands are directly transmitted to the output terminal 2-o. The address signal receiving circuit 24 receives the address signal supplied from the input terminal 2-i as an address signal holding means, that is, an address buffer.
25 and the comparator 26, the polling signal receiving circuit 23 is an address buffer when receiving the polling signal.
25 is set, and the polling signal transmission timing is given to the polling signal transmission circuit 27. The polling signal transmission circuit 27 is set to 2 during the suspension period of the address signal transmission of the primary station 1.
It is a transmission circuit for sending a polling signal to the secondary station 3 in the next order, which is connected to the output terminal 2-o of the next station 2, and thereafter supplies an operation start signal to the comparator 26. The comparator 26 compares the address received by the address signal receiving circuit 24 with the address held in the address buffer 25. If the addresses match, a signal that enables transmission / reception is sent to the data signal transmitting / receiving circuit. Give to 22. The data signal transmission / reception circuit 22 is a data transmission means for performing data transmission between the secondary station 2 and the primary station 1, and transmits output data given from the outside and outputs the received data as input data. .

(Operation of the present embodiment) Next, the operation of the present embodiment will be described with reference to the flowchart and time chart. 5 and 6 are flowcharts showing the operation of the primary station 1 and each secondary station,
FIG. 7 is a time chart showing signals of various parts in an initial operation when setting an address. In this embodiment, first, the operation of setting the address of each secondary station is performed from the keyboard 11 of the primary station. That is, when the primary station 1 starts operation,
It is checked in 31 whether the data transmission mode is entered. If it is not in the transmission mode, the address n is in the address setting state, so the counter n in the RAM 16 is cleared and the process proceeds to step 33 to increment the counter value. Then, the input of an address from the keyboard 11 is awaited (step 34), and if there is an input, it is checked in step 35 whether it is an end input. If it is not the end input, the address value is written in the secondary station address area of the RAM 16 (step 36), the process returns to step 33, the counter n is incremented, and the same processing is repeated. For example, FIG. 8 shows the addresses of the secondary stations 2 to 6 thus written. That is, the addresses A (1) to A of the secondary stations 2 to 6
(5) is "1", "3", "10", "5", "4" respectively
Is set as.

When the addresses are sequentially set up to the final secondary station 6, the counter value n is written in the secondary station number N in step 37, and it is checked in steps 38 and 39 whether the system is in the data transmission mode and data transmission is performed. Wait for the mode to be entered. In this case, the end code END is inserted after the address in the RAM 16 and the value of the number of secondary stations N (5 in this case)
Is held.

In the data transmission mode, the counter n is first cleared in step 40, and the process proceeds to step 41, in which the polling signal P1 is transmitted as shown in FIG. 7 (a). Then, in steps 42 and 43, the counter n is incremented after sending the polling signal, and it is checked whether the count value of the counter n is equal to the number N of secondary stations. If it is not equal to the number N of secondary stations, the routine proceeds to step 44, where the address signal A (1) to the secondary station 2 is transmitted. The secondary station 2 waits for the polling signal in step 61 after the operation is started, and if the polling signal P1 is received, the process proceeds to step 62 to receive the address signal A (1) from the address signal receiving circuit 24,
Since the polling signal has been received before that, it is set in the address buffer 25. Then, in step 63, the polling signal transmission circuit 27 sends out the polling signal P2 to the secondary station 3 as shown in FIG. 7 (b). After transmitting the address signal, the primary station 1 resets the timer and waits for the time up (steps 45 and 46). If the time is up, the process returns to step 42 to increment the counter n, and thereafter the same processing is repeated to send the address signal A (2) to the secondary station 3. After the same processing is performed for the secondary stations 4 to 5 and the addresses A (3) to A (6) are held in the respective address buffers 25, the secondary stations in the subsequent order respectively.
The polling signals P4 and P5 for 4 and 5 are transmitted. Then, the secondary station 6 in the last order sends the polling signal P6 onto the transmission line 7 after holding the address A (5) in the address buffer, but this signal is not received by any secondary station. 1
When the count value of the counter n becomes equal to the secondary station number N in step 43, the next station 1 exits the loop of steps 42 to 46 and finishes the automatic address setting process.

Then, data transmission / reception to / from each secondary station is started. First, the process proceeds to steps 47 and 48 to reset the counter n and then increment the counter n. Then, the process proceeds to step 49, and as shown in FIG.
The address signal A (1) for the address is read from the RAM 16 and transmitted. This address signal passes through all the secondary stations 2 through the low-pass filter 21 connected to the input / output terminals of each secondary station.
6 to 6, each of the secondary stations 2 to 6 checks whether or not the received address matches the held address when receiving the address signal in steps 64 and 65. This address signal A (1) matches only the address signal held in the address buffer 25 of the secondary station 2. Therefore, the secondary station 2 proceeds to routine 66 to transmit / receive the data signal, and the other secondary stations return to step 64 to wait for the next address signal. That is, as shown in FIGS. 9A and 9B, when the primary station 1 sends the data D ₁₂ to the secondary station 2 in the routine 50, the secondary station 2 sends the data signal D ₂₁ to the primary station 1. Send. When the data transmission with the secondary station 2 is completed in this way, the primary station 1 counts the count value n of the counter.
Is equal to the number N of secondary stations held in RAM16. If it is not equal to this value, the process returns to step 48 and the counter n is incremented and the address signal A (2) to the secondary station 3 is transmitted. On the other hand, when the data transmission of the routine 66 is completed, the secondary station 2 returns to step 64 and waits for the next address signal. Next, when the address signal A (2) to the secondary station 3 is transmitted, as shown in FIG.
As shown in (c), data transmission is performed between the primary station 1 and the secondary station 3. Thus, thereafter, FIG. 9 (a)-
As shown in (f), when the data transmission between the primary station 1 and each of the secondary stations 2 to 6 is completed, the number of secondary stations N of the counter n matches. After the processing of one cycle of data transmission to all secondary stations is completed in this way, the process returns from step 51 to step 47 to repeat data transmission / reception and continue data transmission.

When the number of secondary stations connected to the transmission line 7 is increased or decreased or added, the addresses of all the secondary stations are sequentially set again in the primary station 1. When the secondary station is set to the data transmission mode, the set address is automatically set to each secondary station, and the data transmission can be continued in the same manner thereafter.

Although the present embodiment has described a multiplex transmission apparatus using five secondary stations, it goes without saying that a similar system can be constructed by using a larger number of secondary stations. Further, in the present embodiment, a low pass filter is provided to pass the data signal to each secondary station as it is and to block only the polling signal, but a band cut filter that blocks only the frequency of the polling signal may be used. It is also possible to configure the filter of each secondary station by using a high-pass filter that cuts off only the polling signal by modulating a data signal at a frequency higher than that of the polling signal by using a low-frequency signal as the polling signal.

Furthermore, in the present embodiment, a description has been given of the multiplex transmission device that alternately performs data transmission between each secondary station and the primary station. However, in the case where each secondary station is a secondary station having one function of reception or transmission, Needless to say, the present invention can also be applied.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a primary station of a multiplex transmission apparatus according to the present invention, FIG. 2 is a schematic block diagram showing one embodiment of the multiplex transmission apparatus according to the present invention, and FIG. FIG. 4 is a block diagram showing the configuration of the next station.
FIG. 5 is a block diagram showing the configuration of the next station, FIG. 5 is a primary station, FIG. 6 is a flowchart showing the operation of each secondary station, and FIG.
Time chart of each station at the time of initial operation when setting an address to the next station, FIG. 8 is a memory up showing an example of the address written in the RAM which is the address storage means of the primary station, FIG. 3 is a time chart showing the data transmission state of each station during a normal data transmission operation. A: address input means, M: address storage means, S
... Address sending means, P ... polling signal sending means, D ... data transmitting means, 1 ... primary station, 2 to 6 ...
Secondary station, 7 ... Transmission line, 11 ... Keyboard, 12 ... Display, 14 ... CPU, 15 ... ROM, 16 ... RAM, 18,27 ...
... polling signal transmitting circuit, 21 ... low-pass filter (filter means), 22 ... data signal transmitting / receiving circuit (data transmitting means), 24 ... address signal receiving circuit, 25 ... address buffer (address signal holding means), 26 ...... Comparator

Claims (2)

[Claims] 1. A multiplex transmission device in which a primary station and a plurality of secondary stations are connected by a transmission line in a digital chain manner, wherein the primary station inputs an arbitrary address to each of the secondary stations. Address input means, address storage means for storing the input address, address signal transmission means for sequentially and intermittently transmitting a unique address signal to each secondary station, and a polling signal at the earliest when the address is set. Polling signal transmitting means for transmitting to the secondary stations in the order, and data transmitting means for performing data transmission with the secondary station after transmitting the address signal to each secondary station, each of the secondary stations Filter means connected between the input and output terminals for passing a data signal and an address signal and blocking a polling signal, and a receiving means for receiving a polling signal given from the primary station or an upper secondary station. Address signal holding means for holding an address signal to be generated, and a secondary station of a lower rank within a suspension period of the address signal transmission of the primary station after receiving a polling signal from the primary station or an upper secondary station. A multiplex transmission apparatus comprising: a polling signal transmitting means for transmitting a polling signal; and a data transmitting means for transmitting data with the primary station after receiving an address for the secondary station. 2. The polling signal transmitted by the polling signal transmitting means of the primary station and each of the secondary stations is a signal having a frequency higher than that of the data signal and the address signal, and the filtering means of each of the secondary stations. Is a low-pass filter that cuts off the polling signal and passes a data signal and an address signal.