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JPH0752719B2 - Method for manufacturing vertical semiconductor superlattice - Google Patents

Method for manufacturing vertical semiconductor superlattice

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Publication number
JPH0752719B2
JPH0752719B2 JP23930086A JP23930086A JPH0752719B2 JP H0752719 B2 JPH0752719 B2 JP H0752719B2 JP 23930086 A JP23930086 A JP 23930086A JP 23930086 A JP23930086 A JP 23930086A JP H0752719 B2 JPH0752719 B2 JP H0752719B2
Authority
JP
Japan
Prior art keywords
vertical semiconductor
superlattice
semiconductor superlattice
crystal surface
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP23930086A
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Japanese (ja)
Other versions
JPS6394615A (en
Inventor
孝志 福井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
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Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP23930086A priority Critical patent/JPH0752719B2/en
Publication of JPS6394615A publication Critical patent/JPS6394615A/en
Publication of JPH0752719B2 publication Critical patent/JPH0752719B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)
  • Recrystallisation Techniques (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、超高度の1次元電子トランジスタ、あるいは
低発振しきい値を持つ量子井戸細線構造レーザ等に利用
される縦型半導体超格子の製造方法に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a vertical semiconductor superlattice used for ultra-high-dimensional one-dimensional electron transistors, quantum well thin-line structure lasers having a low oscillation threshold, and the like. The present invention relates to a manufacturing method.

〔従来の技術〕[Conventional technology]

第3図(a)に理想化されたAlAs−GaAs縦型半導体超格
子を示す。同図において、基板表面Sは(100)に対し
[011]方位に角度θだけ傾いている。また、同図
(b)は縦型半導体超格子のX線回折位置を示すもので
あり、同図(a)に示すような理想的な縦型半導体超格
子構造が得られている場合には、図中A、Bに示す位置
に超格子回折が見られる。
FIG. 3 (a) shows an idealized AlAs-GaAs vertical semiconductor superlattice. In the figure, the substrate surface S is tilted by an angle θ with respect to (100) in the [011] direction. Further, FIG. 6B shows the X-ray diffraction position of the vertical semiconductor superlattice, and when an ideal vertical semiconductor superlattice structure as shown in FIG. , Superlattice diffraction is seen at the positions indicated by A and B in the figure.

このような縦型半導体超格子を作製する試みは、既に分
子線エピタキシャル成長法(MBE)でなされている(ア
プライド フィジックス レターズ 45巻、6号、620
−622頁(1984年):P.M.Petroff等)。このMBE法による
従来方法では、GaAs(100)結晶の[011]方位に1度か
ら5度傾いた基板を用いており、Asビームを照射しなが
ら、AlとGaのビームを1/2分子層に相当する量交互に基
板上に供給することにより、AlAs−GaAs縦型半導体超格
子の作製を試みている。
Attempts to fabricate such vertical semiconductor superlattices have already been made by molecular beam epitaxial growth (MBE) (Applied Physics Letters, Vol. 45, No. 6, 620).
−622 (1984): PM Petroff et al.). In this conventional method by the MBE method, a substrate tilted from the [011] direction of the GaAs (100) crystal by 1 to 5 degrees is used. We are trying to fabricate an AlAs-GaAs vertical semiconductor superlattice by alternately supplying the amount equivalent to that on the substrate.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

しかし、このMBE法で作製した結晶を電子線回折で調べ
た結果、第3図(a)に示すような理想的な構造は得ら
れなかった。この点について、本願発明者が鋭意研究し
た結果、MBE法によると結晶表面に吸着した原子の表面
拡散距離lが小さいことに原因があることをつきとめ
た。
However, as a result of investigating the crystal produced by this MBE method by electron beam diffraction, an ideal structure as shown in FIG. 3 (a) was not obtained. As a result of diligent research by the inventor of the present invention, it was found that the reason is that the surface diffusion distance l of the atoms adsorbed on the crystal surface is small according to the MBE method.

すなわち、第8図(a)に示すように、まず、ビーム照
射によって基板結晶表面のテラス部(基板結晶表面の水
平の部分)1の任意の位置にAlAs2が吸着し横方向に移
動しようとするが、その表面拡散距離lが小さいため、
同図(b)に示すようにほとんどのAlAsは原子ステップ
(基板結晶表面の段差部)3まで達しない。この状態か
ら引き続いてGaAs4を吸着させるため、テラス上には同
図(c)に示すように2次元核形成が起こってしまう。
その結果、原子ステップから横方向への均一な核形成が
行われず、第3図(a)に示すような縦型半導体超格子
が形成されない。
That is, as shown in FIG. 8 (a), first, AlAs 2 is adsorbed to an arbitrary position on the terrace portion (horizontal portion of the substrate crystal surface) 1 of the substrate crystal surface by the beam irradiation and tries to move laterally. However, since the surface diffusion distance l is small,
As shown in FIG. 2B, most of AlAs does not reach the atomic step (stepped portion on the crystal surface of the substrate) 3. Since GaAs4 is continuously adsorbed from this state, two-dimensional nucleation occurs on the terrace as shown in FIG.
As a result, uniform nucleation is not performed in the lateral direction from the atomic step, and the vertical semiconductor superlattice as shown in FIG. 3A is not formed.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の縦型半導体超格子の製造方法は上記問題点に鑑
みてなされたものであり、結晶面から所定の方位に傾い
た基板結晶表面上に複数の有機金属化合物ガスを順次切
り換えて導き、前記有機金属化合物ガスに応じた半導体
を前記基板結晶表面上に析出する有機金属気相成長法
(MOCVD法)を用い、前記有機金属化合物ガスに応じて
形成される2種類以上の半導体を1分子層形成する間に
順に析出して超格子を形成するものである。
The method for manufacturing a vertical semiconductor superlattice of the present invention is made in view of the above problems, and sequentially switches and guides a plurality of organometallic compound gases on the substrate crystal surface tilted in a predetermined direction from the crystal plane, One molecule of two or more kinds of semiconductors formed according to the organometallic compound gas is used by using a metalorganic vapor phase epitaxy method (MOCVD method) in which a semiconductor according to the organometallic compound gas is deposited on the substrate crystal surface. During the formation of layers, they are sequentially deposited to form a superlattice.

〔作用〕[Action]

MBE法では、成長系内が高真空のため結晶表面の状態が
活性と考えられるが、MOCVD法では、系内の圧力が高く
水素雰囲気で結晶成長を行うため水素吸着により結晶表
面状態が安定し、供給原子が表面に既に吸着された水素
と置換しながら動いてゆくそのため、結晶表面に吸着し
た原子が動き易く、MBE法による場合と比較して表面拡
散距離lが十分に大きくなり、横方向に均一に核形成が
起こる。
In the MBE method, the state of the crystal surface is considered to be active due to the high vacuum in the growth system, but in the MOCVD method, the crystal surface state is stabilized by hydrogen adsorption because the pressure in the system is high and the crystal growth is performed in a hydrogen atmosphere. , The supplied atoms move while substituting with hydrogen already adsorbed on the surface, so the atoms adsorbed on the crystal surface move easily, and the surface diffusion distance 1 becomes sufficiently large compared to the case of the MBE method, and the lateral direction Uniform nucleation occurs.

〔実施例〕〔Example〕

以下、実施例と共に本発明を詳細に説明する。 Hereinafter, the present invention will be described in detail with reference to Examples.

第1図は、本発明の一実施例を示す模式図であり、GaAs
(100)面の[011]方位にθ=2度傾いた基板結晶上に
AlAs0.5分子層、GaAs0.5分子層を交互に析出した例を示
している。同図(a)に示すように、基板結晶表面のテ
ラス1上の任意の位置に吸着したAlAs2の原子は、それ
ぞれのテラス上において左方すなわち原子ステップ3に
向かって移動する。そして、同図(b)に示すように、
原子ステップ3から横方向に均一な核形成が行われゆ
く。この核形成が同図(c)に示すようにステップ間隔
dの1/2に達した時点で、AlAs2に代えて引き続きGaAs4
の析出を行い、同図(d)に示すような層を形成する。
FIG. 1 is a schematic view showing an embodiment of the present invention.
On a substrate crystal tilted by θ = 2 degrees to the [011] direction of the (100) plane
An example is shown in which AlAs0.5 molecular layers and GaAs0.5 molecular layers are alternately deposited. As shown in FIG. 3A, the AlAs2 atoms adsorbed at arbitrary positions on the terrace 1 of the substrate crystal surface move leftward, that is, toward atomic step 3 on each terrace. Then, as shown in FIG.
Uniform nucleation is carried out laterally from atomic step 3. When this nucleation reaches 1/2 of the step interval d as shown in FIG. 7C, GaAs4 is continuously replaced with AlAs2.
Is deposited to form a layer as shown in FIG.

以下に実施例の結晶成長条件の詳細を示す。高周波加熱
の横型炉を用い、0.1気圧の減圧化で成長を行った。原
料としてトリエチルアルミニウム、トリエチルガリウム
及びアルシンを用いた。反応管内の分圧は、それぞれ4.
7×10-7atm、1.3×10-6atmおよび4.7×10-4atmであり、
水素キャリアガスも含め全ガス流量は3リッター/分で
ある。また、成長温度は650℃である。そして、この条
件で、原料トリエチルアルミニウムとトリエチルガリウ
ムを交互に3秒ずつ切り替えた。成長速度は、AlAsおよ
びGaAs共に0.47Å/秒であり、6秒間に交互に析出した
AlAsとGaAsの析出量は2.82Å/秒で丁度1分子層の厚さ
に相当する。全成長時間3時間で成長層厚さ0.5μmの
結晶を作製した。
Details of the crystal growth conditions of the examples are shown below. Growth was carried out at a reduced pressure of 0.1 atm using a horizontal furnace of high frequency heating. Triethylaluminum, triethylgallium and arsine were used as raw materials. The partial pressure in the reaction tube is 4.
7 × 10 −7 atm, 1.3 × 10 −6 atm and 4.7 × 10 −4 atm,
The total gas flow rate including the hydrogen carrier gas is 3 liters / minute. The growth temperature is 650 ° C. Then, under these conditions, the raw material triethylaluminum and triethylgallium were alternately switched for 3 seconds each. The growth rate was 0.47Å / sec for both AlAs and GaAs, and they were deposited alternately in 6 seconds.
The amount of AlAs and GaAs deposited is 2.82Å / sec, which corresponds to the thickness of one monolayer. A crystal having a growth layer thickness of 0.5 μm was produced with a total growth time of 3 hours.

このようにして作製した縦型半導体超格子のX性回折を
第2図に示す。図中A、Bの回折が超格子構造による回
折である。超格子の回折角より超格子周期が原子ステッ
プの間隔と一致していることがわかり、第3図に示す理
想的な縦型半導体超格子が実現していることが明らかで
ある。
The X-ray diffraction of the vertical semiconductor superlattice thus produced is shown in FIG. The diffractions A and B in the figure are diffractions due to the superlattice structure. It can be seen from the diffraction angle of the superlattice that the superlattice period matches the interval of atomic steps, and it is clear that the ideal vertical semiconductor superlattice shown in FIG. 3 has been realized.

本実施例では、(100)から[011]方位へ2度傾けてい
るが、同方向へ0.2度〜4.0度傾いた基板を用いた場合に
も、同様に理想的な縦型半導体超格子が実現できた。な
お、傾斜θとステップ間隔dの関係は、 d=h/tanθ で表される(但し、hは第1図(d)に示すように1分
子層の厚さである)。したがって、たとえば、(100)
面から0.2度傾いた場合には、d=811Å、4.0度傾いた
場合にはd=40Åとなる。
In this embodiment, the substrate is tilted by 2 degrees from (100) to the [011] direction. However, even when a substrate tilted by 0.2 to 4.0 degrees in the same direction is used, an ideal vertical semiconductor superlattice is similarly obtained. It was realized. The relationship between the inclination θ and the step interval d is represented by d = h / tan θ (where h is the thickness of one molecular layer as shown in FIG. 1 (d)). So, for example, (100)
When tilted 0.2 degrees from the plane, d = 811Å, and when tilted 4.0 degrees, d = 40Å.

基板面方位に関して、本実施例のごとく(100)面の[0
11]方位に傾いた場合は縦型半導体超格子が形成される
が、[010]方位あるいは[001]方位に傾いた場合には
良好な縦型半導体超格子は得られない。これは原子ステ
ップにある不対ボンド(ダングリングボンド)が[01
1]方位に伸びているためである。また、(111)面の
[11]方位及び(110)面の[11]方位に傾いた基
板結晶上にも良好な縦型半導体超格子が得られている。
Regarding the substrate plane orientation, as in the present embodiment, [0] of the (100) plane
A vertical semiconductor superlattice is formed when tilted in the [11] orientation, but a good vertical semiconductor superlattice cannot be obtained when tilted in the [010] orientation or the [001] orientation. This is because the unpaired bond (dangling bond) in the atomic step is [01
1] because it extends in the direction. In addition, a good vertical semiconductor superlattice is obtained on a substrate crystal inclined in the [111] direction of the (111) plane and the [11] direction of the (110) plane.

さらに、超格子を構成する2種類の半導体を交互に析出
したときの析出量が1分子量相当量よりずれた場合に
は、縦型半導体超格子は大きく傾く。すなわち、第4図
に示すように、超格子の傾き角をβとし、基板の傾き角
をθとすると、 tanβ={1−(m+n)}/tanθ が成立する。ここに、m,nは、(AlAs)m(GaAs)nの
指数m、nであり、m原子層、n原子層を示す。したが
って、m=0.5、n=0.5のときはβ=0度となる。しか
し、例えば1周期で1.1分子層相当の厚さを析出した場
合、すなわち、m+n=1.1の原子層になると、θ=2
度のときにβ=70度にもなり、ほとんど平行型超格子に
近くなってしまう。したがって、1周期の成長速度は正
確に1分子層に合わせる必要がある。そのためには、第
3図(b)に示す理想化された縦型半導体超格子のX線
回折における点AおよびBに示す位置に超格子回折が見
られるように原料供給量を調整すればよい。
Further, when the deposition amount when two types of semiconductors forming the superlattice are deposited alternately deviates from the equivalent amount of one molecular weight, the vertical semiconductor superlattice is greatly inclined. That is, as shown in FIG. 4, when the inclination angle of the superlattice is β and the inclination angle of the substrate is θ, tan β = {1- (m + n)} / tan θ. Here, m and n are the indices m and n of (AlAs) m (GaAs) n, and indicate m atomic layer and n atomic layer. Therefore, when m = 0.5 and n = 0.5, β = 0 degrees. However, when a thickness equivalent to 1.1 molecular layers is deposited in one cycle, that is, when an atomic layer of m + n = 1.1 is obtained, θ = 2
At the same time, β = 70 degrees, which is close to a parallel superlattice. Therefore, the growth rate of one cycle needs to be accurately adjusted to one molecular layer. For that purpose, the raw material supply amount may be adjusted so that the superlattice diffraction can be seen at the positions indicated by points A and B in the X-ray diffraction of the idealized vertical semiconductor superlattice shown in FIG. 3 (b). .

また、第5図に成長速度とX線の超格子回折強度の関係
を示す。同付からわかるように、2Å/秒以上の速い成
長速度では付着原子が結晶表面で十分拡散できず、原子
ステップからの成長が起こらない。
Further, FIG. 5 shows the relationship between the growth rate and the superlattice diffraction intensity of X-rays. As can be seen from the attached figure, at a high growth rate of 2Å / sec or more, the attached atoms cannot sufficiently diffuse on the crystal surface, and the growth from the atomic step does not occur.

また、本実施例では1分子層形成する間に2種類の半導
体を交互に析出しているが、3種類以上の半導体を順に
析出して3種類以上にの半導体からなる縦型半導体超格
子を形成することもできる。
In addition, in the present embodiment, two kinds of semiconductors are alternately deposited during the formation of one molecular layer, but a vertical semiconductor superlattice composed of three or more kinds of semiconductors is formed by sequentially depositing three or more kinds of semiconductors. It can also be formed.

つぎに、第6図および第7図に、このようにして製作さ
れた縦型半導体超格子を利用した素子の具体例を示す。
第6図に示すものは、変調ドーピング構造をもつ1次元
電子FET(電界効果トランジスタ)である。100Å程度の
厚さを持つ縦型半導体超格子をバッファ層(あるいはク
ラッド層)で挟むことにより1次元電子構造となってお
り、電子が1次元化されることにより不純物による散乱
確率が減り高移動度トランジスタが得られる(ジャバニ
ーズ ジャーナル オブ アプライド フィジックス
19巻12号L735−738頁1980年:H.Sakaki)。なお、同図に
おいて、11はソース、12はゲート、13はドレイン、14は
SiドープAlrGa1-rAs層、15は本実施例により製作された
AlAs−GaAs縦型半導体超格子、16は1次元電子ガス、17
はアンドープGaAs層、18は半絶縁性GaAs基板である。
Next, FIGS. 6 and 7 show specific examples of devices utilizing the vertical semiconductor superlattice manufactured in this way.
What is shown in FIG. 6 is a one-dimensional electron FET (field effect transistor) having a modulation doping structure. A vertical semiconductor superlattice having a thickness of about 100 Å is sandwiched between buffer layers (or clad layers) to form a one-dimensional electronic structure. The electrons become one-dimensional, and the probability of scattering due to impurities decreases, resulting in high movement. Degree Transistor (Javanese Journal of Applied Physics
Vol. 19, No. 12, L735-738 1980: H. Sakaki). In the figure, 11 is a source, 12 is a gate, 13 is a drain, and 14 is
Si-doped Al r Ga 1-r As layer, 15 was fabricated according to this example
AlAs-GaAs vertical semiconductor superlattice, 16 is one-dimensional electron gas, 17
Is an undoped GaAs layer, and 18 is a semi-insulating GaAs substrate.

また、光素子への応用として第7図に量子井戸細線構造
レーザを示す。電子および正孔の状態密度が1次元化す
ることにより不連続となり、発振しきい値が温度に対し
て安定化する(アプライドフィジックス レターズ 40
巻11号939−941頁 1982年:Y.Arakawa等)。ここに、21
はp−GaAsキャップ層、22はp−GaAsクラッド層、23は
本実施例により製作されたAlAs−GaAs縦型半導体超格
子、24はn−AlGaAsクラッド層、25はn−GaAs基板であ
る。
In addition, as an application to an optical device, a quantum well wire structure laser is shown in FIG. When the density of states of electrons and holes becomes one-dimensional, they become discontinuous, and the oscillation threshold value stabilizes with temperature (Applied Physics Letters 40
Volume 11, pages 939-941 1982: Y. Arakawa et al.). Where 21
Is a p-GaAs cap layer, 22 is a p-GaAs clad layer, 23 is an AlAs-GaAs vertical semiconductor superlattice manufactured by this embodiment, 24 is an n-AlGaAs clad layer, and 25 is an n-GaAs substrate.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明の縦型半導体超格子の製造方
法によれば、MOCVD法を利用しているので、結晶表面に
吸着した原子が動き易く、MBE法による場合と比較して
表面拡散距離lが十分に大きくなる。そのため基板結晶
の原子ステップから横方向に均一に核形成が起こり、理
想的な縦型半導体超格子を形成することができる。
As described above, according to the method for manufacturing a vertical semiconductor superlattice of the present invention, since the MOCVD method is used, the atoms adsorbed on the crystal surface are easily moved, and the surface diffusion distance is longer than that in the case of the MBE method. l is sufficiently large. Therefore, nucleation occurs uniformly in the lateral direction from the atomic step of the substrate crystal, and an ideal vertical semiconductor superlattice can be formed.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例を示す説明図、第2図は本実
施例により作製した縦型半導体超格子のX線回折図、第
3図(a)は理想的な縦型半導体超格子を示す構造図、
第3図(b)はそのX線回折図、第4図は条件を変えた
場合の縦型半導体超格子を示す構成図、第5図は結晶成
長速度とX線の超格子回折強度の関係を示す特性図、第
6図および第7図はそれぞれ縦型半導体超格子を利用し
た素子の具体例を示す図、第8図は従来の方法示す説明
図である。 1……テラス、2……AlAs、3……原子ステップ、4…
…GaAs。
FIG. 1 is an explanatory view showing an embodiment of the present invention, FIG. 2 is an X-ray diffraction diagram of a vertical semiconductor superlattice produced by this embodiment, and FIG. 3 (a) is an ideal vertical semiconductor superlattice. Structural diagram showing the lattice,
FIG. 3 (b) is its X-ray diffraction diagram, FIG. 4 is a configuration diagram showing a vertical semiconductor superlattice under different conditions, and FIG. 5 is a relation between crystal growth rate and X-ray superlattice diffraction intensity. FIG. 6, FIG. 6 and FIG. 7 are views showing specific examples of devices using a vertical semiconductor superlattice, and FIG. 8 is an explanatory view showing a conventional method. 1 ... Terrace, 2 ... AlAs, 3 ... Atomic step, 4 ...
… GaAs.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01S 3/18 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical indication H01S 3/18

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】所定の指数面から所定の方位に傾いた基板
結晶表面上に複数の有機金属化合物ガスを順次切り換え
て導き、前記有機金属化合物ガスに応じた半導体を前記
基板結晶表面上に析出する有機金属気相成長法を用い、
前記有機金属化合物ガスに応じて形成される2種類以上
の半導体を1分子層形成する間に順に析出して超格子を
形成することを特徴とする縦型半導体超格子の製造方
法。
1. A plurality of organometallic compound gases are sequentially switched and guided on a substrate crystal surface tilted in a prescribed direction from a prescribed exponential plane, and a semiconductor corresponding to the organometallic compound gas is deposited on the substrate crystal surface. Using metalorganic vapor phase epitaxy
A method for manufacturing a vertical semiconductor superlattice, comprising forming two or more kinds of semiconductors formed according to the organometallic compound gas in order while forming one molecular layer to form a superlattice.
【請求項2】基板結晶表面は、低指数面が(100)、(1
11)または(110)であるときに、それぞれ[011]方
位、[11]方位または[11]方位に0.2度から4.0度
傾いたものである特許請求の範囲第1項記載の縦型半導
体超格子の製造方法。
2. The substrate crystal surface has low index planes of (100) and (1
11. The vertical semiconductor superstructure according to claim 1, wherein when it is 11) or (110), it is tilted from [011] orientation, [11] orientation or [11] orientation by 0.2 to 4.0 degrees. Lattice manufacturing method.
JP23930086A 1986-10-09 1986-10-09 Method for manufacturing vertical semiconductor superlattice Expired - Lifetime JPH0752719B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23930086A JPH0752719B2 (en) 1986-10-09 1986-10-09 Method for manufacturing vertical semiconductor superlattice

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23930086A JPH0752719B2 (en) 1986-10-09 1986-10-09 Method for manufacturing vertical semiconductor superlattice

Publications (2)

Publication Number Publication Date
JPS6394615A JPS6394615A (en) 1988-04-25
JPH0752719B2 true JPH0752719B2 (en) 1995-06-05

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JP (1) JPH0752719B2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2720930B2 (en) * 1988-07-06 1998-03-04 科学技術振興事業団 Quantum thin film device with grid
EP0386388A1 (en) * 1989-03-10 1990-09-12 International Business Machines Corporation Method for the epitaxial growth of a semiconductor structure
JP2575901B2 (en) * 1989-11-13 1997-01-29 新技術事業団 Quantum structure with grid
JPH04154113A (en) * 1990-10-18 1992-05-27 Agency Of Ind Science & Technol Crystal growth method
JPH04154114A (en) * 1990-10-18 1992-05-27 Agency Of Ind Science & Technol Crystal growth method
US5238867A (en) * 1991-07-09 1993-08-24 Posco Educational Foundation Method for preparing an optical switching device having multiple quantum wells
DE69330845T2 (en) * 1992-03-26 2002-04-04 Canon K.K., Tokio/Tokyo Methods for the growth of compound semiconductor layers
DE69323127T2 (en) * 1992-08-10 1999-07-22 Canon K.K., Tokio/Tokyo Semiconductor device and manufacturing method

Also Published As

Publication number Publication date
JPS6394615A (en) 1988-04-25

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