JPH07503564A - Method and apparatus for reducing memory wear in computer systems - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Method and apparatus for reducing memory wear in computer systems [Technical field] TECHNICAL FIELD The present invention relates generally to memory for computer systems, and more particularly to: Reduced wear on storage locations and storage circuits in computer memory systems or regarding prevention.

[Background of the invention] The basic storage hierarchy of a computer includes main memory, cache storage, and auxiliary storage. Includes storage devices (eg, disks). Main memory is usually static RAM This main memory is implemented in either dynamic RAM (SRAM) or dynamic RAM (DRAM). The storage device can be directly accessed via the corresponding physical address by the program software. Store accessible data. Cache storage provides access to main storage. To compensate for the long read delays associated with It is used as a high-speed buffer for accessing data.

Dielectric breakdown or failure of any one circuit or conductor of the memory chip This causes the entire memory chip to fail. One cause of memory circuit failure is This is road wear.

Many factors contribute to memory circuit wear. For example, electromigration tion phenomenon is a contributing factor to circuit wear.

Electromigration is triggered by collisions with energetic electrons. This is the movement of atoms that occurs. This movement is due to the exchange of momentum between the electron and the atom. It is something that Over a period of time, as a result of electromigration , voids may form within the metal conductor. Voids in metal conductors cause current density cause an increase in the degree of This reduces the conductor dimensions as a result of voids, but the remaining conductor must still carry the same amount of energetic electrons. It can be explained as follows. Such an increase in current density intensifies the atomic movement in the conductor, This promotes the growth of metal voids in the conductor. After all, complete An open circuit can occur, causing dielectric breakdown of the entire memory chip.

Current density guidelines for long-term reliability to reduce or prevent conductor wear was established by memory circuit designers. Essentially, this guideline , the thickness of the wire must be sufficient to withstand a constant current for a given period of time. It tells you how much it should be. That period is the lifetime of the chip. It is. Reliability guidelines indicate that memory chips will wear out during their useful life. It is set so that it never occurs.

When designing a memory chip, determine the worst-case current density value for each circuit. Ru. Worst-case values assume the same circuit switches every memory cycle. This is what I did.

Since memory locations are used relatively unevenly, chip designers can Memory chips must be designed based on the situation. (Tsukano system) In some applications, certain physical address locations may be used preferentially over others.

As a result, memory circuits corresponding to locations that are used preferentially are Also, firing/switching occurs frequently. Therefore, the memory circuits used preferentially have a higher duty cycle than other memory circuits, so these The problem remains that the probability that the memory circuit in the memory circuit will fail increases.

One solution to this problem is to keep the circuit utilization constant; This allows the worst-case current density specification for each circuit to be reduced. Conclusion Using thinner wires reduces the physical density of the circuit and Speed can be improved.

Additionally, software programs tend to load memory in a way that is highly biased toward a relatively small number of locations. There is a natural tendency to access the Mori location. For example, In our research, we found that with a total main memory size of 16 megabytes, 1000 frequently accessed blocks (each block is 128 bytes in size) ) account for more than 90% of the total CPU accesses to main memory. It was. Similar studies have also found that access is heavily biased toward a small number of blocks in the cache. another study showed similar access patterns for auxiliary storage. Similar results have been reported. For example, the so-called 80/20 rule Roughly 80% of accesses to 20% of memory locations on disk I'm looking forward to it.

The unbalanced nature of memory access has implications for the long-term reliability of storage systems. may cause undesirable results. This is a record that is particularly sensitive to wear conditions. This applies especially to memory techniques. For example, flash memory technology is currently non-volatile. It is widely used to implement storage devices (eg, main memory). flash Cells in a memory chip typically undergo ioo, ooo addresses before wear-out conditions occur. It has a lifespan of 1°ooo, ooo access. Various memory techniques Has better lifetime characteristics than rush memory, but generally reduces flattening to memory cells. It can be said that long-term reliability can be improved by reducing the average number of accesses. This point , thick (skewed data access patterns are inherently undesirable) . Smaller portions of memory cells are accessed more frequently and are therefore more susceptible to wear. This is because there is a tendency to

Another potential cause of memory reliability problems is the heat generated by the current. A short or open circuit at the metal level.

Heat accumulation can degrade dielectric materials. Unevenness to a fixed memory location Certain memory access patterns may increase the occurrence of such undesirable results. There is a tendency to add

Potential memory wear-out by spreading memory accesses more evenly Proposals are being made to reduce the For example, in U.S. Pat. No. 4,922,456, Non-volatile memory design double-buffers to evenly distribute wearout potential Techniques for diffusing access to are disclosed. However, in this patent, the memory Special for accessing a circular buffer that can be used as a temporary buffer for writing. Although it deals with rotation techniques, it does not deal with reducing the imbalance of accesses to the memory itself. stomach.

Additionally, the CPU designates an internal address that corresponds to a particular physical location in memory. It is generally known in the art to provide address mapping or translation. ing. For example, such mapping can be used to create is performed for virtual to real address translation via Multiple programs dynamically use real main memory under the control of the operating system. will be able to be shared. Another example of such mapping is for large memory This is the configuration table. This saves memory in large chunks (e.g. 4 megabytes). Accessing failed chunks can be reconstructed by Provides the ability to separate from However, such mapping methods are more uniform. No effort has been made to achieve the use of a uniform memory circuit.

[Summary of the invention] Unbalanced memory access patterns are inherent in the nature of software programs. However, the present invention periodically changes the method of storing data in memory. This solves the above problem by achieving more uniform access to memory cells. solve. This technique breaks up the normal pattern of using memory cells. provides an opportunity to improve long-term memory reliability by Ru.

Therefore, according to the invention, data in a storage location of a computer memory Apparatus and methods are provided for managing the storage of. The device inputs the input address receives the input address and changes its input address according to the translation method to generate the output address. It includes a conversion means. Each input address and each output address are - Corresponds to one storage location in memory.

Furthermore, the control means that generates the control signal and sends it to the conversion means controls the conversion method of the conversion means. effectively control the storage of data so that it occupies the entire storage location of computer memory. The changes to the input addresses by the translation means are distributed uniformly over the This will be implemented in a systematic manner.

The method according to the invention receives input addresses from a source, each containing a segment. and providing a translation method that modifies the input address accordingly; The storage of data is evenly distributed throughout the storage locations of computer memory. a step of periodically modifying the conversion scheme in a predetermined systematic manner and adjusting the output address; the step of changing the input address according to the translation scheme to generate the address; and the step of changing the input address according to the translation method to generate the address and outputting the dress.

[Brief explanation of the drawing] The above and other objects, features, aspects and advantages will be apparent from the following detailed description of the invention. will be more readily apparent and better understood.

FIG. 1 is a block diagram according to a preferred embodiment of the invention.

FIG. 2 is a diagram showing a specific example of a conversion circuit according to a first preferred embodiment of the present invention. Ru.

Figures 3A-3D illustrate rotation of data in memory locations according to the present invention. This is a diagram.

FIG. 4 is a diagram showing another embodiment of the conversion circuit.

Figures 58 to 5C show how to protect data when changing the conversion method. It is a figure showing whether it is possible.

FIG. 6 is a diagram showing a prior art cache memory.

FIG. 7 is a diagram illustrating the cache memory of FIG. 6 incorporating the present invention.

FIG. 8 is a block diagram of another embodiment of the invention.

[Detailed description of the preferred embodiment] The present invention is first applied to computer memory systems in general, i.e., to any computer. data memory systems, and then specifically to cache storage systems. Consider the invention as incorporated. However, the scope of the present invention is It should be fully understood that the invention is not limited to storage devices. In addition, those skilled in the art By applying the present invention, registers, magnetic tape storage devices, semiconductor disk storage devices, etc. The details below demonstrate that other memory systems, such as You will understand from the detailed explanation.

Referring first to Figure 1, when performing various computational operations, the central processing unit Computer components such as (CPU) 15 write data to memory 20 , or retrieve data from memory 20. Memory 20 can be used in any computer. It is representative of data memory, and can be a complete storage hierarchy such as main memory, or simply It may be a portion or segment of a memory chip. Generally, the memory 20 includes a plurality of are organized into different individually addressable locations. Each position is its own position. To retrieve the contents stored in or write data to that location, the CPU 15 has a unique corresponding address that is used to access that location. Than Specifically, during each write operation, the CPU 15 determines the position where data is to be written. During each read operation, CPU 15 retrieves the data. Specify the address corresponding to the desired position.

According to the present invention, the conversion circuit 25 is connected between the CPU 15 and the memory 20, and the conversion circuit 25 is connected between the CPU 15 and the memory 20. A control device 30 is connected to the conversion circuit 25. The conversion circuit 25 is a computer with conversion or mapping circuitry that may already be present in the memory system. Alternatively, such matuping can be provided as an additional layer of matuping. If converting circuitry is not present in the computer memory system, converting circuitry 25 may be the only mapping layer present in the system.

Any of the many programmable microcontrollers on the market is a converter controller. It can be used for 30 days. Such microcontrollers are well known to those skilled in the art. (This microcontroller is not explained below.) be easily programmable to perform the functions of the conversion device 3o to It will be understood that - In general, the input address that the CPUI 5 should access After specifying the input address, the conversion circuit 25 receives the input address and converts it to the prespecified conversion method. Modify or transform that input address according to an expression to generate an output address.

Furthermore, in order to intelligently manage the conversion method of the conversion circuit 25, the conversion control device 3o sends a control signal to the conversion circuit 25. Workload balance or all memory locations To facilitate access across the can be changed periodically. It is necessary to change the conversion method using the conversion control device 30. The specific period depends on the particular type of memory 20 being balanced. In addition, strange The conversion method can be dynamically changed at any time period as needed, such as every second, every minute, every day, every week, etc. can be done.

Numerous techniques and circuits can be implemented to implement the conversion scheme, and may be implemented in accordance with the present invention. A number of conversion schemes can be used to achieve the desired result. therefore, The examples set forth herein are included for illustrative purposes only and are not intended to limit the invention. It should not be construed as − For example, The conversion circuit 25 converts all or all of the addresses specified by the CPU 15. Contains multiple selectable inverters that systematically invert some bits.

As shown in FIG. 2, the selectable inverter may be an exclusive OR gate 35. . FIG. 2 shows an example of the conversion circuit 25 required for a 2-bit address. For illustrative purposes only, and with reference also to FIG. The conversion by step 35 will be described in detail.

For example, "II" represents the input address and "OII" represents the output address. vinegar. The input address is the address specified by the CPUI 5 being accessed. After the input address is converted by the conversion circuit 25, the output address is This is the address where it occurs. The output address corresponds to a physical storage location within memory 20. respond. Each bit of the input address is received by an exclusive ○R agate 5. Therefore, the conversion circuit 30 includes two exclusive OR gates 35. Also, convert Control signals from controller 30 are also received by exclusive OR gate 35.

In order to be able to control each exclusive OR gate 35 individually and independently, , each exclusive OR gate 35 receives its own control signal from the conversion control device 3o. take. CB, tO are exclusive OR gates corresponding to bit O of the 2-bit address. CB, tl are bit 1 of the 2-bit address. represents a control signal sent to exclusive OR gate 35 corresponding to . Therefore, the conversion The controller 30 sends either the high signal or the low signal to the corresponding exclusive OR gate 35. You can control whether to invert the bits of a logical address by sending can.

As shown in Figures 3A-3D, each has its own separate conversion scheme or has a mapping state for four independent periods, time or time 4. explain. Each frame 40-55 represents a physical storage location within the memory 20, and each frame 40-55 represents a physical storage location within the memory 20. bit is a 2-bit input address specified by CPU 15 for access. Represents a response.

Table 1 shows that during each of the four time periods, time 4, the conversion controller 30 shows the control signal sent to the exclusive OR gate 35 of the conversion circuit 25.

CBltOcBIti Time 1 0.

Time 2 0 1 Time 31 Q Time 4 1 1 During time 1, control signals CB, t0 and CB! Since t1 is both low (0), it is converted Each bit of the output address is equal to each bit of the input address, as follows: Ru.

Bit 0°; Bit 0. Bit 1° = Bit 1° Therefore, during time 1, the input The output address oo and the output address OO are equal and each correspond to the same physical location 4o. , input address 01 and output address o1 are equal and correspond to the same physical location 45, respectively. Accordingly, the input address 10 and the output address 10 are equally located at the same physical location 5o. , the input address 11 and the output address 11 are equally located at the same physical location. Corresponds to 55.

During time 2, the control signal CB, . . . is sent to the exclusive OR gate of bit O. teeth The control signal CB,t is low (0) and sent to the exclusive OR gate 35 of bit 1. X is high (1). Therefore, according to the logic of exclusive OR gate 35, , bit 0 of the translated output address is equal to bit 0 of the input address , bit 1 of the translated output address is equal to bit 1's complement of the input address.

Bit O0 = Bit 01 Bit 1° = Bit 11 Therefore, during time 2, The input address oO is converted to the output address O1, and this input address OO is the physical Corresponding to position 45, input address 01 is converted to output address 00, and this input Address 01 corresponds to physical location 40 and input address 10 corresponds to output address 11. translated, this input address lO corresponds to physical location 55 and input address 11 is translated into output address 10, which input address 11 corresponds to physical location 5o. .

During time 3, the control signal CB1to sent to the exclusive OR gate 35 of bit 0 is high (1) and the control signal Cl5 sent to the exclusive OR gate 35 of bit 1 It1 is low (0). Therefore, according to the logic of exclusive OR gate 35, Bit O of the converted output address is equal to the complement of bit O of the input address, as follows: Therefore, bit 1 of the translated output address is equal to bit 1 of the input address.

Bit O0 = Bit O1 Bit 1° = Bit 1° Therefore, during time 30, the input The input address 00 is converted to the output address lO, and this input address 00 is the physical address Corresponding to the input address 50, the input address o1 is converted to the output address 11, and the second input address Address 01 corresponds to physical location 55, input address 10 changes to output address 00. This input address 10 corresponds to the physical location 4o, and the input address 11 corresponds to the output input address 01, which corresponds to physical location 45.

During time 4, the control signal CB sent to the exclusive OR gate of bit 0, t0 is high. (1), and the control signal C□t1 sent to the exclusive OR gate of bit 1 is also high ( 1). Therefore, according to the logic of exclusive OR gate 35, as follows: Bit 0 of the translation output address is equal to the complement of bit 0 of the input address; Bit 1 of the input address will also be equal to the complement of bit 1 of the input address.

Bit 0° = Bit 0. Bit 1゜=bit l.

Thus, during time 4, input address OO is converted to output address 11, This input address OO corresponds to the physical location 55, and the input address o1 is the output address. This input address o1 corresponds to the physical location 50 and the input address address 10 is translated into output address O1, and this input address 10 is placed at physical location 45. Correspondingly, input address 11 is converted to output address oO, and this input address 1 1 corresponds to physical location 40.

Thus, for each period from time 1 to time 4, the output address of the input address to the input address specified by the CPU. The corresponding physical location in memory has been rotated. That is, specified by the CPU 15 The same input address accesses a different physical location during each period.

Furthermore, the correspondence between the exclusive OR gate and the number of address bits is shown in Figure 2. Although mentioned in the example above regarding 2-bit addresses, it is not necessary that each address - It should be understood that exclusive OR gates are not required for each bit. In addition, 1 In large memories, such as megabits or larger, each It may be impractical to provide an exclusive OR gate for each address bit. . In such large memories, the exclusive OR gate can be divided into approximately 3 or 4 higher order It is practical and necessary to connect to the dress bit, thereby allowing 8 to 16 different different mapping states are possible.

As shown in FIG. 4, a conversion circuit 25 that can be used to implement different conversion schemes. Another example is to systematically set the bits of an address specified by CPU 15 to It includes a circular shift register 60 that shifts.

Shift register 60 may be any conventional register commercially available; each corresponds to an individual bit of the input address specified by CPU 15. A plurality of latches 65 may be included to receive the bits. Differences in memory 20 To generate four separate output addresses, each corresponding to a physical location, Using a 4-bit input address 0110 and 4 periods, period 1 to period 4. So how is the same input address 0110 translated by shift register 60? Indicates whether

In response to a load control signal received from the conversion controller, shift register 60 is Each latch 65 is loaded with one bit of the input address. Next, register 60 performs a shift operation according to the shift control signal received from the conversion control device 30. do. The resulting translated output address is then accessed in memory 20. will be missed. In this example, no shifting occurs during period 1, and the translated output address is during period 2, period 3, and period 4, shift register 60 performs 1st shift, 2nd shift, and 3rd shift, respectively. The results are shown in Table II below.

Table II Bit O Bit 1 Bit 2 Bit 3 Person address 0 1 1 0 Shift Output address after conversion Bit O Bit 1 Bit 2 Bit 3 Period 1: OO110 Period 2: 1 0 0 1 1 Period 3:2 1 0 0 1 Period 4:3 1 1 0 0 Shift registers can be used to convert input addresses of arbitrary length, and Longer input addresses require more (more) bits to accommodate the input address bits. It should be understood that registers with latches need only be used. In addition, If the power address is extremely long, such It may not be necessary or practical to shift all bits of the input address. Sometimes it doesn't make sense. Note that in such a situation, the translated output address cannot be applied. For example, shift 4 or 5 bits of the input address to Sometimes all you need to do is to

As mentioned above, the conversion method can be changed over any period of time as needed. can. The specific period during which the conversion method should be changed depends on the individual design of the memory system. and reliability requirements. However, for questions where memorized data is still required, When you change the conversion method, any data stored under the previous conversion method will be transferred to the CPU15. Please understand that it is not accessible by. Therefore, at that time, the CPU The input address specified by 15 no longer corresponds to the same output address and all This means that the input address will be translated differently to the output address, and the memo will be The corresponding physical locations within the library will also be different. Cache is simply used for temporary storage. uses a memory system such as memory, but does not block programs or data. Other memory systems that require permanent memory storage may require a different conversion method. That becomes a problem. Such permanently stored programs require certain conversion methods and must be preserved when changing from one conversion method and period to another. Ta For example, an operating system that resides on a hard disk drive. The program requires such preservation.

Referring now to Figures 58 through 5C, such permanently stored programs Temporary buffer 70 is used in memory systems that have programs or data. to retranslate the program to a location in memory using the new conversion method to be implemented. can do. For example, a new conversion scheme and period may be found in memory location 75. If you need to transfer data to memory location 90 and vice versa copies some of the data in location 90 to buffer 70, as shown in FIG. 5A. or transfer.

Some buffers 70 include cache memory, part of main memory, external disk, etc. , in any unused memory space (or in memory dedicated for such purpose) It can also be a part of the chip. It is then stored in location 75, as shown in FIG. 5B. data can be written to location 90, and more specifically, to location 75. day of data can be written on top of the data at position 9o. Next, as shown in Figure 5C, , the data in the temporary buffer 70 (the data originally stored in location 90) is It is possible to write to location 75. Therefore, the data previously stored in location 75 The data is now stored in location 90, and the data previously stored in location 90 is now stored in location 90. It is stored in position 75 when . This data is then applied to the new conversion method and period. can be accessed correctly in time.

Next, a specific application of the present invention to a cache memory will be considered. first In order to present the operation of the present invention in a cache in an appropriate environment, A brief explanation of flash memory will be given. To simplify the drawing, in Figure 6 A unidirectional associative cache 95 is shown. Cache access from CPU Assume that all addresses are in 8-byte double word (DW) units. , On a typical high-performance computer, each access to main memory takes 20 to 3o machine cycles may also be required.

To compensate for such long read delays for main memory accesses, CP Cache storage devices are widely used as high-speed buffers for data access. It's here. In many computer systems, cache is simply a storage subsystem. It is implemented as a hardware layer of the system and has no impact on the program/software. do not have.

Typically, a cache is a block of memory of a fixed size (e.g., 12 8 bytes), and includes a directory section 100 and an array section 105. Contains two parts.

Cache array 105 stores the actual data blocks and Directory 100 contains the contents of data blocks in array 105 (e.g. address and other status tags). Data accessed by CPU A cache miss condition often occurs when a block is missing from the cache. A new block entry can be written to the cache, and it can trigger the replacement of another existing block from the cache.

When creating a new block entry in the cache, you generally data is retrieved from a lower level storage hierarchy (eg, main memory bag Wl).

Cache replacement is typically LRU (least-recently-used ) managed by a standard algorithm. CPU data access is cached A cache hit is a condition in which a valid block entry in a cache is hit. The probability (cache hit rate) is typically 93-98% on modern computers. in range. Therefore, on a computer with a cache, the cache itself The body uses bits 15-24 of C address 110 to Intercept and satisfy most dataer access requests (reads and writes) .

The CPU uses the 32-bit address (bit 0 -31), etc., is specified. The cache array 105 is It can also be considered as a one-dimensional table with IK (1024) entries, with each entry An entry contains a block (line) of data 128 bytes in size. therefore , the total size of this cache is 128 bytes. , cache from CPU For each access address to address 110, bits 25-3 of address 110 1 is the line offset (for example, byte address within a 128-byte line) bits 15-24 of address 110 are IK cache entries. used to select one of the

This is a direct mapped cache, so there is only one good line entry. . Cache directory 100 contains addresses for all line entries. cache array 105 stores all data bits. do. To simplify the diagram, a single array chip covers all cache devices. Assume that the data bits are retained. Each directory entry or record 115 is an ADDR field holding 15 address bits and one valid address bit. It has a validity tag (V bit). A cache entry has an associated V bit of Only considered valid when high (1).

Line selection bits of bits 110, bits 15-24 of bits 100 and array 105. Select the line entry on both edges of b. selected directory - The entry is read into the comparison logic circuit 120. Comparison logic circuit 120 Set bits O-14 of address 110 to the ADDR field of directory record 115. and also check the V bit of record 115. address 110 Bits 0-14 match the ADDR field of directory record 115. , and the V bit of record 115 is high, comparison logic circuit 12 0 sends the "Hit J signal to the CPU. If either condition is not met, the comparative The logic circuit 120 sends a "miss" signal to the CPU.

In cache array 105, bits 15-24 are 128-byte lines. Bits 25-28 are used to select 125, and bits 25-28 are used to select Used to select one of the 16 DWs in selected line 125 The output of the aDW that is It is considered valid only when taken. During a cache "miss" condition, the required A copy of the selected cache line is retrieved from main storage. need to be loaded into. Next, change the directories to reflect the new line status. If the bird information (address bits O-14 and V bit) is not updated properly, No.

Referring now to FIG. 7, according to the present invention it is possible to implement an input address O. Wear. That is, cache directory 100 and cache array 1 The line entry selection at 05 is changed according to the translated address. Ru. The converted address is specified by the conversion circuit 25 and the conversion control device 30. generated according to the specified conversion method.

That is, the particular column specified by bits 15-24 of input address 110 In entries are not selected for access. Instead, it is converted Bits 15-24 of input address 110 are changed to generate the output address The converted output address is modified by the conversion circuit and used to select for access. be exposed.

The conversion circuit 25 and conversion control device 30 shown in association with the cache 95 are generally The memory system may include the same circuitry described above in connection with the memory system. difference Additionally, the conversion scheme outlined above can also be used within cache 95. , or any other suitable method to convert bits 15-24 of input address 110. Any conversion method can be used.

When the present invention is used in a cache storage device, the CP After main memory is updated by a write from U, the existing data contained in the cache is Existing data may be removed or invalidated. This invalidation process is called a write This is particularly simple for caches that are implemented in a one-way manner. Right through one hand The formula automatically writes each data write from the CPU to the main memory in addition to writing it to the cache. This allows Mori to write through.

In the previous example, we used a single mapping for all accesses to memory; It is possible to divide the memory of a computer into multiple sections and map each section separately. Can also be done. Referring now to FIG. 8, memory 20 is divided into four sections 160-17. It is divided into 5 parts. Each portion 160-175 has its own transformation scheme, and each The conversion scheme is implemented by respective portions 140-155 of conversion circuit 25.

One memory portion is selected for each access from the CPU. Partial selection one The example is based on two bits in the access address that do not change with translation (also It is. Each of the conversion circuit portions 140 to 155 is separately connected to the conversion control device 30. control signals (eg, an XOR mask). For illustrative purposes, the conversion circuit section Minutes 140 to 155 are bit vectors received from conversion controller 30, respectively. From the input address (from cp u) by doing le mask and X○R, Generate mapped output addresses. This arrangement allows each part to be data allocation can be reorganized.

In practice, the mapping of parts of memory and the reorganization of data allocation are Less disruptive to performance than total reorganization. For example, Figure 8 is The cache array chip 105 is considered to be an on-chip partition. Wear. Partition selection is made by bits 15-16 of input address 110 from the CPU. Therefore, bits 15-16 are never modified by conversion circuit 25. This arrangement configuration allows cache mapping to be reorganized periodically for each individual partition. . During each mapping reorganization, only the cache contents of the relevant partitions are invalidated. There is a need. One advantage is that three-quarters of the contents of the cache are correct even after reorganization. , yet the cache can effectively operate as a high-speed memory buffer.

Although the invention has been described with respect to specific embodiments, numerous alternatives, modifications, and variations may occur. It is clear from the above description that it will be obvious to a person skilled in the art. Therefore, the original The scope and spirit of the invention as well as the scope and spirit of the invention and the scope and spirit of the appended claims It is intended to include all such alternatives, modifications and variations.

FIG.1 FIG.2 Procedural amendment IF (voluntary) International application PCT/US921067132, title of the invention Method and apparatus for reducing memory wear in computer systems 3. Person who makes corrections Relationship to the incident: Patent applicant Address: Armonk, New York, United States 10504 (no street address) Name International Business Machines Corporation 4. Agent Address: Postal code 242 IBM Japan Co., Ltd. 1623-14 Shimotsuruma, Yamato City, Kanagawa Prefecture Inside Yamato Office Te1 (main representative 10462-76-1111 contact information; 0462-73-332 5.0462-73-3318 As per attached sheet The scope of the claims 1. Manage the storage of data in storage locations of the computer memory (2o) a device for receiving the input address and converting the input address according to a conversion method; conversion means (25) for changing the address to generate an output address; control means (30) for generating and sending a control signal to the conversion means; generates an output address, each said input address includes multiple segments, and said Each input address and each output address are stored in one memory of the computer memory. Corresponding to the position, the control signal periodically modifies the conversion scheme so that the data so that the storage of data is uniformly distributed throughout the storage locations of computer memory. the input address is changed by the conversion means in a predetermined systematic manner; A device characterized by:

2. The conversion method is modified after a preset period has elapsed. The device according to claim 1.

3. The conversion means (25) performs all conversions according to one conversion method each during a certain period of time. The device according to claim 1 or 2, characterized in that the input address of the device is changed.

4. Each part (160, 165, 170, 175) is small (all are one code) Computer memory (20) converting means (25) adapted to manage the storage of data in the data memory; ) corresponds to the first portion of the computer memory according to the first transformation scheme. the second address of the computer memory according to the second translation scheme. Multiple conversion methods (140, 145) that change the input address corresponding to the part , 150, 155).

5. Place the data in the computer memory location corresponding to the generated output address. 5. A device according to claim 1, wherein a data is written.

6. The conversion means (25) receives an input address from the central processing unit (15). A device according to any of the preceding claims, characterized in that the device comprises: a.

7. In order to generate an output address, said conversion means (25) converts said input address into as claimed in any one of the preceding claims, characterized in that: The device described in.

8. The converting means (25) inverts the selected segment of the input address. 3. The method according to any one of the preceding claims, characterized in that it comprises reversing means (35) for Device.

9. Claim 8, characterized in that said inverting means (35) comprises an exclusive OR gate. The device described in.

10. The converting means (25) comprises a circular shift register (60). Apparatus according to any of the preceding claims, characterized in that it is characterized by:

11. A plurality of conversion methods are installed on the machine side, and a computer according to the second conversion method is ・Reload the previously stored data according to the first conversion method into the storage location of the memory. means (7o) for converting the first conversion method to generate the second conversion method; Claims 1 to 3 and 5 to 1o are characterized in that they are modified to The device described in any of the above.

12. The means for reloading data temporarily holds the data to be reloaded. 12. The device according to claim 11, characterized in that it comprises a partial buffer (70) for.

13. Manage storage of data in storage locations of computer memory (20) A method of Input ads each containing a segment from the source (15).

the step of receiving a response; providing a translation scheme for modifying the input address accordingly; The storage of data is uniformly distributed throughout the storage locations of computer memory. periodically modifying the transformation scheme in a predetermined systematic manner such that modifying said input address according to a translation scheme to generate an output address; stages and outputting the output address; method including.

14. The step of periodically modifying the conversion method is performed after the preset period has elapsed. 14. The method according to claim 13, characterized in that:

15. All input addresses change during a period of time and according to one conversion method. 15. The method according to claim 13 or 14, characterized in that:

16, each portion including at least one computer memory storage location; A computer system consisting of multiple parts (160, 165, 170, 175) a first conversion scheme adapted to manage the storage of data in the memory (20); an input corresponding to a first portion of computer memory according to a first conversion scheme; the address, and the second translation method is the computer according to the second translation method. ・Multiple conversion methods such as changing the input address corresponding to the second part of memory 14. A method according to claim 13, characterized in that:

17. At the computer memory location corresponding to the generated output address, Claims 13 to 16, further comprising the step of writing data. The method described in any of the following.

18. The source that receives the input address is the central processing unit t(15) 18. A method according to any one of claims 13 to 17.

19. The step of changing the input address includes selecting a selected segment of the input address. Any one of claims 13 to 18, characterized in that the method includes the step of changing the ment. The method described in.

20. The conversion scheme includes inversion of selected segments of the input address. 20. A method according to any one of claims 13 to 19, characterized in that:

21, the inversion of the selected segment of said input address is executed by an exclusive OR gate (3 21. The method according to claim 20, characterized in that it is carried out using 5).

22. The first conversion method is applied to the storage location of the computer memory according to the second conversion method. Reloads previously stored data into a storage location in computer memory according to a formula wherein the first conversion method is modified to generate the second conversion method. Any one of claims 13 to 15 and 17 to 21, characterized in that Method described in Crab.

Continuation of front page (72) Inventor: Singh, David Ting, New York, USA 17 Vuolino Drive, Poughkeepsie, WA

Claims (22)

[Claims] 1. A device for managing the storage of data in storage locations in computer memory. The location is Each input address and each output address corresponds to a storage location in computer memory; receiving the input address each including a plurality of segments and using a conversion method; means for modifying said input address to generate said output address; and periodically converting said input address. A control signal for modifying the format is generated and sent to said conversion means, thereby converting the data. so that the storage of data is evenly distributed throughout the storage locations of computer memory. modifying the input address by the conversion means in a predetermined systematic manner; control means and equipment containing. 2. Claim characterized in that the conversion method is modified after a preset period of time has elapsed. The device according to item 1. 3. The conversion means converts all input ports according to one conversion method throughout a period of time. 3. Device according to claim 1 or 2, characterized in that it changes the dress. 4. each portion each includes at least one computer memory storage location , to manage the storage of data in multiple parts of computer memory. the converting means is adapted to convert the first change the input address corresponding to the part, and also change the computer according to the second conversion method. multiple transformations that change the input address corresponding to the second part of the data memory Device according to claim 1, characterized in that a method is provided. 5. The data is placed in the computer memory location corresponding to the generated output address. Device according to any one of claims 1 to 4, characterized in that data is written. . 6. The conversion means receives an input address from a central processing unit. An apparatus according to any preceding claim. 7. In order to generate an output address, said translation means selects said input address. according to any one of the preceding claims, characterized in that the segment Device. 8. an inversion in which the conversion means inverts selected segments of the input address; Apparatus according to any preceding claim, characterized in that it comprises means. 9. 9. According to claim 8, the inverting means comprises an exclusive OR gate. equipment. 10. Any of the above, characterized in that the conversion means comprises a circular shift register. Apparatus according to any claim. 11. A plurality of conversion methods are provided, and a computer according to a second conversion method is provided. ・Reload the previously stored data according to the first conversion method into the storage location of the memory. for the first conversion method to generate the second conversion method; Any one of claims 1 to 3 and 5 to 10, characterized in that it is modified. The device described in. 12. The means for reloading the data temporarily holds the data to be reloaded. 12. The device according to claim 11, characterized in that it comprises a temporary buffer for. 13. in a method of managing the storage of data in storage locations in computer memory There it is, receiving from a source input addresses each including a segment; providing a translation scheme for modifying the input address accordingly; The storage of data is uniformly distributed throughout the storage locations of computer memory. periodically modifying the transformation scheme in a predetermined systematic manner such that modifying said input address according to a translation scheme to generate an output address; stages and outputting the output address; method including. 14. A step of periodically modifying the conversion method is carried out after the expiration of a preset period. 14. The method according to claim 13, characterized in that: 15. All input addresses change according to one translation method over a period of time 15. The method according to claim 13 or 14, characterized in that: 16. Each portion includes at least one computer memory location. manages the storage of data in multiple parts of computer memory and the first conversion method converts the computer memory according to the first conversion method. The input address corresponding to the first part of the file is changed, and the second conversion method is the input address corresponding to the second part of the computer memory according to the conversion scheme. 14. The method according to claim 13, characterized in that a plurality of conversion schemes are provided for changing. How to put it on. 17. The computer corresponding to the generated output address. At the memory location, 17. The method according to claim 13, further comprising the step of writing data. Any method described. 18. Features that the source that receives the input address is the central processing unit 18. The method according to any one of claims 13 to 17. 19. The step of modifying the input address includes modifying a selected segment of the input address. 19. The method according to any one of claims 13 to 18, characterized in that the method comprises the step of changing the ment. Method described in Crab. 20. the conversion scheme includes inverting selected segments of the input address; 20. A method according to any of claims 13 to 19, characterized in that: 21. The inversion of the selected segment of said input address is performed using an exclusive OR gate. 21. The method according to claim 20, characterized in that it is carried out by: 22. The storage location of the computer memory according to the second conversion method is stored by the first conversion method. Reloads previously stored data into a storage location in computer memory according to a formula wherein the first conversion method is modified to generate the second conversion method. Any of claims 13 to 15 and 17 to 21, characterized in that The method described in