JPH0748705B2 - Spread spectrum receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a receiver used in a spread spectrum communication system, and more particularly to a peak hold circuit thereof.

B. Outline of the invention In a spread spectrum receiver that uses a correlator to correlate a received signal with a reference signal, obtains a correlation spike, and holds a hold value obtained by peak-holding the correlation spike with a peak hold circuit for reception signal processing. , A / D conversion circuit for A / D converting the correlation spike value, and
A latch circuit that latches the output of the A / D conversion circuit, a comparison circuit that compares the output of the latch circuit with the output of the A / D conversion circuit, and the latch circuit is the output of the comparison circuit. A spread spectrum receiver that obtains the hold value of the peak hold circuit by means of controlling the latch operation of.

C. Conventional technology In the spread spectrum communication system, even if the correlator output fluctuates, it is necessary to follow it and obtain an appropriate threshold signal to detect the target correlation output.

As a conventional system, for example, there is a system shown in JP-A-60-5639, "Reception circuit in spread spectrum communication system".

In this method, the positive and negative correlation spikes of the matched filter output are peak-held by the peak-hold circuit, and then combined, and a threshold signal proportional to this peak-hold value is generated, and the threshold circuit is used. The circuit configuration is shown in FIG. In FIG. 3, 21 is a correlator, 22 is a peak hold circuit, 23 is an arithmetic circuit, 24 is a flip-flop, 25 is a shift clock generator, 26 is a shift circuit, 27 is a PN code, 28 is a delay circuit, 29, Reference numeral 30 is a multiplier, which in this case multiplies by -1 and functions as an inverter. That is, the peak hold circuit 31 holds the positive peak and the peak hold circuit 32
Retains the negative peak. A threshold signal is obtained from the peak value via the variable resistor R ₃ , the comparator 33 detects a positive correlation spike, and the comparator 34 detects a negative correlation spike.

D. Problems to be Solved by the Invention However, this circuit configuration has the following problems. When the peak hold circuit 22 completely peak-holds the correlation spike, the width of the correlation spike is very small.
The time constant due to the internal resistance of the diode D ₁ or D ₂ and the capacitor C ₁ or C ₂ must be made very small. That is, it is necessary to reduce the charging time constant.

On the contrary, when holding this peak value for one cycle of the correlation spike, in order to suppress the decrease of the hold value called droop, the resistance R ₁ or R ₂ and the capacitor C ₁ or
The time constant of C ₂ must be increased. That is, it is necessary to increase the discharge time constant.

With the circuit configuration shown in FIG. 3, the discharge time constant R ₁ C ₁ of the peak hold circuit 31 or 32 is set in setting the threshold signal that fluctuates corresponding to the fluctuating correlation spike φ (t).
Alternatively, it is clear that R ₂ C ₂ must be increased, as shown in FIG.

Next, when considering the follow-up to the fluctuation of the peak value, in the case of a peak-hold circuit having a good hold property, that is, a peak-hold circuit having a large discharge time constant, the follow-up property to the decrease of the peak value becomes poor. This will be described with reference to FIG.

When the correlation spike φ (t) (in this case, the data corresponds to 1,1,0,0,) causing the level fluctuation as shown in FIG. 5 is input to the peak hold circuit 22, The values of the peak hold circuits 31 and 32 are S _{A in} b) and c).
And S _B.

Here, when the correlation spike 2 smaller than the positive correlation spike 1 or the correlation spike 4 smaller than the negative correlation spike 3 is obtained, the capacitor C ₁ or C ₂
Will not be charged and will continue to discharge. That is, when the peak value decreases more than the droop due to the discharge, the peak value cannot be detected. Further, if the threshold signals S _C and S _D are set as shown in FIG. 5a), the correlation spike 1 can be detected, but the correlation spikes 2, 3, 4 cannot be detected.

As a result, the demodulated data d (t) becomes erroneous with respect to the input data. In FIG. 5, d) and e) are the third
The waveforms of S _E and d (t) are shown in the figure, respectively.

An object of the present invention is to provide a peak hold circuit that reliably follows the fluctuation even when the correlator output fluctuates with the fluctuation of the received signal level.

E. Means for Solving the Problems To achieve the above object, the present invention provides a correlator,
A correlation spike is obtained by taking the correlation between the received signal and the reference signal, and the peak value obtained by peak-holding the correlation spike by the peak hold circuit is used for the received signal processing. In the spread spectrum receiver, the correlation spike value is A / D converted. A first latch circuit for storing an output of the A / D conversion circuit, an output of the first latch circuit, and an output of the A / D conversion circuit. And a means for updating the data stored in the first latch circuit according to the output of the comparison circuit and for clearing the data for each period of the correlation spike. The gist is that a second latch circuit that holds the peak value for one cycle of the correlation spike output from the peak hold circuit is provided at the subsequent stage of the peak hold circuit.

F. Examples Hereinafter, the present invention will be described in more detail using examples with reference to the drawings, but they are merely examples, and various modifications and improvements can be made without departing from the scope of the present invention. Of course it is possible.

FIG. 1 is a block diagram showing the configuration of a correlation pulse generating circuit used in a spread spectrum receiver according to the present invention, and FIG.
The drawing is a timing chart of signals in each part of the circuit shown in FIG. In FIG. 1, 1 is a correlator and PDI (Pos
t Detection Integration: Integrating circuit) 2, A / D converter, 3 inverting circuit, 4,5,8,11 latch circuit, 6,7,14,15
Is a comparator circuit, 9 and 10 are gate circuits, 12 and 13 are threshold value setting circuits, and 16 and 17 are digital peak hold circuits.

The A / D converter 2 A / D-converts the correlation spike a based on the sampling signal b to obtain an output c. Here, the result of sampling the period in which the correlation spike a exists is A / D
It is in the shaded area of the output c of the converter 2.

Next, the output c of the A / D converter 2 is branched into the path 1 and the path 2. Path 1 is a path for detecting a positive correlation spike, and path 2 is a path for detecting a negative correlation spike.

The path 2 can be realized with the same circuit configuration as the path 1 by inverting the polarity of the N-bit data of the output c of the A / D converter 2. Therefore, after the A / D converter 2, the path 2 is input to the inverting circuit 3. In the path 2, the circuit configuration of the inverting circuit 3 and the subsequent parts is the same as that of the path 1, so the operation of only the path 1 will be described.

The output c of the A / D converter 2 is the latch circuit 4 and the comparison circuit 6.
Entered in. In the comparison circuit 6, the output c of the A / D converter 2
And the data f stored in the latch circuit 4 are compared,
When it is judged that the data of the output c of the A / D converter 2 is larger, the pulse output d is obtained. Using this pulse d as a trigger, the latch circuit 4 stores the data of the output c of the A / D converter 2 and updates the data f of the latch circuit 4.

In this way, the output c of the A / D converter 2 and the data f of the latch circuit 4 are sequentially compared, and the data f stored by the latch circuit 4 is stored.
To form the digital peak hold circuit 16 for obtaining the maximum value of the output c of the A / D converter 2.

The latch circuit 4 outputs a clear signal e every period of the correlation spike.
The content f stored by is cleared and a peak hold for one cycle of a new correlation spike is performed. The cycle of the pulse of the clear signal e is the same as the cycle of the correlation spike. That is, with the digital peak hold circuit having this circuit configuration, the peak value in one cycle of the correlation spike can be reliably held.

Next, the maximum value of the output c of the A / D converter 2 for one cycle of the correlation spike stored in the latch circuit 4 is cleared by the signal h before the latch circuit 4 is cleared by the clear signal e.
Is stored in the latch circuit 8 as a trigger. Here, when the positive correlation pulse j is input before the pulse of the clear signal e is input, the gate circuit 9 passes the enable signal g and inputs the signal h to the latch circuit 8.

When the positive correlation pulse j does not exist, the gate is closed, nothing is output to the signal h, and the latch circuit 8 does not receive the trigger pulse, so the output i of the latch circuit 8 does not change.

The latch circuit 8 holds the peak value for one cycle of the correlation spike, and due to the presence of the positive correlation pulse, the peak value data for the one cycle of the correlation spike currently held is updated in the next one cycle of the correlation spike. Determine whether to do or not.

By adopting such a configuration, the peak value of the correlation spike can be reliably held within one cycle of the correlation spike a, fluctuations of the peak value can be tracked, and malfunction when the polarity of the correlation spike changes. Can be eliminated.

Next, the output data i of the latch circuit 8 is input to the threshold setting circuit 12. Here, the output data i of the latch circuit 8 and the control signal k representing the multiplication coefficient are calculated to generate the threshold signal l. This threshold signal 1 is an N-bit digital signal. The control signal k is generated by, for example, a CPU or the like.

Next, the threshold signal 1 obtained by the threshold setting circuit 12 is compared with the comparison circuit 14
Entered in. The comparison circuit 14 compares the output c of the A / D converter 2 with the threshold signal l, and when the output c of the A / D converter 2 larger than the threshold signal 1 is input, the output j is obtained. Thus, the correlation pulse j corresponding to the correlation spike is obtained.

Furthermore, as a supplementary note, the digital peak hold circuit 16
By storing the peak value of the output c of the A / D converter 2 within one cycle of the correlation spike obtained in the above in the latch circuit 8, the threshold signal 1 in the next cycle can be set. Even if there is no output c of the A / D converter 2 that exceeds the threshold signal 1 within the one cycle and the correlation pulse j is not obtained, the data i of the latch circuit 8 is still held. The threshold value signal l is set to the same value in the next cycle.

Therefore, as shown in FIG. 2, the digital peak hold circuit 16 within the period in which the negative correlation spike exists.
Although the data f stored in the latch circuit 4 indicates the noise level, as long as the latch circuit 8 holds the peak value of the previous cycle, the comparator circuit 14 does not detect the correlation pulse j by mistake.

Further, the threshold signal 1 for detecting the correlation spike in the next cycle of the negative correlation spike can be set by the output i of the latch circuit 8, and only the correlation spike can be detected.

G. Effect of the Invention As described above, according to the present invention, there is an advantage that an accurate peak hold operation can be performed even when a correlator output fluctuation occurs due to a fluctuation of the input level.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a correlation pulse generating circuit used in a spread spectrum receiver according to the present invention, and FIG.
The figure is a timing chart of signals in each part of the circuit shown in FIG. 1, FIG. 3 is a circuit diagram of a conventional correlation pulse generation circuit, and FIG. 4 is a voltage waveform when the discharge time constant is small and when the discharge time constant is large. FIG. 5 and FIG. 5 are signal waveform diagrams in each part of the circuit shown in FIG. 1 ... Correlator and PDI, 2 ... A / D converter, 3 ... Inversion circuit, 4,5,8,11 ... Latch circuit, 6,7,14,15 ... Comparison circuit, 9,10 ...... Gate circuit, 12,13 …… Threshold setting circuit, 16,
17: Digital peak hold circuit.

Claims (1)

[Claims] 1. A spread spectrum receiver for obtaining a correlation spike by correlating a received signal and a reference signal by a correlator, and using a peak value obtained by peak-holding the correlation spike by a peak hold circuit for receiving signal processing. An A / D conversion circuit for A / D converting the correlation spike value, wherein the peak hold circuit stores a first latch circuit for storing an output of the A / D conversion circuit and an output of the first latch circuit. , A comparison circuit for comparing the output of the A / D conversion circuit and the data stored in the first latch circuit according to the output of the comparison circuit, and the data is cleared at each cycle of the correlation spike. And a second latch circuit for holding the peak value for one cycle of the correlation spike output from the peak hold circuit after the peak hold circuit. Spread spectrum receiver being characterized in that provided.