JPH0746512B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit device, for example, a CMOS (complementary MOS) static RAM (random
The present invention relates to a technique effectively used for a semiconductor memory device configured by incorporating a bipolar transistor in a part of a peripheral circuit of an access memory).

[Background technology]

CMOS-ECL compatible RAM is a CMOS-type RAM (random access memory) that is directly accessed by an ECL (Emitter Coupled Logic) circuit.
L PAPERS), February 1982, pp. 248-249. Also, in order to increase the speed of a CMOS static RAM, one using a bipolar transistor is disclosed in Japanese Patent Laid-Open No.
No. 58193, Nikkei McGraw-Hill, May 21, 1984, “Nikkei Electronic” page 198, etc. As described above, various RAMs in which the CMOS circuit and the bipolar transistor circuit are combined have been proposed.

The applicant of the present application has already developed a RAM which realizes the high speed by incorporating a bipolar transistor in a part of an address buffer, an address decoder and an input / output circuit in order to increase the speed of a CMOS static RAM. This R
In AM, a sense amplifier is composed of a differential amplifier circuit using bipolar transistors for high speed operation. In such a sense amplifier, in order to reduce the current consumption, it was considered to provide a constant current source that forms an operating current with a switch function. In this case, we have developed a circuit that drives a MOSFET that constitutes a constant current source by providing a MOS diode between the output terminal of the CMOS inverter circuit receiving the sense amplifier control signal and the ground potential of the circuit to form a constant voltage. This circuit configures the MOS diode and constant current source when the output signal of the CMOS inverter circuit is high level and the MOS diode is turned on to form a constant voltage, and when the output signal of the CMOS inverter circuit is low level. To turn off the MOSFET. However, when turning on the MOS diode, the CMOS
P-channel MOSFET that composes the inverter circuit and the MO
The disadvantage is that a relatively large DC current flows through the S diode. In this case, in order to reduce the power consumption, the P channel MO that constitutes the CMOS inverter circuit is formed.
Attempting to reduce the direct current supplied from the P-channel MOSFET to the MOS diode by reducing the conductance of the SFET slows down the speed when the sense amplifier is switched from the non-operating state to the operating state. This means that the operation speed is limited, and thus the operation speed is limited. That is, a P-channel MOSFET and an N-channel MOSF that form a MOS diode and a CMOS inverter circuit that drives such a MOS diode.
ET generally has a non-negligible parasitic capacitance such as PN junction capacitance and wiring capacitance due to its structure. Since the N-channel MOSFET that constitutes the CMOS inverter circuit is turned on, the voltage between the terminals of the MOS diode is substantially zero, that is, the sense amplifier is deactivated and the sense amplifier is activated. When the state of the CMOS inverter circuit is inverted as shown in FIG.
The ET changes from the OFF state to the ON state, and the above-mentioned parasitic capacitance that was previously discharged by the N-channel MOSFET is the P-channel MOSFET that has changed to the ON state.
Will start to be charged. In this case, if the conductance of the P-channel MOSFET is made small so as to make the direct current small as described above, the charging of the parasitic capacitance is correspondingly performed at a relatively slow speed. As a result, even if the P-channel MOSFET is changed to the ON state, it takes time until the bias voltage of a sufficient level starts to appear in the MOS diode, and the speed from the non-operating state to the operating state of the sense amplifier. Will be greatly limited. In order to increase the speed of change of the sense amplifier to the operating state, it is unavoidable to increase the conductance of the P-channel MOSFET that supplies the DC current to the MOS diode. In that case, naturally, a large DC current is consumed. Become.

[Object of the Invention]

An object of the present invention is to provide a semiconductor integrated circuit device that achieves high speed operation and low power consumption.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, a constant voltage formed by a diode type MOSFET and a diode type bipolar transistor formed in series is output via an emitter follower output transistor, and a constant current source is selectively configured via a transmission gate MOSFET. It supplies to each of a plurality of MOSFETs.

〔Example〕

FIG. 1 shows a static RAM to which the present invention is applied.
A block diagram of is shown. In the figure, the storage capacity is about
It shows the internal structure of a 64-Kbit RAM with a 4-bit output. In the figure, each circuit portion surrounded by a broken line is formed on a semiconductor substrate such as a single crystal silicon by a semiconductor integrated circuit technique.

The static RAM of this embodiment has four matrices (memory arrays M-ARY1 to M-ARY4) each having a storage capacity of 128 columns (rows) x 128 rows (columns) = 16384 bits (about 16 Kbits). Have a total of about 64
It has a storage capacity of K bits. An address circuit for selecting a desired memory cell MC from each of the memory arrays M-ARY1 to M-ARY4 having a plurality of memory cells MC includes an address buffer ADB, a row address decoder R-DCR, and a column address decoder C-. DCR, column switches C-SW1 to C-SW4, etc.

Although not shown, the memory cells MC have the same configuration as each other and are not particularly limited.
A pair of N-channel storage MOSFETs whose drains are cross-connected to each other, information holding resistors respectively provided in the drains, the storage MOSFETs and a pair of complementary data lines D,
And N channel transmission gates MO provided between
It is composed of SFET and. The memory cell MC holds the stored information by supplying the power supply voltage Vcc to the connection point of the resistor. The resistance is set to a high resistance value of, for example, several megohms to several gigaohms in order to reduce the power consumption of the memory cell MC in the state where the stored information is held. In addition, since the resistance reduces the area occupied by the memory cell, for example, a polysilicon layer having a relatively high resistance formed on the surface of the semiconductor substrate forming the MOSFET via a field insulating film having a relatively large thickness. Composed of.

The signal circuit for handling reading / writing of information is not particularly limited, but includes data input circuits DIB1 to DIB4, data output circuits DOB to DOB4, and sense amplifiers SA1 to SA16.

The timing circuit for controlling the read / write operation of information is composed of an internal control signal generation circuit COM-GE and a sense amplifier selection circuit GS, although not particularly limited.

The row decoder R-DCR sends 128 kinds of decode output signals obtained based on the address signals A0 to A6 to the row address selection lines (word lines W1 to W128). This decode output signal is not particularly limited, but it is arranged on the left and right with the row address decoder R-DCR as the center.
It is commonly supplied to the word lines W1 to W128 of the memory arrays M-ARY1 and M-ARY2 and the memory arrays M-ARY3 and M-ARY4, respectively.

Address signals are connected to the column address selection lines Y1 to Y128.
The 128 decoded output signals obtained based on A7 to A13 are sent from the column decoder C-DCR. This decode output signal is not particularly limited, but is common to two column switches C-SW1, C-SW2.C-SW3, C-SW4 arranged on the left and right with the column address decoder C-DCR as the center. Is supplied to.

The address buffer ADB receives an address signal A0~A13 supplied from an external terminal, forming an internal complementary address signal a 0 to a 13 based on this. The internal complementary address signal a 0 is configured with the internal address signals a0 of the address signals A0 and phase, and the internal address signal 0 that is phase-inverted with respect to the address signals A0 through. Similarly, the remaining interior complementary address signal a 0 to a 13, constituted by the internal address signal a1~a13 and phase-inverted internal address signals 1-13-phase.

Of the internal complementary address signal a 0 to a 13, which is formed by the address buffer ADB, is not particularly limited, the internal complementary address signal a. 7 to a 13 are supplied to the column address decoder C-DCR. Column address decoder C-D
CR is decipher these internal complementary address signal a. 7 to a 13 to (decoding), and the resulting selection signal by decoding (decode output signal), the column switch C-SW1~C
-Supply to the gates of switch MOSFETs (insulated gate field effect transistors) Q6, Q6 to Q7, Q7, etc. in SW4.

Word line W1 in each memory array M-ARY1 to M-ARY4
Among W128 to W128, one word line designated by a combination of external address signals A0 to A6 is selected by the row address decoder R-DCR described above, and one word line from the outside is selected by the column address decoder C-DCR described above. A pair of complementary data lines designated by a combination of address signals A7 to A13 is selected from 128 pairs of complementary data lines. As a result, in each of the memory arrays M-ARY1 to M-ARY4, 1 is arranged at each intersection of the selected word line and the selected complementary data line.
The memory cells MC are selected.

The storage information read from the selected memory cell MC is the four pairs of sub-common complementary data lines CD1, ▲ ▼ 1 to CD.
Appears in one of 4, ▲ ▼ 4. That is, the sub-common complementary data lines CD1, ▲ ▼ 1 to CD4, ▲ ▼ 4 are
Like the memory array M-ARY1 shown as a representative, 12
Eight pairs of complementary data lines correspond to the memory blocks M1 to M4 divided into 32 pairs. Sense amplifiers SA1 to SA4
Is the divided sub-common complementary data line CD1, ▲ above
It is provided for each of ▼ 1 to CD4 and ▲ ▼ 4.

In this way, sub-common complementary data lines CD1, ▲ ▼ 1 to CD4,
{Circle around (4)} The purpose of providing the sense amplifiers SA1 to SA4 in each is to divide (reduce) the parasitic capacitance of the common complementary data line to speed up the information read operation from the memory cell.

The sense amplifier selection circuit GS uses the above address signals A12 and A13.
On the basis of 4 to decode the sense amplifier selection signals m1 to 4m. The above four sense amplifiers SA1 to SA4
Of the (SA5 to SA8, SA9 to SA12, and SA13 to SA16), one sense amplifier corresponding to the complementary data line selected by the column switch is activated by the selection signals m1 to m4 and the timing signal sac. Transmit the output to the common complementary data line CDL, ▲ ▼.

The common complementary data line CDL, ▲ ▼ is coupled to the input terminal of the data output circuit DOB and the output terminal of the data input circuit DIB. In the write operation, the divided sub-common complementary data lines CD1, ▲ ▼ 1 to CD4, ▲
▼ 4 is a transmission gate MOSF that receives the write control signal we
Shorted by ETQ1,1 to Q5,5.

The internal control signal generation circuit COM-GS receives the two external control signals ▲ ▼ (chip select signal) and ▲ ▼ (write enable signal) to receive the internal chip selection signals cs1 and sac.
(Sense amplifier operation timing signal), we (write control signal), dic (data input control signal), ▲ ▼ (data output control signal), etc. are transmitted.

FIG. 2 shows a circuit diagram of one embodiment of the sense amplifier SA and the data output circuit DOB. In the figure, the MOSFET Q11 having a straight line on the channel part is a P-channel M
It is an OSFET and is distinguished from the N-channel MOSFET Q10.

A sense amplifier SA1 shown as a representative is provided between a differential bipolar transistor T1, T2 whose base is coupled to the corresponding sub-common complementary data line CD1, ▲ ▼ 1, and its common emitter and the ground potential point of the circuit. It is constituted by an N-channel MOSFET Q10 which constitutes a constant current source provided. The sense amplifier SA4 shown as another representative is also a differential bipolar transistor T3, T4 whose base is similarly coupled to the corresponding sub-common complementary data line CD4, ▲ ▼ 4.
And an N-channel MOSFET Q13 forming a constant current source provided between the common emitter and the ground potential point of the circuit. These differential transistors T1, T2 and T
3, T4 collector is common complementary data line CDL, ▲ ▼
Respectively combined with. Although not shown, the collectors of the differential transistors forming the remaining two similar sense amplifiers are also commonly connected to the common complementary data line CDL ,.

The output signal of the sense amplifier appearing on the above common complementary data line CDL, ▲ ▼ is the first stage circuit PDO of the data output circuit DOB.
Is amplified to an output signal such as almost ECL (emitter coupled logic). The common complementary data line CDL, ▲ ▼ is a grounded base amplification transistor.
It is coupled to the emitters of T7 and T8. These transistors T
A bias voltage (Vcc-2Vf) formed by the diodes D1 and D2 and the MOSFET Q23 as a constant current source for flowing the operating current is supplied to the bases of the transistors 7, T8. Note that Vf is the forward voltage of the diodes D1 and D2. Above transistor T
Between the emitters of 7, T8 and the ground potential point of the circuit, MOSFETs Q22, Q24 as constant current sources for flowing the bias current are provided. Load resistors R1 and R2 are provided at the collectors of the transistors T7 and T8. The collector outputs of the base-grounded amplification transistors T7 and T8 are transmitted to the next output circuit OB via the emitter follower output transistors T9 and T10 and the level shift diodes D3 and D4. MOSFETs Q25 and Q26 as constant current loads are provided at the emitters of the output transistors T9 and T10.

MOSFETs Q10, Q13 and Q22 to Q2 that make up the above constant current sources
The constant voltage 5 is formed by the next constant voltage circuit, and is selectively operated by the selection circuit. That is, the bipolar NPN transistor T5 formed in a diode form by connecting the base and collector in common.
And its gate and drain are connected in common to form a diode type N-channel MOSFET Q20 in series. A bias current is supplied to the series circuit through a P-channel MOSFET Q19 that equivalently acts as a resistance element when the ground potential of the circuit is constantly applied to its gate. This allows MOSFET Q1
From the drain of 0, the threshold voltage Vth of the MOSFET Q10 and the base-emitter voltage Vb of the bipolar transistor T5
A constant voltage according to e is formed. This constant voltage is sent out through the emitter follower output circuit formed by the bipolar NPN transistor T6. The gate of the transistor T6 has a power supply voltage Vcc.
Is constantly supplied, an N-channel MOSFET Q21 equivalently acting as a resistance is provided as a load. The P-channel MOSFET Q19 is adapted to carry the minimum small current required to drive the emitter follower output transistor T6. Further, the N-channel MOSFET Q21 is not particularly required,
Even when the selection circuit is selected, there is no constant current flowing out from the constant voltage circuit (all the outputs of the constant voltage circuit enter the gate). A small amount of current flows to prevent the transistor T6 from being turned off due to the output constant voltage being raised for some reason.

In the constant voltage circuit configured as described above, the base-emitter voltage of the diode-type transistor T5 and the base-emitter voltage of the emitter-follower output transistor T6 cancel each other out, so that the threshold voltage Vth of the MOSFET Q20 is almost obeyed. A constant voltage can be generated. Further, this makes it possible to compensate for the process variations and temperature characteristics of the output transistor T6.

The output constant voltage is transmitted to the gates of the MOSFETs forming the respective constant current sources via the transmission gate MOSFETs Q12, Q15 and Q18. For example, to describe the sense amplifier SA1, the constant voltage is supplied to the gate of the MOSFET Q10 that constitutes a constant current source via the transmission gate MOSFET Q12.
The gate of the transmission gate MOSFET Q12 has a select signal m1 for the sense amplifier and an operation timing signal for the sense amplifier.
A control signal according to the logical product of sac is supplied. Further, in order to quickly deactivate the sense amplifier SA1, an N-channel switch MOSFET Q11 is provided between the gate of the MOSFET Q10 that constitutes the constant current source and the ground potential of the circuit, and a CMOS inverter is provided at its gate. The control signal inverted by the circuit IV1 is supplied. As a result, the transmission gate MOSFET Q12 and the switch MOSFET Q11 can be complementarily controlled, so that the constant current source MOSFET Q10 is switched between operation and non-operation at high speed.

The constant voltage is selectively supplied to the gates of the MOSFETs Q13 and Q22 to Q26 that form other constant current sources by a similar selection circuit. The constant voltage source MOSFETs Q22 to Q26 of the first-stage circuit P22 are provided with a constant voltage by a common selection circuit, but the invention is not limited to this, and each independent selection circuit or these MOSFETs can be provided in multiple sets. It may be divided and provided with a common selection circuit.

The output circuit OB is selectively activated by a power switch MOSFET, and realizes a level conversion function and an output enable function by a differential amplifier circuit having a current mirror type active load circuit. That is, the first stage circuit
On the one hand, the ECL level complementary signal formed by PDO is supplied to the gates of P-channel type differential amplification MOSFETs Q28 and Q29. A P-channel type power switch MOSFET Q27 that receives an operation timing signal {circle around ()} is provided between the common source power supply voltage Vcc of the differential amplification MOSFETs Q28 and Q29. Differential amplification MOSFET Q above
Between the drains of 28 and Q29 and the ground potential point of the circuit, an N-channel active load MO in the form of a current mirror is formed.
SFETQ31 is provided. An N-channel MOSFET Q34 that receives the control signal {circle around (3)} is provided between the common drains of the MOSFETs Q29 and Q31 which are the outputs of the differential amplifier circuit and the ground potential point of the circuit.

On the other hand, the ECL level complementary signals are supplied in anti-phase to the inputs of the similar differential amplifier circuits (Q35 to Q40).

In the above two sets of differential amplification circuits, if the control signal ▲ ▼ is low level, the power switch MOSFETs Q27 and Q35 are turned on and the operating currents are supplied to the two differential amplification circuits. The circuits are CMOS with opposite phases
A level output signal is obtained. On the other hand, control signal ▲
If ▼ is high level, the power switch MOSFETs Q27 and Q35 are turned off, so that the two differential amplifier circuits are both deactivated. In this case, since the N-channel MOSFETs Q34 and Q40 are both turned on by the high level of the control signal {circle around (1)}, both output signals of low level are obtained.

The output signals of the above two sets of differential amplifier circuits are not particularly limited, but the base of the emitter follower output transistor T11 composed of a bipolar NPN transistor for sending a high level output signal to the external terminal Dout, and the external terminal D.
It is transmitted to the gate of the N-channel output MOSFET Q41 which outputs a low level output signal to out. In order to set the output signal sent to the external terminal Dout to the TTL level, the emitter of the transistor T11 is provided with a level shift diode D5.

An outline of the read operation of the static RAM will be described below with reference to FIG.

All the operations in this MOS static RAM, that is, the address setting operation, the read operation, and the write operation are performed only while one external control signal ▲ ▼ is at the low level. At this time, if the other external control signal ▲ ▼ is high level, a read operation is performed, and if it is low level, a write operation is performed.

The address setting operation is always performed based on the address signal applied during this period when the external control signal ▲ ▼ is low level. On the contrary, by setting the external control signal ▲ ▼ to the high level, it is possible to prevent the address setting operation and the read operation based on the uncertain address signal.

When the external control signal {circle over ()} becomes low level, the row decoder R-DCR receives the high level internal control signal cs1 synchronized with this signal and starts its operation. The row decoder (also word driver) R-DCR decodes seven kinds of complementary address signals a 0 to a 6 and selects one word line,
Set this to high level. The column decoder C-DCR is
Similarly to the above, the operation is started upon receiving the high level internal control signal cs1. The column decoder C-DCR is a selection signal for complementary data lines of a pair to decrypt the seven complementary address signal a. 7 to a 13 to a high level.

In this way, one memory cell is selected (address setting) in each of the memory arrays M-ARY1 to M-ARY4.

The information of the memory cell selected by the address setting operation is sent to one of the divided sub-common complementary data lines and amplified by the sense amplifier. In this case, regarding the memory array M-ARY1, the four sense amplifiers SA
Any one of 1 to SA4 is selected by the memory array selection signals m1 to m4, and only one selected sense amplifier operates while receiving the high level internal control signal sac. In this way, the four sense amplifiers SA1
Low power consumption can be achieved by setting the remaining three sense amplifiers, which are unnecessary to use, among SA4 to SA4. The outputs of the three sense amplifiers in the non-operating state are in a high impedance (floating) state.

The output signal of the sense amplifier is amplified by the data output circuit DOB and sent as output data Dout to the outside of the IC.

In the data output circuit DOB, when the chip selection signal ▲ ▼ of the first stage circuit PDO is set to the low level, the internal chip selection signal cs is set to the high level and the constant current source MOSFETs
When Q22 to Q26 are put into the operating state, the output circuit OB is set to the operating state and the low-level control output ▲
Operates while receiving ▼. That is, when the control signal ▲ ▼ is low level, the P channel MOSFETs Q27, Q35 of the differential amplifier circuit are turned on and the N channel MOS is turned on.
FETs Q34 and Q40 are turned off. As a result, a high level (power supply voltage Vcc level) and a low level (ground potential of the circuit) of the CMOS level are obtained at the outputs of the two sets of differential amplifier circuits. Now, when a high-level amplified output is supplied to the base of the transistor T11, an opposite low level is supplied to the gate of the MOSFET Q41, so that the transistor T11 is turned on, the MOSFET Q41 is turned off, and the output terminal D
A TTL high level output signal such as a power supply voltage Vcc-2Vf is sent to out (where 2Vf is the base-emitter voltage of the transistor T11 and the forward voltage of the diode D5). Further, when a low-level amplified output is supplied to the base of the transistor T11, a reverse-phase high level is supplied to the gate of the MOSFET Q41, so that the transistor T11 is turned off and the MOSFET Q41 is turned on. D
A low level output signal such as the ground potential of the circuit is sent to out.

If the control signal ▲ ▼ is high level, the P channel MOSFETs Q27 and Q35 of the differential amplifier circuit are turned off,
N-channel MOSFETs Q34 and Q40 are turned on. As a result, both amplified output signals are set to the low level, so that both the transistor T11 and the MOSFET Q41 are turned off, and the output terminal Dout is set to the high impedance state.

In the write operation, when the external control signal ▲ ▼ becomes low level, the synchronized high level control signal we is used to divide the sub-common complementary data line shown in FIG.
It is supplied to the MOSFETs (Q1, 1; ...; Q5, 5) and commonly coupled to the common complementary data line CDL, ▲ ▼. On the other hand, the data input circuit DIB amplifies the input data signal Din from the outside while receiving the control signal dic, and sends it to the common complementary data line pair CDL, ▲ ▼ which is commonly coupled. The input data signal on the common complementary data line pair CDL, ▲ ▼ is written in the memory cell MC determined by the address setting operation.

[Effect]

(1) An output constant voltage is formed via an emitter follower output transistor composed of a bipolar type transistor which operates by receiving a constant voltage by a diode type MOSFET and a diode type bipolar transistor, and via a transmission gate MOSFET. Selectively drives the constant current source MOSFET. As a result, a relatively large steady-state direct current does not flow in the emitter follower output transistor, so that it is possible to achieve the effect of achieving constant power consumption. That is, P channel MOSF
The CMOS inverter circuit itself with a reduced ET conductance limits the DC current supplied to the MOS diode, and the DC current itself must be relatively large, unlike the case where the operating speed cannot be increased, and the steady state is maintained. By using the constant voltage circuit using the bipolar transistor, which can sufficiently reduce the output impedance even if the dynamic operating current is sufficiently reduced, it becomes possible to obtain the characteristics of low power consumption and high speed.

(2) Since the constant voltage is output via the emitter follower output transistor, the driving current can be made relatively large, so that the constant current source MOSFET can be operated at high speed. As a result, an effect that high speed operation can be achieved is obtained.

Although the invention made by the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention. Absent. For example, a diode-type MOSFET that forms a constant voltage to be supplied to the base of the emitter follower output transistor may be arranged on the ground potential side of the circuit. In addition, the constant voltage is the constant current source MOSFET
The transmission gate MOSFET that is selectively supplied to the gate of may be a P-channel MOSFET. In this case, since the control signal is controlled by the control signal having a level opposite to that of the above-described embodiment, the inverter circuit can be omitted and the control signal can be directly supplied to the gate of the N-channel type switch MOSFET.

[Field of application]

The present invention is a constant current source MOSFET having a plurality of switch functions.
It can be widely used for a semiconductor integrated circuit device having a.

[Brief description of drawings]

FIG. 1 shows a static type RA showing an embodiment of the present invention.
FIG. 2 is a block diagram of M, and FIG. 2 is a circuit diagram showing an embodiment of the sense amplifier and the data output circuit. M-ARY1 to M-ARY4 ... Memory array (memory matrix), MC ... Memory cell, GS ... Sense amplifier selection circuit, C-DCR ... Column address decoder, SA1 to SA16 ...
... sense amplifier, COM-GE ... internal control signal generation circuit,
R-DCR: Row address decoder, ADB: Address buffer, C-SW1 to C-SW4: Column switch, DIB1 to
DIB4 …… Data input circuit, DOB1 to DOB4 …… Data output circuit

 ─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-57-198594 (JP, A) JP-A-60-28096 (JP, A) JP-A-58-70482 (JP, A)

Claims (3)

[Claims] 1. A diode type MOSFET arranged in series.
And a diode type bipolar transistor, and
An emitter follower output transistor that receives a constant voltage formed by a MOSFET and a bipolar transistor,
A semiconductor integrated circuit device comprising: a plurality of MOSFETs constituting a constant current source to which a constant voltage obtained from the emitter of the output transistor is selectively supplied via a transmission gate MOSFET. 2. A switch MOSFET operating complementarily to the transmission gate MOSFET is provided between the gate of the MOSFET constituting the constant current source and the ground potential of the circuit. The semiconductor integrated circuit device according to claim 1. 3. A plurality of MOSFETs constituting the constant current source,
It is used as a constant current source provided in the common emitter of a bipolar differential amplification transistor which constitutes a plurality of sense amplifiers in a static RAM constructed by combining a CMOS circuit and a bipolar transistor. The semiconductor integrated circuit device according to claim 2, wherein