JPH0746479B2 - Code converter - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code conversion device for obtaining a Run Lenght Limited (DC free RLL) code which does not contain a DC component, which is used when recording a digital signal.

2. Description of the Related Art When recording / reproducing a digital signal through a transmission line showing a DC component cutoff characteristic by a rotary transformer such as a digital VTR, it is desirable to use a DC free code that does not include a DC component in the recording code itself. .

Furthermore, it is desired to use an RLL code that limits the number of consecutive bits of the same binary value to d or more and k or less.

Normally, a DC-free RLL code is obtained by converting an m-bit data word into an n-bit code word that is larger than m. Letting 1 bit length of the data word be T, the 1-bit length of the code word is Becomes

Therefore, the minimum inversion interval T _min = d · T _{ω of the} binary value in the DC-free RLL code.

By the way, regarding the bit error rate in the reproduced signal, in order to reduce the influence of the high frequency component cutoff characteristic of the transmission line, T
_min is large, and T _{ω is set} in order to reduce the influence of fluctuations on the time axis such as peak shift and jitter during playback.
Is large, and it is desirable that k is small from the viewpoint of easily obtaining the self-clocking function.

Conventionally, various DC-free RLL codes have been developed from the above viewpoint, and the 4/8 conversion code (Japanese Patent Laid-Open No. 57-195308) is one example.

The 4/8 conversion code has, for example, d = 2, k = 9, m = 4, n in the above definition.
= 8, T _ω = 0.5T, DC-free RLL code, m = 4
By converting a data word of bits to a code word of n = 8 bits, the number of consecutive bits of the same binary value is limited to 2 or more and 9 or less in the bit string generated by the connection between the converted 8-bit code words. At the same time, this bit string does not include a DC component.

In general, a DC-free code that does not include a DC component refers to a code that has the following properties.

[DC-free code]: In a bit string generated by connecting code words, a DSV that is constant with the difference between the number of 1s and 0s from the beginning of the bit string to any bit in the bit string
(Digital Sum Variation) is always finite.

With respect to the code of n2, the DSV cannot be controlled in bit units, so normally, the control is performed in code word units and the DSV is kept finite.

That is, the DSV value DSV ₁ at the last bit of the immediately preceding codeword
On the other hand, as a code word to be transmitted from now on, a code word having a disparity DP (a difference in the number of 1s and 0s in the code word) having a polarity opposite to that of DSV ₁ is selectively used.

By doing this, the DSV will never diverge and will always be finite.

Not only the 4/8 conversion code, but most of the conventional DC-free RLL codes of n2 are codewords (table pattern) Z starting from 1 and 1 of the codewords of the table pattern for the codeword of DP = 0.
And a code word of the reverse pattern in which 0, 0 and 1 are all inverted are paired to correspond to one data word.

Since DP = 0, the DSV does not increase in codeword units, and therefore the front pattern and the back pattern are selectively used so as to satisfy the d, k restriction.

For a code word of DP ≠ 0, four words of a code pattern α and β of a front pattern starting with both DP> 0 and DP <0 and a back pattern of the code words α and β are paired, and d, These four words are selectively used to meet the k and DSV constraints.

As described above, the conventional DC-free RLL code satisfies the d, k restriction and the DSV restriction. For example, in addition to the 4/8 conversion code, a 9/16 conversion code with d = 2 (Japanese Patent Laid-Open No. 57-57 (1988)). DC-free RLL codes such as −195308) have been obtained.

In the 9/16 conversion code, the number of bits in the data word is m
= 9, the number of bits of the codeword n = 16, and therefore T _ω = _9/16
T0.56T is, can to a large than 4/8 conversion code T ω = _0.5T.

Here, FIG. 15 shows a block diagram of a circuit for generating a conventional DC-free RLL code.

The circuit shown in FIG. 15 is an n-bit code word corresponding to an m-bit data word from a serial-parallel converter (S / P) 50, which generates an m-bit parallel data word from a data string. ROM (Read Only Memory) 51 that generates α
And a ROM 52 that generates an n-bit code word β having a disparity different from that of the code word α, and the back patterns of the code words α and β and the code words α and β obtained by inverting the code words α and β and 0 and 1, respectively. , And one of these four words α, β, so as to satisfy the d, k, DSV restrictions, and the control selection circuit 53 for converting this code word into serial and sending it out.

Each of the ROMs 51 and 52 in FIG. 15 has an address of m bits and an output of n bits. Therefore, the capacity of each ROM is V _E = 2 ^n.
・ It becomes m bits.

The disparity DP appears in the output of ROM51.
In the case of the code word Z of = 0, no meaningful code word appears in the output of the ROM 52.

On the other hand, FIG. 16 shows a block diagram of a circuit configuration for decoding the serial code word thus obtained into a data word.

In FIG. 16, a serial-parallel converter (S / P) 54
Converts a serial code word to n-bit parallel and RO
The M55 decodes the m-bit data word corresponding to this bit-parallel code word. Therefore, ROM55 capacity V _D = 2
^{There are n} · m bits.

Problems to be Solved by the Invention The DC-free RLL code can be configured as described above, and further,
According to a codeword length n to large, it can be Yuku to expand the T _ω. For example, for d = 2, n = 20, m = 12 (T
_ω = 0.6T), d = 2, n = 24, m = 15 (T _ω = 0.625
T) DC-free RLL code is obtained.

However, if the codeword length n is further increased in order to increase T _ω , the capacities of the ROMs 51 and 52 in FIG. 15 and the ROM 55 in FIG. 16 increase, especially the capacity of the ROM 55 increases exponentially. If the code word length reaches 30 bits, the memory capacity required for the ROM 55 is V _D = 20 ³⁰ · mm × 10 ⁹ =
It will become m-gigabit, and the circuit scale becomes unrealistic.

Conversely, as long as the conventional DC-free RLL code is used, for example, There is a problem that a huge amount of memory is required to realize.

Further, when n is an odd number, there is no code word with DP = 0, so in the conventional DC-free RLL code, one code word must be associated with four code words (the above α, β). However, it is more disadvantageous than when n is an even number.

Therefore, a DC-free RLL code in which n is an odd number is rarely used, which is a large constraint on the degree of freedom in selecting a codeword length, which is a problem to be overcome.

The object of the present invention is to solve the problems of the above-mentioned conventional example,
DC-free RLL suitable for higher density recording than DC-free RLL code
It is an object of the present invention to provide a code conversion device that realizes a code with a realistic circuit scale.

A first feature of the present invention is to convert an m-bit data word into an n-bit code word, and to convert the same binary value in a bit string generated by connecting the converted code words. In a code conversion device that limits the number of consecutive bits to d or more and k or less, and keeps the number difference DSV of "1" and "0" in the bit string finite, inputs an m-bit data word and connects the code word Output an n-bit codeword so that consecutive bits of the same binary value in the bit string obtained by
Difference between the number of "1" and "0" in the code word group consisting of n code conversion means and the continuous g output of the m / n code conversion means
The group disparity calculating means for calculating GDP, the digital sum variation calculating means for cumulatively calculating the output of the group disparity calculating means, and the polarity of the output of the group disparity calculating means added to the digital sum variation calculating means are "1" in the code word group is set to "0" in accordance with the group disparity polarity control means for controlling the polarity to be different from the output polarity of the digital sum variation calculation means and the polarity selected by the group disparity polarity control means. ",
And a codeword group inversion control means for controlling whether or not all “0” s are inverted to “1” s.

A second feature of the present invention is that, in place of the m / n code conversion means in the first feature of the present invention, an m-bit data word is input and the same 2 in a bit string obtained by connecting the code words is input. M / n code conversion means for outputting an n-bit codeword so that the number of consecutive bits of the base value is not less than d and not more than k is provided, and in addition to the first feature of the present invention, the preceding code When the last codeword of the word group and the first codeword of the current codeword group are connected, and the consecutive bits of the same binary value in the bit string are not d or more and k or less, the preceding codeword group That is, a code word replacing unit that replaces the last code word with another code word is provided.

Furthermore, the third feature of the present invention is that, in addition to the above first and second features, each of the g code words forming the controlled code word group appearing at the output of the code word replacing means is divided into a plurality of parts. Then, the temporary decoding means for outputting a value capable of distinguishing the bit patterns of the divided parts from each other, and the final decoding means for decoding the data word corresponding to each of the g code words based on the output value of the temporary decoding means. And to prepare.

Operation The first feature of the present invention is equivalent to dividing and generating the code word in the DC free code. That is, conventional DC
The code word in the free code corresponds to a code word group (hereinafter simply referred to as a group) made up of g code words of the present invention. Therefore, in either conversion of data words to code words or conversion of code words to data words,
The smallest unit is a codeword, not a group. As a result, it is possible to prevent the memory capacity from increasing even if the group length becomes large.

A second feature of the present invention is that, like the first feature, the DC-free code is divided and generated to prevent an increase in the memory capacity.
It is a DC-free RLL code that is limited to k or less. Therefore, higher density digital signal recording is possible.

With the provisional decoding means according to the third aspect of the present invention, the number of bits required to identify an n-bit codeword can be used in common with a value smaller than n, and the first aspect of the present invention is introduced. You can prevent the unnecessary memory capacity from increasing.

Hereinafter, each of the three features of the present invention will be described in detail using examples.

Example 1 This example relates to the first and second features of the present invention.

In the group structure of the present invention shown in FIG. 2, C _i (i
= 1,2, ..., g) represents the RLL code satisfying the same d and k restrictions, and n _i represents the number of bits of the RLL code C _i .

That is, the group in the present invention is composed of g RLL codes, and the group bit number Becomes

Here, CW _i is the code word DW _i forming the RLL code C _i , the data word corresponding to CW _i , m _i is the number of bits of DW _i , If defined as, T _ω / T = m ′ / n ′ in this case.

The condition required for the RLL code C _i in FIG. 2 is that even in the bit string generated by connecting the CW _i and CW _{i + 1} (i = 1, ... It only satisfies the d, k constraint, except.

That is, regardless of what encoding rule the RLL code C _i was obtained with, regarding the group obtained by sequentially concatenating the RLL codes C _{1 to} C _g , except for the start end and the end thereof, d, It suffices if the k limit is satisfied.

Regarding the start end and the end, even if the d limit is not satisfied, the d limit may be satisfied by connecting the groups. It should be noted that violation of the k limit is not allowed at the beginning and the end.

In this way, the group G controlled to satisfy the d, k constraint
G1 for the connection between 2 and the group G1 preceding G2
The value of DSV at the last bit of is set to G2 so that the polarity S _n2 of the group disparity GDP ₂ defined by the number difference between “1” and “0” in group G2 is different from the polarity S _{n1 of} DSV _1. Control.

That is, when S _n1 ≠ S _n2 , G2 is used as it is, and S _n1 = S
_{When n2} , set “1” to “0” for all bits in G2,
Invert “0” to “1”. By doing this, G2 after reversal
The polarity of GDP ₂ at −S _n2 is S _n1 ≠ S _n2 .

If DSV ₁ = 0 or GDP ₂ = 0, DSV control is carried over to the next group. In these cases,
G2 may or may not be inverted, but it is not inverted in this embodiment.

By defining as described above, the DSV becomes DC-free without continuously increasing in the diverging direction.

On the other hand, when connecting the group G2 controlled to meet the DSV restriction to the group G1,
Violations of d, k restrictions may occur.

In such a case, the final codeword CW _g of G1 is replaced. That is, in FIG. 3 showing the connection between groups, in the connection between the last codeword CW _g of G1 and the _first codeword CW ₁ of G2 that is controlled to satisfy the DSV restriction, If is not satisfied, replace CW _g .

For example, in the case of d = 2, when a d restriction violation occurs as shown in FIG. 4 (a), if CW _g is selected and replaced with a code word having a final bit different from that in the case of FIG. 4 (a), The d limit is satisfied as shown in FIG. The same applies to the k limit.

In this way, by combining codewords ending with “0” and codewords ending with “1” as CW _g, it is possible to satisfy the d, k restriction even if groups are connected.

Hereinafter, an example where d = 2, k = 12, and the number of bits n _i of the g RLL code are all 22, will be described in detail.

First, the RLL code used in this embodiment.

In order to classify the codewords CW that make up the RLL code in this embodiment, parameters that show the characteristics of the codewords as shown in FIG. 5 are introduced. In other words, assuming that the number of bits of the code word is n, L block: a start end portion where 1-bit same binary value TB continues, R block: end portion where r-bit same binary value LB continues, B block: b (= It is an intermediate part consisting of (n-1r) bits.

The code word CW in the case of d = 2 and k = 12 is limited to those satisfying the following conditions.

(I) 111,1r11 (ii) The B block completely satisfies the d, k constraint.

The above (ii) indicates that "0" and "1" of d bits or more and k bits or less continue alternately in the B block (b = 0.
except for).

Furthermore, the following parameters F and E are introduced for l and r.

F = 0 (l = 1), F = 1 (2l6), F = 2 (7l
11) E = 0 (r = 1), E = 1 (2r6), F = 2 (7r
11) The connection between the code words is controlled based on the four parameters (TB, F, E, LB) defined as described above. This control is based on the first code word W1 shown in FIG. And the second code word W2
It means that the connection between the R block of W1 and the L block of W2 also satisfies the d, k restriction.

Below, the rule regarding the connection of these codewords is called the connection rule.

In the RLL code in this embodiment, the combination of code words is defined by using the four parameters (TB, F, E, LB), and Table 1 shows RLL code C _i (i = 2 in FIG. 2). , ~, G
-1), Table 2 shows RLL code C ₁ and 3 in FIG.
The table relates to the RLL code C _{g in} FIG. RLL code
Only C _g requires restrictions on disparity DP.

In Tables 1 to 3, "CW-No." Is a combination number of code words and an identification number of code words forming the combination, and the same data word corresponds to the code words forming one combination. Let (DP, TB, F, E, LB) is a parameter related to the codeword,
The "x" mark indicates irrelevant, and A indicates the same value within one combination. Further, "EXAMPLE" indicates an example of the code word that can be represented by the parameter.

Further, "WORD" is a rewriting of "CW-No." To make the structure of the code word easy to understand, and the values of F, E, and LB are added to "CW". In addition, "-" means a back pattern.

For example, CW210 is a code word of a front pattern (starting with "1") where F = 2, E = 1, and LB = 0, and ▲ ▼ is a back pattern of CW210.

Hereinafter, Tables 1 to 3 will be described.

[Explanation of Table 1] The combination of code words shown in Table 1 is RL in FIG.
The L code C _i (i = 2, 3, ..., G-1) is common and is combined as follows.

(1.1) Code word CW (F, E, F = 1, E ≠ 1, TB = 1, LB = 1
1) is the back pattern of CW (F, E, 1) And CW (F, E, 1) and F, E, TB are equal and LB = 0 code word CW
Back pattern of (F, E, 0) and CW (F, E, 0) (“CW-No.” = 1,4,13,16).

(1.2) The code word CW (F, 1, ×) of F ≠ 1, E = 1, TB = 1 is
CW (F, 1, ×) back pattern (“CW-No.” = 2,3,14,15). In addition,
“X” indicates that both 0 and 1 are possible.

(1.3) Codeword CW with F = 1, E ≠ 1, TB = 1, LB = 1 (1, E,
1) is combined with CW (1, E, 1) and codeword CW (1, E, D) in which the values of F, E and TB are equal and LB = 0 (“CW−No.” = 5,6, 1
1,12).

(1.4) Codewords CW (1,1, ×) and CW (1, where F = 1 and E = 1
1, x) back pattern Corresponds to a data word alone without being combined with other code words (“CW-No.” = 7,8,9,10).

By combining the codewords (1.1) to (1.4) shown above, as shown in FIG. 7, even when the codewords are connected, it is possible to satisfy the d, k restriction without fail.

In “PARAMETERS” in FIG. 7, E and LB are the numbers in FIG.
It is a value relating to the R block of the code word W1, and F is shown in FIG.
It is a value related to the L block of W2, and Y is a value of Y = “1” when W2 is a back pattern and Y = “0” when W2 is a back pattern in the case of F ≠ 1 of W2. , S is d,
It is a parameter that is effective only when the preceding codeword W1 is replaced to satisfy the k constraint, and W1 with LB = S is selected. Note that "-" indicates that it has nothing to do with W1.
Further, "EXAMPLE" in FIG. 7 exemplifies states of the R block of W1 and the L block of W2 corresponding to the values of the respective parameters.

The connection rules for the code words shown in FIG. 7 are summarized as follows. It is assumed that the code word W0 preceding W1 and the TB of the code word W1 following W0 are already determined.

(I.1) (W2 F = 0) or (W1 E = 0 and W2 F
= 2), W2 is selected and used so that TB of W2 = LB of W1.

(I.2) When (F1 of W1 and F = 2 of W2), T of W2
W2 is selected and used so that LB of B ≠ W1.

(I.3) When (F of W2 is 1 and E of W1 is 0), T of W1
Select W1 so that LB of W1 = TB of W2 without changing B.

(I.4) When (F = 1 of W2 and E = 1 of W1), W1, W2
Both are used as they are.

(I.5) When (F of W2 = 1 and E of W1 = 2), T of W1
W1 is selected and used so that LB of W1 ≠ TB of W2 without changing B.

The above (I.1) corresponds to No. = 1,2,5 to 8,15,16 in FIG. 7, and in this case, LB = TB, so the number of consecutive bits of the same binary value in the connection part is BLEN. Becomes BLEN = r + 1.

Here, when F = 0, since 1 = 1 from the above definition, BLEN = 1 + r, and 1r11, so d = 2
BLEN12 = k, which satisfies the d, k limit.

On the other hand, when E = 0 and F = 2, from the above definition, r = 1,7l
Since it is 11, d <7 BLEN = r + 1 + 1 + 112 = k and the d, k restriction is satisfied.

The above (I.2) corresponds to No. = 13,14,19,20 in FIG. 7, where LB ≠ TB and E1 (2
Since r11) and F = 2 (7l11), the d, k restriction is satisfied.

The above (I.3) corresponds to No. = 3,4 in FIG. 7, and at this time, since LB = TB, so BLEN = l + r, but from the above definition, E = 0 (r = 1), Since F = 1 (2l6), d <3 BLEN7 <k and the d, k restriction is satisfied.

The above (I.4) corresponds to No. = 9 to 12 in Fig. 7, and LB
If ≠ TB (No. 10, 11), E = 1 (2r
6) and F = 1 (2l6), the d, k constraint is satisfied.

On the other hand, when LB = TB (No. 9 and 12), BLEN = r + l, but 4r + l12, so d <4BLEN12 =
k, which satisfies the d, k constraint.

The above (I.5) corresponds to No. = 19,20 in FIG. 7, where LB ≠ TB, and E = 2 (7r1) from the above definition.
Since 1) and F = 1 (2l6), the d, k constraint is satisfied.

As described above, due to the combination of the codewords of (1.1) to (1.4) and the connection rule of (I.1) to (I.5), d = 2,
Obtain an RLL code that satisfies k = 12.

In addition, the reason why the TB of W1 is not changed in the above connection rules (I.3) and (I.5) is that when the TB of W1 is changed, the codeword W0 preceding W1 or the codeword preceding W0 This is because you have to go up to and control it.

Also, when W1 is changed ((I.3), (I.5), E of W1 ≠
In 1), the combination of the codewords (1.1),
As can be seen from (1.3), for codewords with E ≠ 1, T
Since the values of B and F are the same and the codewords of LB = 0 and LB = 1 are always combined, the parameter related to the L block of W1 does not change even if W1 is replaced, and therefore the codeword W0 preceding W1 The number of consecutive bits of the same binary value in the connection part of W1 is also 2 or more and 12 or less, which satisfies the d, k limit.

[Explanation of Table 2] The combination of the code words shown in Table 2 is RL in FIG.
Regarding the L code C ₁ , it can be obtained by combining the combination of the front pattern and the back pattern for the code word of F = 1 in the combination of Table 1. That is, in the combination rules (1.1) to (1.4), the code word of F = 1 is applied by applying the combination rule in the case of F ≠ 1.

Therefore, as far as the RLL code C _{1 is} concerned, it is not necessary to specially distinguish the code word of F = 1, and further, from the relationship with the connection rule between groups described later, F = in the RLL code C ₁
The code word of 1 is handled as a code word of F = 2.

The RLL code C ₁ combined according to Table 2 and the first
The connection with the RLL code C ₂ combined according to the table also satisfies the d, k restriction in the same manner as in the case of Table 1 according to the connection rules (I.1) to (I.5).

[Explanation of Table 3] The combinations of code words shown in Table 3 are RL in FIG.
Regarding the L code C _g , the code word of LB = 0 and the code word of LB = 1 are combined with respect to the code word of E = 1 in the combination of Table 1. That is, the combination rule (1.
1) to (1.4), for a codeword with E = 1, E ≠
It is nothing but a combination of applying the combination rule in the case of 1.

Therefore, as far as the RLL code C _{g is} concerned, it is not necessary to specifically distinguish the code word of E = 1, and further, from the relationship with the connection rule between groups described later, E = in the RLL code C _g .
The code word of 1 is treated as a code word of E = 2.

In the combination of code words shown in Table 3, 1
The absolute values of disparities of the codewords that form one combination must be equal, and the disparity values themselves must be equal for two codewords that start with the same binary value.

For example, the code words in Table 3 "CW-No." = 1.3,1.4 both start with "1" and their disparity DP is also A. Therefore, their back pattern (“CW-No.” = 1.
2,1.1) Both disparity DPs are also -A.

Further, A in Table 3 is a symbol that represents all the values that can exist as disparity, and does not indicate one specific value.

The reason why such a restriction on disparity is necessary is as follows. CW _{g of} G1 when connecting groups
When replacing, it ends with a CW _g0 with a “0” and with a “1”
If the disparity of CW _g1 is different, replacing the CW _g of G1 will change the DSV value DSV ₁ at the last bit of G1.

If the polarity of DSV ₁ is reversed, G2 must be reversed, thus changing the CW _g of G1 again, the polarity of DSV ₁ is reversed again, and CW _g is permanently determined. Absent.

Thus, for CW _g , a combination of code words that does not cause DSV ₁ polarity inversion is required, and for such a combination, disparity is equal to TB of A and A or A and A ± 2. It is sufficient to use one codeword (and a codeword obtained by inverting all “1” and “0” thereof).

In the present embodiment, a combination having the same disparity is selected because the means for calculating the group disparity is easy.

In this case as well, the CW _g of G1 must be replaced, but even if it is replaced, DSV ₁ does not need to be recalculated because the disparities are equal.

The RLL code C _g-1 in combination according to Table 1, the connection to the RLL code C _g in combination according to Table 3 also, in accordance with the successively law (I.1) (I.5), in the case of Table 1 Similarly, d,
meet the k-limit.

As shown above, due to the combination of the code words shown in Tables 1 to 3 and the connection rules of (I.1) to (I.5) above, d in the middle part of the group excluding the beginning and end of the group , k limit can always be satisfied.

Next, connection between groups will be described.

In FIG. 8 showing the connection between the groups, “DV” is related to the DSV value DSV ₁ at the last bit of the preceding group G ₁ , DV = 1 if DSV ₁ 0, DV = −1 if DSV ₁ <0 "GP" is the group disparity GDP ₂ of the group G2 that starts with "1" following G1. If GDP ₂ = 0, then GP =
If 0, GDP ₂ > 0, GP = 1; if GDP ₂ <0, GP = −1; “GI” is GI = 0 when G2 is not inverted, and GI = 1 when it is inverted. The value, "E '", is E of CW _g of G1
If 0, E ′ = 0, if E1, E ′ = 2,
"F '" is F = 0 if F of CW ₁ of G2' values and = 0, F1 if _{F '= 2, "S g} " relates to the selection of CW _g of G1, S _g
= TB is the last bit of LB CW _g selects the CW _g towards equal to TB, S _g = TB is a value indicating a selection of the direction of LB ≠ TB becomes CW _g, "LB" is S _g It is the value of the last bit of G1 after selection by.

In FIG. 8, the value GI for controlling the inversion / non-inversion of the group G2 is determined only by DV and GP, and GP = 0 or GP = −
GI = 0 for DV, and GI = 1 for other GP and DV.

In this embodiment, since the head bit of G2 is "1" as a reference, GP is a value related to G2 starting with "1". Therefore, GI = 0 indicates the first bit TB = 1 of G2, and GI = 1
Indicates TB = 0.

On the other hand, the value S _g that controls the replacement of CW _g of G1 is GI, E ′,
Determined by F ', L only if E' = 2 and F '= 2
Select CW _{g such} that B ≠ TB, and if E ′ ≠ 2 or F ′ ≠ 2
Select CW _{g where} LB = TB.

Regarding No. = 2 to 4 in Fig. 8, even if 11 bits consecutive "1" or "0" is replaced by 2 bits consecutive "1" or "0", d = 2, k = 12 It turns out that the following restrictions are satisfied. That is, the codeword of E1 is E ′ with respect to CW _g.
It can be seen that even if the codewords of F1 = C2 are handled collectively as codewords of = 2 and the codewords of F1 with respect to CW ₁ are handled collectively as codewords of F ′ = 2, the d, k restriction is satisfied.

As described above, a DC-free RLL code can be obtained by forming a group with g non-DC-free RLL codes and controlling the DSV between the groups.

Note that the number of code word pairs N ₁ = 34423 obtained as a result of combining d = 2, k = 12, and n = 22 according to Table _1.
(> 32768 = 2 ^15), the number of sets of code words obtained as a result of the combination according to table 2 N ₂ = twenty-one thousand nine hundred and eighty-six (> 16384 =
2 ¹⁴ ), and the number of code word pairs obtained as a result of combining in accordance with Table 3 is N ₃ = 16645 (> 16384 = 2 ¹⁴ ).

Therefore, m ₁ = m _g = 14, m _i = 15 (2ig-1), so T _ω /T={28+15(g-2)}/22·g<0.682, and when g = 6, Is obtained.

_T ω /T=0.667 for _T ω /T=0.5 in the conventional 4/8 conversion may about 33% wider.

As described above, the d = 2, k = 12, n _i = 22 (iig) example has been shown for the selection / combination rule of codewords, the connection rule between codewords, and the connection rule between groups. The rules can easily be extended to any d, k, n _i .

That is, in the above rule, the code word length n _i and the RLL code word g (2) forming one group have nothing to do with the conditions for satisfying the d, k and DSV restrictions.

For example, when d = 2 and k = 12, the conditions (i) and (i
For a codeword that satisfies i), regardless of the codeword length, as long as the above rule is followed, the d, k restriction is always satisfied, and the DSV does not diverge.

Therefore, the code lengths of the RLL codes that form one group can be set independently of each other, and may be the same or different.

Further, the above condition (i) can be generalized to the following condition (i) '.

(I) 'xlk-d + 1, d-xrk-d + 1
1 × d−1 Note that l and r1 are set only when d = 1. here,
The F and E are expanded as in the following equation (1).

However, it is dzk-d.

It can be seen from the following that the d, k limit is satisfied even if the codewords are connected according to the connection rule defined in this way.

When E = 0, the result of controlling so that TB = LB is: d = d−x + xr + ld−1 + k−d + 1 = k, When F = 0, the result of controlling so that TB = LB, d = d− When x + xr + lk-d + 1 + d-1 = k, E = 1 and F = 1, TB ≠ LB obviously satisfies the d, k constraint, and when TB = LB, d <d + 2r + dk-z + z = k, E = 2, and If F ≠ 0, or E ≠ 0 and F = 2,
Since the first codeword or the second codeword is controlled so that TB ≠ LB, the d, k restriction is satisfied.

By the way, when the values of x in the condition (i) ′ and z in the formula (1) take the values shown in the formulas (2) and (3), the number of codeword pairs becomes maximum. It can be easily confirmed by using.

x = MAX (1, [d / 2]), or x = MAX (1, d- [d / 2])
(2) z = [k / 2] or z = k- [k / 2] (3) However, MAX (A, B) indicates that the larger value of A and B is taken. , [A] indicates that it takes a maximum integer value that does not exceed A.

When d = 2 and k = 12, x = 1, z = 6, k−d + 1
= 11, and this generalized result is consistent with the condition (i).

In this embodiment, not only d = 2, k = 12, n _i = 22, g = 6 but also d =
DC that T _ω /T=0.667T even at 2, k ＝ 13, n _i ＝ 19, g ＝ 9
Free RLL codes can be realized, and many DC-free RLL codes that cannot be obtained by conventional methods can be realized.

Next, the implementation means of the present embodiment will be described separately for the group generation circuit for generating groups and the group connection circuit for connecting the groups.

First, regarding the group generation circuit shown in FIG.

FIG. 9 shows a circuit for controlling the selection / connection of codewords so as to satisfy the d, k restrictions within the group.

In FIG. 9, the data word generation circuit 1 generates a data word DW _i of m _i bits. The code word generation circuit 2 generates the code word CW _ia of n _i bits corresponding to the data DW _i and the parameters F and E related to the L and R blocks thereof, and the code word generation circuit 3
Generates a code word CW _ib of n _i bits corresponding to the data DW _i , and sends the code words CW _ia and CW _ib serially.

Here, the code words CW _ia and CW _ib are code words that are combined according to Tables 1 to 3, and the binary values that form the L block
Choose those with TB equal to each other. Furthermore, when the front pattern and the back pattern are combined, the front pattern is selected. It should be noted that in Table 1, code words that are not combined with other code words are defined to be generated by the code conversion circuit 2.

The holding circuits 4 and 5 hold the values of the parameters E and LB relating to the R block of W1. The value of LB may be the value of the last bit of the codeword.

The Y generation circuit 6 generates a value Y for controlling whether W2 is a front pattern or a back pattern according to FIG. However, since the first code word CW ₁ in the group is defined as a table pattern within the group (see the description of FIG. 8 above), it is necessary that Y = 0 for CW ₁ .

Therefore, the control signal is generated by the counter 7, which counts the number of the code word in the group CW _ia , CW _ib of the code word generation circuit output, and sends out the value i. , A signal indicating that it is the first codeword (i = 1)
To generate.

At the output of the exclusive OR (EXOR) gate 8, CW _ia ′ (= CW _ia (Y = 0) or the back pattern ▲ ▼ (Y = 1) of CW _ia ) appears according to the value of Y. Similarly, the output of the EXOR gate 9 is CW _ib ′ (= CW _ib (Y = 0) or ▲
▼ (Y = 1)) appears.

The output of the EXOR gate 8 is sent to the n _i bit delay circuit 10 for EXOR
The output of the gate 9 is sent to the n _i bit delay circuit 11.

The code words CW _ia ′ and CW _ib ′ have a length of n _i bits.

On the other hand, the holding circuit 12 holds the value of the first bit TB of the code word appearing at the output of the EXOR gate 8.

CW that is the output of the holding circuit 12 and the output of the codeword generation circuit 2
_{Using the} parameter F for the L block of _{ia and} the parameters E, LB for the R block of the preceding codeword W1 and the outputs of the holding circuit 4 and the holding circuit 5, according to FIG. If the output of the n _i- bit delay circuit 10 is selected, S = 0, and if the output of the n _i- bit delay circuit 11 is selected, S =
The S generation circuit 13 generates the value S of 1.

When the output of the n _i bit delay circuit 10 is CW _ga ′ which is the last code word of the group, the code word following CW _ga ′ is the first code word of the next group and the connection between the groups. Also, since the control for satisfying the d, k limit is performed after the DSV control, here, the n _i bit delay circuit 10 is forcibly forced.
The output of is selected (S = 0). This control is performed by the output (i = 1) of the counter 7.

The switch 14 selects and outputs the output of the n _i bit delay circuit 10 and the output of the n _i bit delay circuit 11 according to the value of S.

As a result, the code word CW _i-1 ′ (= CW _{i
i-1, a} 'or CW _{i-1, b} ' appears.

FIG. 10 shows a timing chart regarding the operation of FIG. 9 when g = 6. The subscript in Fig. 10 is CW _ia , C
Corresponds to the value of i in W _ib . For example, F ₁ is CW _1a and C
It is the value of the parameter F for the L block of W _1b .

According to the circuit of FIG. 9 and the timing chart of FIG.
The connection rules (I.1) to (I.5) of the codewords can be realized, and a group satisfying the d, k restriction can be obtained within the group.

Next, the group connection circuit shown in FIG. 1 will be described.

FIG. 1 shows a circuit for obtaining a DC-free RLL code that satisfies the d, k limits even if groups are connected while keeping DSV finite. Group generation circuit 15 (FIG. 9), DSV control Circuit, d, k control circuit. Group generation circuit .DSV
The control circuit is for controlling group inversion (reversing all 1s in a group to 0 and 0s to 1) and non-inversion in order to keep DSV finite.
GDP calculation circuit 16 for obtaining the number difference group disparity GDP of G, and if GDP <0, GP = −1, and if GDP = 0, GP =
If 0, GDP> 0, a GP generation circuit 17 that generates a value GP that sets GP = 1, a holding circuit 18 that holds the DSV value at the last bit of the preceding group, and if DSV0, DV = 0, DSV If it is <0, the DV generation circuit 19 that generates DV = 1 and the value GI that sets GI = 1 if the group is inverted according to FIG. 9 based on GP and DV and GI = 0 if it is not inverted GI generation circuit 20
And GI = 0, GDP '= GDP, GI = 1 GDP' =-GD
Selection circuit 21 for selecting P and adder 2 for obtaining DSV + GDP '
2 and one group delay circuit 23 and an exclusive OR (EXOR) gate 24.

The group sent from the group generation circuit 15 is G _{j + 1}
When the inverted and non-inverted for this group G _{j + 1} has to be done after the group disparity GDP _{j + 1} is Motoma' about G _{j + 1.} Therefore, the one-group delay circuit 23 is required.

Further, at the same time that the head bit of G _{j + 1} appears in the output of the group generation circuit 15, the output of the 1-group delay circuit 23 is
_{The first} bit of group G _j preceding _{j + 1} appears.

At this time, it generates GP _j, the DV _j-1, to obtain a GI _j for G _j, GI
According to the value of _j , the output of the EXOR gate 24 is G _j ′ (= G _j (GI _j
= 0) or an inversion pattern _j (GI _j = 1)) of G _j appears.

Incidentally, GP _j the value of GP corresponding to the group disparity GDP _j of G _j, DV _j-1 corresponds to the DSV value DSV _j-1 in the last bit of the group G _j-1 preceding the G _j These are DV values, and these values and GI _j are held for one group.

Along with GP _j DV _j and GI _j , the DSV value DSV _j at the final bit of G _{j such} that DSV _j = DSV _j-1 + GDP _j ′ is obtained and held in the holding circuit 18. Then, immediately after the GP _j is obtained, the contents of the GDP calculator 16 are cleared.

With the above settings, inversion / non-inversion control can be realized so that the DSV does not diverge for each group in the group sequence that appears continuously.

The d, k control circuit controls whether or not to replace the last codeword of the preceding group to satisfy the d, k limit even if the groups that have been controlled to satisfy the DSV limit are connected. And the parameters E, LB relating to the R block of the last codeword of the preceding group G,
Based on the holding circuit 25 for holding the value of the parameter F relating to the L block of the first code word of the group following the group G and the values of these E, F, LB and the value of GI, the group G S _g = if the last codeword is replaced
1, S _g generation circuit 26 that generates a value S _g of S _g = 0 if not replaced, 1-group delay circuit 27, EXOR gate 28,
It comprises n _g bit delay circuits 29, 30 and a switch 31.

Note that the group generation circuit 15 uses the m / n code conversion means, GDP
The arithmetic circuit 16 is the group disparity arithmetic means, the holding circuit 18 and the adder 22 are the digital sum variation arithmetic means, the GP generation circuit 17, the DV generation circuit 19, and the GI generation circuit 2
0, the selection circuit 21 corresponds to the group disparity polarity control means, the EXOR gates 24 and 28 correspond to the code word group inversion control means, and the S _g generation circuit 26 and the switch 31 correspond to the code word replacement means.

Below, the code word C appearing at the output of the data word generation circuit 15
W _i ′ _(j) represents the i-th codeword of the j-th group G _j appearing at the output of the switch 14 in FIG.
_It is assumed that _ib ' _(j) represents the first code word of G _j appearing at the output of the n _i bit delay circuit 11 in FIG. The CW _{g '(j)} only CW _ga' because they definite to _(j), CW _g '
without the _(j) referred to as a CW _{ga '(j).}

Now, the code word sent from the group generation circuit 15 is the first code word CW _{1 (j + 1)} of the group G _{j + 1} , and the first bit of CW _{1 (j + 1)} is the group generation circuit 15 Of the code word CW ₁ ′ _(j) appears at the output of the 1-group delay circuit 23 and appears at the output of the EXOR gate 24 according to the output GI _j of the GI generation circuit 20. CW ₁ ″ _(j) (＝ CW _i ′ _(j) (GI _j
= 0), or the inversion pattern of CW ₁ ′ _(j) ▲
▼ (GI _j = 1)) appears, and the output of the n _g bit delay circuit 29 shows the last code word CW _ga ″ of the group G _{j-1.
The first} bit of _(j-1) appears.

On the other hand, the code word CW _ga ″ _(j−1) , the value of the _first bit, the value of the parameter F for the L block, and the value of the parameter E for the R block are the same, and the code word CW having different binary values forming the R block _gb ′ _(j-1) is the group generation circuit 15
Output b, 1 group delay circuit 27, EXOR gate 28, and _ng bit delay circuit 30.

That is, since the codewords CW _ga ″ _(j-1) and CW _gb ″ _{(j-1) take} exactly the same path, the _first bit of the codeword CW _ga ″ _(j-1) is n _g
At the same time as it appears at the output of the bit delay circuit 29,
The _first bit of CW _gb ″ _(j-1) appears at the output of _ng bit delay circuit 30.

Furthermore, the code word CW _ga ″ _(j-1) held in the holding circuit 25
Values of parameters E and LB for the R block of E _j-1 , LB
_{Based on j−1} , the value F _j of the parameter F relating to the L block of the code word CW ₁ ′ _(j) , and the control signal GI _j from the GI generation circuit 20, the S _g generation circuit 26 codes according to FIG. Word CW _ga ″ _(j-1)
To CW _gb ″ _(j-1) is generated to generate a control signal S _{g, j−1} . The control signal S _g is the output of the n _g bit delay circuit and is the final code word of the group. Can be S _g = 1 only, and all other codewords are S _g = 0. Further, E ′ and F ′ in FIG. 8 are based on E _j−1 and F _j . Then, the conversion is performed in the S _g generation circuit 20.

The switch 31 receives the code word C when the control signal S _{g, j−1} = 0.
If W _ga ″ _(j-1) is selected and S _{g, j−1} = 0, then the code word C
Select W _gb ″ _(j-1) to output.

As a result, a DC-free code limited in d, k is obtained at the output of the switch 31.

FIG. 11 shows a timing chart regarding the operation of FIG. In FIG. 11, a code word obtained by inverting all 1, 0, 0 and 1 of the code word A is represented as.

A DC-free RLL code can be obtained by using the circuit of FIG. 1 and the timing chart of FIG.

FIG. 12 is a block diagram of the decoding circuit. The decoded word CW _i is represented by CW _i
For decoding into a data word DW _i corresponding to.

In FIG. 12, it appears at the output of switch 31 in FIG.
The d, k and DSV limited bit strings are applied to one input terminal of the exclusive OR (EXOR) gate 33 through the holding circuit 32. The holding circuit 32 operates in 1-bit units.

On the other hand, the holding circuit 34 takes in the head bit GTB of the group, keeps the negated value GTB for one group, and applies it to the other input terminal of the EXOR gate 33.

As a result, the output of the EXOR gate 33 always shows the group G _j starting with 1.

This G _j is equal to the group G _j appearing at the output a of the group generation circuit 15 in FIG.

The serial-to-parallel converter 35 _{outputs the} code word from the group G _j.
Take out CW _i and send in parallel.

In the data word decoding circuit 36, the parallel CW _i and this CW _i are
The value i representing the number of the code word of the group G _j is counted,
Based on the output i of the counter 37 that outputs this value i,
Decode the data word DW _i corresponding to CW _i .

As described above, according to the present embodiment, it is possible to generate the DC-free RLL decoding and to decode the data word from the DC-free RLL code.

Second Embodiment The second embodiment of the present invention relates to the third feature of the present invention, and is a code conversion device capable of reducing the circuit scale used when decoding the code word CW _i into the data word DW _i as compared with the conventional one. is there.

Hereinafter, for the present embodiment, the d = 2, k = 12, n _i = 22 (1
ig) will be described.

FIG. 13 is a block diagram showing a circuit configuration for realizing this embodiment. In addition to the decoding circuit of FIG. 12, codewords are converted into a table pattern (excluding codewords of F = 1). The circuit and the 22-bit codeword are divided into 14-bit and 8-bit,
It is composed of a temporary decoding circuit that generates bit pattern numbers BP ₁ and BP ₂ corresponding to each, and a final decoding circuit that decodes a data word based on BP ₁ and BP ₂ . The temporary decoding circuit and the final decoding circuit correspond to the temporary decoding means and the final decoding means, respectively.

As shown in the explanation of Figure 12, the exclusive OR gate
In the output of 33, the group G _j starting with 1 appears. The code words CW _i (1 ig) forming this group G _j have either a front pattern or a back pattern in order to satisfy the d, k restriction within the group.

From the viewpoint of reducing the amount of information used for decoding as much as possible, all the code words that combine the front pattern and the back pattern are converted into the front pattern and then decoded.

As can be seen from Tables 1 to 3, the combination of the front pattern and the back pattern is a code word in which the value of the parameter F relating to the L block of the code word is not 1 or the code word CW ₁ at the head of the group. Is.

In FIG. 13, the holding circuit 38 holds the first bit TB of the code word, and the F = 1 detection circuit 39 does not hold (F = 1) = 1,1 if the value of the parameter F for the L block of the code word is 1. If so, a value (F = 1) = 0 (F = 1) is output.

Since the NOR gate 40 receives TB and (F = 1) as its inputs, its output becomes 1 only when TB = 0 and F ≠ 1. Therefore, the 6 bits required to detect F = 1 (F = 1: 2
The code word coming through the delay circuit 41 of 16) is converted into a table pattern by the EXOR gate 42 only when the output of the NOR gate 40 is 1.

The serial code word appearing at the output of the EXOR gate 42 is converted by the serial-parallel converter 35 into a 22-bit parallel code word. Of these, 14 bits from the first bit are sent to the temporary decoding circuit 43, and 8 bits from the last bit. Bit temporary decoding circuit 44
Send to.

At this time, the same 2 in the R block of the codeword used
If the number of consecutive bits r of the decimal value is limited to 6 or less, the input 14 bits of the temporary decoding circuit 43 can be distinguished from each other by 10 bits and the input 8 bits of the temporary decoding circuit 44 by 6 bits.

The number of code word pairs when r6 is 33295 (> 2 ¹⁵ ) according to the combinations in Table 1 and 21 when according to Table 2.
266 (> 2 ¹⁴ ) and 16553 (> 2 ¹⁴ ) according to Table 3. Also, the number of bit patterns in 14 bits BP ₁ = 949
(<2 ¹⁰ = 1024), the number of bit patterns in 8 bits BP ₂
= 64 (= ²⁶ ).

Since the pair of code words CW _i and (BP ₁ , BP ₂ ) has a one-to-one correspondence,
The (BP _1, BP ₂₎ also on the basis of decoded data word DW _i corresponding to the code word CW _i, no any inconvenience.

The final decoding circuit 45 outputs the data word corresponding to the provisionally decoded (BP ₁ , BP ₂ ).

The temporary decoding circuits 43, 44 and the final decoding circuit 45 correspond to the data word decoding circuit 36 in FIG. 12, and the final decoding circuit 45 becomes (BP ₁ , BP ₂ ) according to the value of the output i from the counter 37. It is decided whether to decode the corresponding data word according to any one of Tables 1 to 3.

By using this embodiment, the memory required to decode the 22-bit code word CW _i is 14 bits for the address and 10 bits for the temporary decoding circuit 43. Therefore, V ₁ = 2 ¹⁴
- 10-bit, with respect to the provisional decoding circuit 44, address 8 bits, because the output is 6 bits, for V ₂ = 2 ⁸ - 6 bits, a final decoding circuit 45, address 16 bits, the output 15 (or 14) bits Therefore, V ₃ = 2 ¹⁶ · 15 bits, total V
= V ₁ + V ₂ + V ₃ 1.1 Mbits.

Address 22 bits in the conventional decoding circuit, since the output is 15 bits, since a memory capacity V '= 2 ²² · 1560M bits, by using the present embodiment, about 1/60 the amount of memory required for the decoding circuit Yes, it is very economical.

The present embodiment is not limited to the case of d = 2, k = 12, _ni = 22, and d =
It can be used for decoding all RLL codes except for the case of 1, k = ∞.

Third Embodiment The third embodiment of the present invention is related to the third feature of the present invention and is combined according to Tables 1 to 3 by determining the correspondence relationship between the data word and the code word as described below. This is for realizing the correspondence between a set of code words and a data word by a common code word generation circuit and data word decoding circuit.

In this embodiment, the data word generation circuit 1 in FIG.
Codeword generation circuits 2 and 3 and final decoding circuit 45 in FIG.
Only the configuration of the above, and other circuits and the operation thereof are completely unchanged.

Hereinafter, the present embodiment will be described in detail with reference to the drawings. Also in this embodiment, d = 2, k = 12, _ni = 22 (i
= 1 to g), the DC-free RLL code is used as an example.

For d = 2, k = 12, n _i = 22, the above conditions (i) ′, (i
i) Number of codeword pairs CWC ₁ combined according to Table 1 according to Table ₁ N ₁ = 34423, number of codeword pairs CWC 2 combined according to Table ₂ N ₂ = 21986, according to Table 3 The number N _{3 of the} combination CWC3 of codewords is 16645. However, z = 6 in Formula (1).

Therefore, the code word set CWC1 has 15 bits (N ₁ > 2 ¹⁵ ).
Data word, code word pair CWC2 has 14 bits (N ₂ > 2 ¹⁴ )
Data word, code word pair CWC3 has 14 bits (N ₃ > 2 ¹⁴ )
The data words can be associated with each other.

Here, the code word generation circuit 2 in FIG. 9 is configured by a ROM (Read Onli Memory) 46 and a parallel-serial converter (P / S) 47, as shown in FIG. The code word generation circuit 3 is composed of a ROM 48 and a parallel-serial converter (P / S) 48.

The ROM 46 in FIG. 14 has an address of 15 bits and an output of 26 bits (code word 22 bits, F and E 2 bits each), and the data word D is always 15 bits from the data word generation circuit 1.
Let W _i ′ be the output of the 22-bit codeword CW _ia corresponding to DW _i ′ and the values of the parameters F and E for the L block and the R block.

The parallel-serial converter 47 converts the 22-bit parallel code word CW _ia from the ROM 46 into serial and sends it out.

On the other hand, the ROM 48 has an address of 15 bits and an output of 22 bits, and outputs a 22-bit code word CW _ib corresponding to the data word DW _i ′.

However, the code words CW _ia and CW _ib are code words combined according to Tables 1 to 3, starting with the same binary value (only 1 when F ≠ 1).

The parallel-serial converter 49 converts the 22-bit parallel code word CW _ib from the ROM 48 into serial and sends it out.

Next, there are three types of data word and code word pairs, that is, a 15-bit data word and code word pair CWC1, a 14-bit data word and code word pair CWC2, and a 14-bit data word and code word pair. CW
Correspondence relationship for C3 is shown as a set of ROM (Fig. 14 ROM46, 48)
A method for realizing this will be described.

Since the addresses of ROMs 46 and 48 in FIG. 14 are both 15 bits, the code word set CW that can correspond to a 15-bit data word is
Regarding the generation of C1, the data word generation circuit 1 may fetch a 15-bit data word from the input data string and send it as it is to the ROMs 46 and 48 as the data word DW _i (2ig-1).

However, regarding the generation of the code word pair CWC2, CWC3 that can handle only 14-bit data words, the data word generation circuit 1 uses the 14-bit data word D from the input data string.
ROM 15 is used to store a 15-bit data word DW ₁ or DW _g obtained by taking in W ₁ ′ or DW _g ′ and adding a 1-bit dummy to it.
Must be sent to 6,48.

In this embodiment, with respect to the data word DW _g ′, 0 is added next to the least significant bit (LSB) to make DW _g , and the data word DW _g
Regarding W ₁ ′, 0 is added to the most significant bit (MSB) to make it DW ₁ . That is, DW ₁ = 0.DW ₁ ′, DW _g = D
W _g ′ · O. In the following, regarding data words and ROM addresses, A is a 15-bit value, A'is a 14-bit value,
A ″ represents a 13-bit value, and 0 · X ′ is the MSB = 0 of the 15-bit value and the 14-bit value following the MSB is X ′, X ′ · 0.
Is a 15-bit value whose upper 14-bit value is X'and LSB = 0,
0 · X ″ · 0 indicates that MSB = LSB = 0 and the 13-bit value surrounded by MSB and LSB is X ″.

Therefore, the DW ₁ has its MSB = 0, the value of the lower 14 bits is
DW ₁ ′ represents a value consisting of 15 bits, and DW _g represents that the value of the upper 14 bits thereof is a value consisting of 15 bits of DW _g ′ and LSB = 0.

Thus, the code word set CWC2 is set at the addresses 0 and X'of the ROM 46 and 48, and the code word set CWC3 is set at the address Z'.0.
Must exist respectively.

Therefore, N ₂ = 2198 is assigned to the addresses 0 and X'of the ROMs 46 and 48.
Of the six sets certain codeword set CWC2, is stored to choose 16384 pairs, stored in the address Z '· 0 of ROM46,48, N ₃ = 16645 sets there to choose 16384 sets of code words set CWC3 Let

However, there is an address 0 · X ″ · 0 that is common to addresses 0 · X ′ and Z ′ · 0, and at this address 0 · X ′ · 0, a codeword common to the codeword set CWC2 and CWC3. Must exist.

Here, looking at Tables 2 and 3, it can be seen that the set of code words starting with 1 in Table 3 can be a common set of code words.

This is because, while all codeword sets CWC3 in Table 3 have restrictions on disparity, the codeword set CWC2 in Table 2 has no restrictions on disparity. The first reason is that the codeword set in Table 3 must be selected as a common codeword set.

Next, among the code word sets CWC2 in Table 2, only the code word sets starting with 1 are selected as the code word generating circuit 2 in FIG.
3, that is, since it has been determined that the ROM 46, 48 in FIG. 14 generates the codeword group starting with 0 in Table 3,
The second reason is that it cannot be a common codeword pair
Is.

Of the common code word groups selected as described above, 2 ¹³ = 8192 code word groups necessary for satisfying the address 0 · X ″ · 0 are set to the addresses of the ROMs 46 and 48 in FIG. 0
The data is sequentially stored in X ″ · 0 (X ″ = 0 to 8191).

Here, in the number N ₃ of the code word set CWC3, the parameter F,
Table 4 shows a breakdown of E, N ₃ (F, E). However, N
₃ (F, E) represents the number of codeword pairs in the codeword pair CWC3 whose parameter values for the L and R blocks are F and E.

In order to make the 14-bit data word and code word set CWC3 correspond one-to-one, the code word set CWC3 may be 2 ¹⁴ = 16384 sets, and the fourth
Table 5 shows an example of the breakdown N ₃ ′ (F, E) of 16384 code word sets CWC3 obtained by excluding 16645−16384 = 261 code word sets from the table.

Of the code word sets shown in Table 5, only the code word set with F = 1 has a set of code words starting with 0, and the number is N ₃ ′.
It is (1, E) / 2. Therefore, the set of code words F = 1 starting with 1 in Table 5 is N ₃ ′ (1,0) / 2, respectively.
= 2600, N ₃ ′ (1,1) / 2 = 3341.

Table 6 shows the code word set CW from the code word set shown in Table 5.
An example of selecting a code set common to C2 and CWC3 is shown.

In Table 6, the disparity is A, the binary value constituting the L block is 1, and the parameter value relating to the number of consecutive bits of 1 in the L block is the F and R blocks in Table 6 in the contents of the ROMs 46 and 48. A code word CW (A, F, E, LB) whose binary value is LB, and whose parameter value relating to the number of consecutive bits of LB in the R block is E is shown.

For example, the code word of disparity A starting from 1 and having F = 2, E = 0, and LB = 1 is CW (A, 2,0,1). It should be noted that the disparities A to H in Table 6 may be equal to or different from each other, and only represents that the disparities of the combined codewords are equal.

Next, the data words are made to correspond to the remaining code words CWC2 and CWC3 and stored in the ROMs 46 and 48 in FIG. 14, but in this case, the same code word has the same ROM for different 15-bit inputs. It should not be output.

For example, Table 7 shows the relationship between the codeword set CWC3 determined based on the common codeword set shown in Table 6 and the data word.

The meaning of each symbol in Table 7 is the same as in Table 6, and the relationship between the code word set and the data word is F in Table 6.
When the data word corresponding to the code word set CWC3 (F = 1) of = 1 is 0 · X ″ · 0, the code word is composed of the code words of the back pattern of the code words forming the code word set CWC3 (F = 1). Codeword set The data word corresponding to is 1 · X ″ · 0.

As an example, the code word set CW (D, 1,1,0) in Table 6
And the data word corresponding to CW (D, 1,1,1) is 0 ・ (4458) ・
If 0, The data word 1 (4458) 0 is associated with.

On the other hand, 2251 sets excluding 22 sets of codewords CW (P, 0,1,0) and CW (P, 0,1,1) used as common codeword sets in Table 6 Codeword set CW belonging to codeword set CW3
(Q, 0,1,0), CW (Q, 0,1,1) has 2251 remaining LSBs
= 0 data word 1 (0-1857), 0 and 1 (7799-81)
91) ・ Correspond to 0.

Due to the correspondence between the data word X ′ · 0 and the code word set CWC3 shown in Tables 6 and 7, all of the 16384 code word sets shown in Table 5 are shown in FIG. The ROMs 46 and 48 exist at different addresses X'.0.

On the other hand, with respect to the code word set CWC2, in addition to the common code word set shown in Table 6, there are remaining code word sets corresponding to the data words 0 · X ″ · 1.

By the way, the code words stored in the ROM 48 out of the set of code words of E = 1 starting with 1 in Table 6 constitute a group when the code words are generated according to Tables 1 and 2. It cannot be a codeword.

This is because the code word of E = 1 starting with 1 in Tables 1 and 2 is combined only with the back pattern, and the code word of this back pattern is the code word generation circuit 2, 3 in FIG.
That is, it is not directly generated by the ROMs 46 and 48 in FIG. 14, but is obtained by inverting the code word starting with 1 generated by the ROM 46 afterward. Therefore, when generating a code word in accordance with the first and second tables so selects the output of the S generation circuit 13 n _i bit delay circuit 10 always in FIG. 9 with respect to the code words of E = 1, n _i bit This is because whatever the output of the delay circuit 11, the output of the switch 14 is not affected.

From the above, the code word of E = 1 shown in the item of contents of ROM 48 in Table 6 can be stored in the address of ROM 46, 0 · X ″ · 1, as shown in Table 8 for example. Become.

Similarly, the code word of E = 1 shown in the section of contents of ROM 48 in Table 7 can be stored in the address of ROM 46 at 1 · X ″ · 1, as shown in Table 9 for example.

Note that the address 1 · X ″ · 1 relates only to the codeword set CWC1, so there is no restriction on disparity.
Since a set of codewords starting from 0 with F = 1 is also allowed as the output of the ROM 46, there is no problem in the correspondence between the datawords and the codewords shown in Table 9.

The symbols and meanings in Tables 8 and 9 are the same as those in Tables 6 and 7, but the address 0 · X ″ · 1 (X ″ =
4458-8191), and address 1 · Z ″ · in Table 9
1 (Z ″ = 0 to 1857, 4458 to 8191) has a code word only in the ROM 46, and these addresses in the ROM 48 have no code word.

As a result, the corresponding codeword set or codeword is 1
The addresses of the ROMs 46 and 48 which have not been determined are 0, X ", 1 (X" = 0-4457), 1, Z ", 1 from Tables 6-9.
It can be seen that (Z ″ = 1858 to 4457).

It should be noted that all of the code word sets and the code words in Tables 6 to 9 are included in the 16384 sets shown in Table 5 among the code word sets combined according to Table 3.

The number of code word pairs CWC13 obtained as a result of combining the code words forming the 16384 code word groups shown in Table 5 according to Table 1 is N ₁₃ = N ₃ (0,0) + N ₃ (1, 0) + N ₃ (2,
0) + 2 (N ₃ (0,1) + N ₃ (1, 1) + N ₃ (2, 1)) = 25710
Becomes The reason for this is that if the codewords forming the set of codewords of E = 1 in Table 5 are CW _ga and CW _gb , different _datawords must be associated with these codewords as long as they follow Table 1. It depends on what you can do.

Similarly, the number of code word sets CWC23 obtained as a result of combining the code words forming the 16384 code word sets shown in Table 5 according to Table 2 is N ₂₃ = N ₃ (0,0) + 2 · N ₃ (0,
1) + N ₃ (1,0) / 2 + 2 ・ (N ₃ (1,1) / 2) + N ₃ (2,0) +
2 · N ₃ (2,1) = 16428.

The reason for this is that since half of the F = 1 codeword sets in Table 5 begin with 0, they are not included in the codeword set CWC2. This is because one set of E = 1 codewords becomes two codewords in the codeword set CWC2.

From these, the code word set CWC2 is sufficient to correspond to 0 · X ″ · 1 (X ″ = 0 to 4457) because N ₂ −N ₂₃ = 5558 sets remain. Set CWC1 is N ₁ −4458−
Since N ₁₃ = 4257 pairs remain, 1 · Z ″ · 1 (Z ′ = 1
858-4457).

It should be noted that the number of consecutive bits of the same binary value in the R block is 6 or less, that is, the number of code word sets CWC1 when only the code word sets of E1 are used N ₁ ′ = 33295, code word set CWC2
The number N ₂ ′ = 21266, and in this case also 0 · X ″ · 1
(X ″ = 0-4457), 1 · Z ″ · 1 (Z ″ = 1858 to 445)
It can cope with 7) enough.

As shown above, 3 shown in Tables 1 to 3 according to this embodiment.
Correspondence between a set of different code words and data words can be realized by one kind of ROM. As a result, only one type of data word decoding circuit 36 in FIG. 12 is required.

Furthermore, even when only the E1 codeword is used, one type of
Since the ROM code word generation circuit can be configured, the number of data word decoding circuits also becomes one, and in this case, the embodiment can be applied as it is, and the decoding circuit can be realized in FIG.

As a result, the total memory capacity required for decoding can be reduced to about 1.1 Mbits.

Although the present embodiment d = 2, k = 12, n i = 22 consists DC-free RLL code shown in the example, it goes without saying that can be extended to the case of other DC-free RLL code, as in the present embodiment The effect of is obtained.

As described above, the practical effect of this embodiment is very large.

EFFECTS OF THE INVENTION As described above, according to the present invention, since DSV control is performed for each group configured by using g consecutive RLL codes, code conversion is performed on each RLL code even if the group length becomes long. The memory capacity required for code conversion is not directly related to the group length.

As a result, for example, d = 2, k = 12, T which could not be realized by the conventional DC-free RLL code due to the unrealistic circuit scale.
_The DC-free RLL code of _ω = 0.667T is realized on a realistic circuit scale, and the practical effect of the present invention is great.
Suitable results are obtained when used for ultra-high density recording such as R.

Furthermore, the present invention is not limited to d = 2, k = 12, but has the generality of being able to be extended to any d, k, and therefore DC-free that is optimal for the system.
A code conversion device that can realize an RLL code can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram of a group connection circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of groups, FIG. 3 is a connection diagram of groups, and FIG. 4 is an example of connection rules of groups. Explanatory diagram, FIG. 5 is a structural diagram of code words, FIG. 6 is a connection diagram of code words, FIG. 7 is an explanatory diagram showing a connection rule of code words, and FIG. 8 is a connection rule of groups. Explanatory diagram, FIG. 9 is a block diagram of the group generation circuit, FIG. 10 is a timing chart of the group generation circuit,
FIG. 11 is a timing chart of the group connection circuit,
The figure is a general block diagram of a decoding circuit, Fig. 13 is a detailed block diagram of a decoding circuit, Fig. 14 is a block diagram of a codeword generation circuit, Fig. 15 is a block diagram of a conventional code conversion circuit, and 16th.
The figure is a block diagram of a conventional decoding circuit. 1 ... Data word generation circuit, 2, 3 ... Code word generation circuit, 4,
5,12,18,25,32,34,38 …… Holding circuit, 6 …… Y generation circuit, 7,37 …… Counter, 10,11 …… n _i bit delay circuit, 1
3 ... S generation circuit, 14,31 ... Switch, 15 ... Group generation circuit, 16 ... GDP arithmetic circuit, 17 ... GP generation circuit, 19
...... DV generation circuit, 20 …… GI generation circuit, 21 …… Selection circuit,
22 …… Adder, 23,27 …… 1 group delay circuit, 26 …… S
_g generation circuit, 29,30 …… n _g- bit delay circuit, 35,50,54 ……
Serial-parallel converter, 36 ... Data word decoding circuit,
39 ... F = 1 detection circuit, 41 ... delay circuit, 43,44 ... temporary decoding circuit, 45 ... final decoding circuit, 46,48,51,52,55 ... RO
M, 47, 49 ... Parallel-serial converter.

Claims (2)

[Claims] 1. A m-bit data word is converted into an n-bit code word, and the number of consecutive bits of the same binary value in a bit string generated by connecting the converted code words is limited to d or more and k or less. At the same time, in the code conversion device that keeps the number difference DSV between “1” and “0” in the bit string finite,
An m-bit data word is input, and an n-bit code word is output so that the number of consecutive bits of the same binary number in a bit string obtained by connecting at least g relevant code words is d or more and k or less. n code conversion means, group disparity calculation means for calculating the number difference GDP between "1" and "0" in a group of g consecutive code words output from the m / n code conversion means, and the group The polarity of the output of the digital sum variation calculation means for cumulatively calculating the output of the disparity calculation means and the output of the group disparity calculation means added to the digital sum variation calculation means differ from the polarity of the output of the digital sum variation calculation means. The group disparity polarity control means for controlling and the polarity selected by the group disparity polarity control means. Then, the code word group inversion control means for controlling whether or not to invert all "1" s to "0" s and "0" s to "1" s in the code word group, and the last of the preceding code word group. When the number of consecutive bits of the same binary value in the bit string obtained by connecting the codeword and the first codeword of the current codeword group is not d or more and k or less, the last codeword of the preceding codeword group is set. A code conversion device comprising: a code word replacement unit that replaces with another code word. 2. An m-bit data word is converted into an n-bit code word, and the number of consecutive bits of the same binary value in a bit string generated by the connection of the converted code words is limited to d or more and k or less. At the same time, in the code conversion device that keeps the number difference DSV between “1” and “0” in the bit string finite,
An m-bit data word is input, and an n-bit code word is output so that the number of consecutive bits of the same binary value in a bit string obtained by connecting at least g relevant code words is d or more and k or less. / n code conversion means, group disparity calculation means for calculating a difference GDP between "1" and "0" in a group of g consecutive code words output from the m / n code conversion means, The polarity of the output of the digital sum variation calculation means for cumulatively calculating the output of the group disparity calculation means and the output of the group disparity calculation means added to the digital sum variation calculation means differ from the polarity of the output of the digital sum variation calculation means. Group disparity polarity control means that controls the group disparity polarity and the polarity selected by the group disparity polarity control means. Then, the code word group inversion control means for controlling whether or not to invert all "1" s to "0" s and "0" s to "1" s in the code word group, and the last of the preceding code word group. When the number of consecutive bits of the same binary value in the bit string obtained by connecting the codeword and the first codeword of the current codeword group is not d or more and k or less, the last codeword of the preceding codeword group is set. Each of the code word replacing means for replacing with another code word and each of the g code words forming the controlled code word group appearing in the output of the code word replacing means are divided into a plurality of bits, and the bits of the divided portion are divided. It is characterized by comprising provisional decoding means for outputting a value capable of distinguishing patterns from each other, and final decoding means for decoding a data word corresponding to each of the g number of code words based on the output value of the provisional decoding means. Code converter .