JPH0744486A - I / O controller - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the efficiency of setting or changing the configuration information of the communication path in the input / output control device that connects multiple hosts by serial interface. An input / output control device for controlling connection between an input / output device and a host by a serial interface via a dynamic switch that dynamically controls channel connection and the like based on a link address and a logical channel address in a transfer frame. The link address table that registers the transfer source link address and the logical address in the logical path establishment frame as the link address and the logical channel address of the dynamic switch port is provided, and the address in the table is used to send when accessing the host. Create a trust frame and send it to the dynamic switch.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output control device for controlling connection between a computer and an input / output device such as a magnetic disk device or a communication control device by a serial interface via a dynamic switch. The present invention relates to an input / output control device suitable for efficiently setting configuration information of an output device.

[0002]

2. Description of the Related Art In an input / output control device connected to a plurality of computers via a dynamic switch, when an input / output processor in the input / output control device transfers an asynchronous status to a specific host channel, a target is set. The link address and logical channel address assigned to the port of the dynamic switch to which the host channel is connected
Need to be set and sent.

FIG. 12 is a block diagram showing an example of the configuration of an input / output system using a conventional input / output control device. In the figure, 120a to 120c are processing devices that perform computer processing, and 121a and 121b are processing devices 1.
20a are hosts that are executed in parallel (indicated as hosts (1) and (2) respectively in the figure), 121c and 121d are hosts that are individually executed by the processing devices 120b and 120c (as shown in FIG. 3), (4)),
Reference numerals 122a to 122c are serial channels for controlling serial input / output of the processing apparatuses 120a to 120c, and 123 is input / output for controlling connection between input / output devices (not shown) such as a magnetic disk and a communication control apparatus and the processing apparatuses 120a to 120c. The controller 124 is the input / output controller 1
23 is a dynamic switch that controls the dynamic connection between the serial communication channels 23 and the serial channels 122a to 122c of the processing devices 120a to 120c.

As described above, in the input / output system having the serial interface, the dynamic switch 124 is used.
Thereby, the dynamic connection control between the plurality of serial channels 122a to 122c and the input / output control device 123 is performed. The dynamic switch 124 controls connection with the serial channels 122a to 122c according to the value of the transfer destination link address in the frame for data transfer. Also, a plurality of hosts 121a and 121b such as the processing device 120a.
, The serial channel 122a identifies with which host the input / output operation is performed by the value of the transfer destination logical channel address in the frame. Therefore, when the attention status is transferred from the input / output control unit 123 to the hosts 121a and 121b, the link address and logical channel address of the partner host are transmitted.
Must be set in the system.

These pieces of information are instructed by the user by the time the product is shipped from the factory, and the input / output control unit 12 receives the information.
In the configuration information storage medium such as disk and switch in 3,
For example, the one that is manually set via an operation panel for maintenance is used. As a conventional technique for facilitating the setting of such configuration information, for example, a public manual number SC38-0066 issued by IBM Corp.
Are listed in. That is, CTC (Channel)
C such as l to Channel Adapter)
PU (Central Processing Uni)
In the input / output control device with a built-in central processing unit, the link address and logical channel address (LPAR number in this known example) corresponding to each host of the partner processing device determined at the time of system construction are set by the system generation program. It is set in the processing device and stored as configuration information data in a storage device or the like in the processing device. When the power of the processing device is turned on, these address information is given to the CTC.

However, these pieces of configuration information are often not determined until just before the start of operation due to a delay in system construction work, and in this case, the product cannot be shipped from the factory. To prevent this from happening, the user has to decide the system configuration by several months before the start of operation, which is a bottleneck in system construction. Even after the product is shipped, it may be necessary to change the system configuration such as the addition / removal of the processing device, or the configuration information of the input / output control device each time the dynamic switch port fails or is changed. It takes a lot of time and cost including confirmation work for this configuration change, and the operation of the system must be stopped for this purpose. Further, in the serial interface, the processing device and the input / output control device may be connected by an optical fiber cable, and the input / output control device is installed several tens of kilometers away from the center where maintenance personnel are located. In that case, it takes a long time to change the configuration information.

[0007]

The problem to be solved is that the prior art cannot dynamically set the configuration information consisting of the link address of the dynamic switch port and the logical channel address. . An object of the present invention is to solve these problems of the prior art and to dynamically obtain the link address and logical channel address of a dynamic switch port, thereby making it possible to efficiently set or change the configuration information. It is to provide an input / output control device that does.

[0008]

In order to achieve the above object, the input / output control device of the present invention uses (1) a channel based on a transfer destination link address and a transfer source link address in a header of a transfer frame. In the input / output control device that controls the connection between the input / output device and the host channel by the serial interface through the dynamic switch that dynamically controls the connection with the input / output control device, the logical path establishment frame from the host channel The value of the transfer source link address field, the value of the transfer source logical address field, and the value of the transfer destination logical address field are respectively the link address and logical channel address of the dynamic switch port to which the host channel is connected, and the logical path. As the identification information of the input / output device corresponding to A link address table is registered for each, and when the status is transferred from the I / O device to the host channel, the link address and logical channel searched from the link address table using the value of the transfer destination logical address field corresponding to this I / O device as a key. A feature is that a frame for transmission to the host channel is created using the address and is sent to the dynamic switch. (2) In the input / output control device described in (1) above, the device address defined in the host channel and the logical path are used with the identification information of the input / output device arbitrarily determined in the input / output control device as a key item. A first conversion table for registering the value of the transfer destination logical address field in the establishment frame in association with each other is provided, and at the time of status transfer from the input / output control device to the host channel, the identification information of this input / output device is used as a key, The first conversion table is searched to read the value of the transfer destination logical address field in the logical path establishment frame, and the link address table is searched using the read value of the transfer destination logical address field as a key. To do. (3) In the input / output control device described in (2) above, the first conversion table is a block that stores control information indicating an operating state of the input / output device, corresponding to the identification information of the input / output device. When an access request is made from the input / output device to the host channel, the first conversion table is searched using the identification information of the input / output device as a key.
It is characterized in that the address of the block storing the control information of the input / output device is read and the control information of the corresponding input / output device is rewritten. (4) In the input / output control device according to any one of (1) to (3) above,
The address of the block that stores the input / output device identification information and the control information indicating the operating status of the input / output device, using the value of the transfer destination logical address field in the logical path establishment frame and the activated device address as key items. A second conversion table for registering items and items is associated with each other, and when the access request is made from the host channel to the input / output device, the identification information of the host channel and the value of the transfer destination logical address field in the logical path establishment frame are set. With the key, the second conversion table is searched to read the address of the block storing the control information of the input / output device,
The feature is that the control information of the corresponding input / output device is rewritten. (5) In the input / output control device according to any one of (1) to (4) above, an input / output control device control mechanism for independently performing protocol control of a serial interface corresponding to a plurality of host channels is provided. Provided,
It is characterized in that each table is searched by using the logical control device address used as a key to identify each control operation for a plurality of host channels by this input / output control device control mechanism.

[0009]

In the present invention, the values of the transfer source link address field and the transfer source logical address field in the logical path establishment frame from the host are the dynamic switch port to which the host is connected. Focusing on showing the link address and the logical channel address of the I / O controller, I / O control is performed using the values of the transfer source link address field and the transfer source logical address field in these logical path establishment frames. The device side dynamically acquires the configuration information. This eliminates the need to have the link address or logical channel address of the host as the configuration information in the input / output control device, eliminating the need to set the configuration information at the time of factory shipment, thus reducing the configuration setting work cost of the input / output control device. It is possible to reduce the configuration information, facilitate the change of the configuration information, change the configuration information associated with the system configuration change at the user site, reduce the number of additional work steps, and avoid an online planned stoppage.

Further, by using the first address conversion table, the identification of the host concerned and the value of the transfer source logical address field, that is, the logical channel address and the control information storage block of the input / output device are made high speed. Can be searched for, and processing for activation from the input / output device can be performed at high speed. Further, by using the second address translation table, the identification of the relevant input / output device and the control information storage block of the input / output device can be searched at high speed, and the processing for the activation from the host can be performed at high speed. . In addition, the control mechanism of the I / O controller is divided into multiple parts and associated with each host, and by identifying the logical controller address that matches the logical channel address of each host, the connection between multiple hosts and the I / O device is connected. The controls can be performed independently and in parallel.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the configuration of the input / output control device of the present invention according to the present invention.
FIG. 3 is a block diagram showing a specific example of the configuration of a computer system using the same. In FIG. 2, 10a to 10c are processing devices that perform computer processing (in the figure, host CP
U), 11a to 11c are the processing devices 10a to 1
0c is a serial interface serial channel for controlling the external connection, 12 is a cable for the serial interface, 14 is a dynamic switch for dynamically controlling the connection between the serial channels 11a to 11c and the input / output controller 15. Reference numerals 13a to 13f are dynamic switch ports which are the ports for the serial interface cable 12 of the dynamic switch 14, 15a to 15c are input / output control devices according to the present invention, and 16a to 16c are each input / output control device 15a. 15 to 15c, which is a link control mechanism as the input / output control device control mechanism of the present invention for performing serial interface link control with the serial channels 11a to 11c.

As described above, in the computer system having the serial interface, the dynamic switch 14 controls the dynamic connection between the plurality of serial channels 11a to 11c and the input / output control devices 15a to 15c.
The dynamic switch 14 controls connection with each of the dynamic switch ports 13a to 13f according to the value of the transfer destination link address in the data frame to be transferred. Further, when the processing devices 10a to 10c are composed of a plurality of hosts, the serial channels 11a to 11c determine which host the input / output operation is performed by the value of the transfer destination logical address in the data frame. Identify. Therefore, when the status signal is transferred from the input / output control devices 15a to 15c to the processing devices 10a to 10c, the link address and logical channel address of the partner host must be set in the transmission frame.

Conventionally, these pieces of information are set in a configuration information storage medium such as a disk or a switch in the input / output control device upon receiving an instruction from the user when the product is shipped from the factory. I was using it. The input / output control device 15
Reference numeral a denotes a disk device 17, input / output control device 15b controls a communication line 18, and input / output control device 15c controls a printer 19, respectively. CPU: CentralProc
communication control processing device (C) that includes a communication unit and a memory and performs communication control in a program storage system.
CP: Communication Control P
The input / output control device 15b as a processor will be described.

FIG. 3 is a block diagram showing a specific example of the internal configuration of the input / output control device in FIG. This example is a communication control processing device to which the present invention is applied. In this figure, 20 is a communication control processor for performing communication control between lines designated by the processing devices 10a to 10c in FIG. The main storage 22 mainly used by the communication control processor 20 is a service processor 16b for starting the communication control processing device, loading configuration information, initial program load (IPL), failure recovery processing, and the like.
2 is a link control mechanism for performing serial input / output interface protocol control between the serial channels 11a to 11c of the processing devices 10a to 10c in FIG. 2 via the serial interface cable 12; Line control mechanism for interface control, 2
Reference numeral 5 is a hard disk for storing microprograms such as the link control mechanism 16b and the line control mechanism 24, configuration information, and error log information. The hardware system area 26 in the main storage 21 stores the configuration information in the hard disk 25 by the service processor 22 when the power is turned on, and the communication control processor 20 causes the link control mechanism 16b and the line. It is a special area used for communication with the control mechanism 24 and the like.

The link control mechanism 16b in the communication control processing device having such a configuration is capable of operating a plurality of logical control devices (an operation of independently controlling input / output of each of the plurality of processing devices with each host). As described above, a microprocessor, a local memory accessible by the microprocessor, a memory control circuit capable of data transfer with the main memory in the input / output control, a transmission frame register with which the microprocessor can communicate, a reception frame with reference Composed of registers. Then, one logical control device is assigned to one host, a logical control device address (logical address) is given to each logical control device,
The logical address of the logical controller assigned to this host is defined in the logical controller address parameter of the controller definition statement of the input / output device of the system generation of the host.

Then, the communication control processor 20 assigns a device address of its own device for identification of its own device to the link control mechanism 16b in order to specify a communication path with the host, and this device address of the own device belongs to the device. Logical controller address (information indicating which host to communicate with)
And configuration information indicating a logical correspondence between the host and the device address on the host side for identifying the host are prepared in the hard disk 25. The configuration information is loaded into the hardware system area 26 by the service processor 22 when the power of the apparatus is turned on. The link control mechanism 16b reads out this configuration information in its own initialization processing, and based on this, creates the first and second conversion tables in its own memory. The first conversion table stores the corresponding logical control unit address and host side device address using the device address of the own device as a key, and the second conversion table stores the logical control unit address and host device address as a key. The corresponding device address on the device side is stored in −.

The link control mechanism 16b further receives the transfer source link address field and the transfer source logical address field in this frame when the logical path establishment frame transmitted by the logical path establishment procedure is received by the serial channel.
Since the value of each field indicates the link address and the logical channel address of the host, the link address and the logical channel address are specified by the value of the transfer destination logical address field in the frame indicating the logical control unit address. Store and create a link address table. still,
In the logical path establishment procedure, the serial channel autonomously executes for each logical control unit specified by the logical control unit address parameter of the control unit definition statement in the system generation of the host.

When the link control mechanism 16b recognizes the activation from the communication control processor 20 in the device after the initialization process, it reads the first conversion table with the device address of the device itself as a key, Obtain the corresponding logical control unit address and host device address, then read the link address table using the logical control unit address as the key, and obtain the link address and logical channel address that are the physical path information with the host. Ask. Then, the obtained link address is used as the transfer destination link address field of the transmission frame, the logical channel address is used as the transfer destination logical address field, and the logical controller address is used as the transfer source logical address field. , The device address on the host side is set in the device address field, and the frame is transmitted. On the other hand, when the frame is received from the host, the link control mechanism 16b uses the values of the transfer source logical address field and the device address field in the received frame as keys to generate the second conversion table. Is read out to obtain the device address of the device itself, and an interrupt is generated to the communication control processor 20.

As described above, the communication control processing device (input / output control processing device) of the present embodiment has the values of the transfer source link address field and the transfer source logical address field in the logical path establishment frame. Paying attention to the fact that the values respectively indicate the link address and logical channel address of each port of the dynamic switch to which the host is connected, the link control mechanism 16b is divided into a plurality of logical control devices associated with each host. . Then, the communication control processing device is provided with configuration information indicating the correspondence relationship between the device address of the own device activated from the processor of the own device, the device address of the host, and the logical control device address, and the link control mechanism is By associating the first and second conversion tables created based on this information with the link address table storing the logical channel address information and the link address obtained at the time of receiving the logical path establishment frame , Host side link address, logical channel address, host side device address, and own device side device address are converted to each other, so there is no host connection path information in the communication control processing unit (input / output control unit). I'm done.
The detailed configuration of the link control mechanism 16b of such a communication control processing device is shown in FIG. 1, and a detailed description of the present invention will be given below with reference to FIG.

In FIG. 1, 30 is a link control mechanism 1.
The microprocessor 31 performs initialization processing of 6b, start / interrupt processing between communication processors, interface protocol processing of link, and the like, 31 is the microprocessor 3
0 is a local memory for storing various tables and buffers for performing these processes, and 32 is a logical control unit address and a host side from the information of the transmission frame of the communication control processor 20 of FIG. The first conversion table 33 according to the present invention for obtaining the device address is
The second conversion table 34 according to the present invention for obtaining the device address of the communication control processor side device itself from the link address in the frame at the time of frame reception is a logical control device 34 obtained by the first conversion table 32. The port of the dynamic switch mechanism where the host is connected from the address
Link address table 35 according to the present invention for obtaining a link address and a logical channel address
As one step of the initialization process of the link control mechanism 16b, the configuration information area obtained by reading the contents of the configuration information table in the hardware system area 26 in FIG.
Reference numeral 36 is a communication control processor start / interrupt control unit for starting and interrupt control from the communication control processor 20 in FIG. 3, and 37 is the main storage 21 in FIG.
D with (including hardware system area 26)
MA (Dynamic Memory Access)
Main storage DMA control unit for controlling transfer, 38
Is a transmission frame register for creating a frame to be transmitted on the link by the microprocessor 30 for interface control with the host, and 39 is a transmission frame.
The parallel data of the system register 38 is converted to bit serial data.
Data, or bit serial data from the receiving link.
Data converter for converting parallel data into parallel data, 28
Is a receive frame register for holding a frame received from the receive link via the serial-parallel converter 39,
Reference numeral 29 is a device control block that stores the command execution status of the communication path.

As described above, the link control mechanism 16b is provided with a microprocessor 30, a local memory 31 accessible by the microprocessor, and a main storage in the input / output control device so that a plurality of logical control devices can operate. Main memory DMA control unit 37 capable of data transfer between the memory and local memory 31 and communication processor start / interrupt control unit 3 which can be referenced and set by the microprocessor 30.
6 and frame transmission and reception with the link
Transmission frame register 3 for setting and referencing the contents in the frame
8, a reception frame register 28, and a serial-parallel converter 39, and one logical controller is assigned to one host to be connected. A logical control unit address is given to each logical control unit, and the control unit address parameter of the control unit macro is used in the I / O configuration definition of the communication control processing unit by the system generation of the host. Be sure to define the logical controller address assigned to the host.

In order to specify which host the communication control processor 20 in the communication control processor 15b in FIG. 3 communicates with, the device address of the self device associated with the communicating host is assigned to the link control mechanism 16b. ,
In the hard disk 25 managed by the service processor 22 shown in FIG. 3, the configuration information table having the contents shown in FIG.
Bulls are provided in the configuration information area 35.

FIG. 4 is an explanatory diagram showing a configuration example of the configuration information table in the configuration information area in FIG. In the configuration information table 40 of this example, a validity flag field (denoted by V in the drawing) 41 indicating the validity of the record in the configuration information table 40 and a device indicated by the record are recorded. A logical control unit address field (indicated as LGCUA in the figure) 42 indicating the logical control unit address to which it belongs,
A device address field of its own device (described as CCP-DA in the figure) 43 used to identify the communication path indicated by the record, and a device address field of the host side used in channel identification (described as CH-DA in the diagram). ) 44, and shows the corresponding relationship.

The configuration information in the configuration information table 40 is stored in the hard disk 2 by the service processor 22 in FIG. 3 when the communication control processing unit is powered on.
5 is read out and loaded into the hardware system area 26. In FIG. 1, the microprocessor 30 of the link control mechanism 16b activates the main storage DMA controller 37 by loading the above configuration information in the initialization process of itself when the power input is activated (power on). It is loaded into the configuration information area 35 in the cull memory 31, and the first conversion table 32 and the second conversion table 33 whose detailed configurations are shown in FIGS. 5 and 6 are created based on this configuration information. Further, when receiving the logical path establishment frame from the host, the microprocessor 30 reads the reception frame register 28 and creates a link address table 34 whose detailed configuration will be described later with reference to FIG.

FIG. 5 is an explanatory diagram showing a configuration example of the first conversion table in FIG. The first conversion table 50 of this example stores a validity flag field (denoted by V in the figure) 51 indicating the validity of the record and a logical control unit address to which the device indicated by the record belongs. The logical control device address field (shown as LGCUA in the figure) 52 shown, the host-side device address field for channel identification (shown as CH-DA in the figure) 53, and the command execution status of the communication path are stored. A device control block address field (indicated as DCBA in the figure) 54 indicating the address of the device control block, and the own device side device address (CCP-DA) from the communication control processor 20 in FIG. Is associated with. This first conversion table 50
1, the link control mechanism 16b of FIG. 1 uses the device address of its own device from the communication control processor 20 of FIG. 3 as a key, and outputs the corresponding logical control device address and device address of the host, and from the communication control processor. The address of the device control block that manages the command execution state of the device address of its own device and the sense data is obtained.

FIG. 6 is an explanatory diagram showing a configuration example of the second conversion table in FIG. In the second conversion table 60 of this example, a validity flag field (denoted by V in the figure) 61 indicating the validity of the record and a device address field of the own device side corresponding to the device address of the host side. (Indicated as CCP-DA in the figure) 62,
A device control block address field (indicated as DCBA in the figure) 63 indicating the address of the device control block storing the command execution status of the communication path,
Each is associated with a logical control device address (LGCUA) and a self device side device address (CH-DA). The link control mechanism 16b of FIG. 1 uses the logical control unit address (LGCUA) in the receive frame to report it to the communication control processor 20 of FIG. 3 when a command activation frame is received from the host. ) And the device address (CH-DA) of the device itself, and the second
From the conversion table 60, the corresponding device address of the communication control processor side device side and the address of the device control block are obtained.

FIG. 7 is a flow chart showing an example of the processing for creating the first conversion table and the second conversion table in FIGS. Link control mechanism 16 in FIG.
b is initialized by clearing the contents of the first and second conversion tables, the link address table, the configuration information record counter, the device control block address counter, etc. to "0" at power-on startup (power-on). Processing is performed (step 101). Next, the contents of the configuration information table 40 shown in FIG. 4 are read from the hardware system area 26 (HSA) in FIG. 3 (step 10
2). Then, one record is read from this configuration information table (step 103), and it is determined whether the value of the validity flag field (V) of this record is "1" (step 104). If "V = 1", the contents of the record read from the configuration information table are used as the corresponding fields of the first conversion table 50 shown in FIG. 5 with the device address (CCP-DA) of the own device as a key. (Step 105).

Further, the logical control unit address (LGCU
A) and the device address on the host side (CH-DA) as a key, the record contents read from the configuration information table
The corresponding fields of the second conversion table 60 shown in FIG. 6 are written (step 106). Also,
Using the logical controller address (LGCUA) as a key, the validity flag field (V) in the link address table, which will be described in detail in FIG. 8 below, is set to "1" (step 10).
7). Then, the device control block address (DCB
A) The counter and the record counter are incremented by "1" and updated (step 108). If the record counter is not the final value, the next record is read (step 109). In this way, all records in the first conversion table 50 and the second conversion table 60 shown in FIGS. 5 and 6 are registered based on the configuration information table 40 shown in FIG.

FIG. 8 is an explanatory diagram showing a configuration example of the link address table in FIG. In the link address table 70 of this example, a validity flag field (denoted by V in the figure) 71 indicating the validity of the logical control device address and a logical path establishment status between the host communicating with the logical control device are shown. A logical path establishment flag field (indicated by E in the figure) 72 and a link address field (indicated by D-LKA in the figure) 73 indicating the link address of the dynamic switch port to which the host is connected,
When the host is performing a plurality of logical computer operations, a logical channel address field (described as D-LGA in the figure) 74 indicating the logical computer address corresponds to each logical control unit address (LGCUA). It is attached.

When receiving the logical path establishment frame from the host, the microprocessor 30 of the link control mechanism 16b of FIG. 1 reads the received frame and uses the value of the transfer destination logical address field as a key. Link address table 7
0 is set, the value of the transfer source link address in the reception frame is set in the link address field 73, and the value of the transfer source logical address is set in the logical channel address field 74, and a logical path with the host is established. The logical path establishment flag 72 indicating that it has been set is set.

FIG. 9 is a flow chart showing an example of the processing for creating the link address table in FIG. Upon receiving the logical path establishment frame, the microprocessor 30 of the link control mechanism 16b in FIG. 1 receives the transfer destination logical address in the reception frame register and the values of the respective fields of the transfer source link address and the logical address (D-
(LGA, S-LKA, S-LGA) are read (step 111). Then, each read value is written in each corresponding field of the link address table 70 shown in FIG. 8 with the transfer destination logical address value (D-LGA) as a key, and the logic of the link address table 70 is also written. "1" is written in the path establishment flag field (E) (step 112) to create a link address table. Next, the first and second created in this way
The operation of the communication control processing device using the conversion table and the link address table according to the present invention will be described.

FIG. 10 is a sequence diagram showing a first specific example of the processing operation of the link control mechanism in FIG. 1 according to the present invention. This example shows the processing of the link control mechanism 16b until the frame is transferred from the communication control processor 20 in the communication control processing device to the host 10d, and the link control mechanism 16b starts up from the communication control processor 20. When (step 81) is read and recognized by the communication control processor activation / interruption control unit 36, the activation information such as the device address (CCP-DA) of its own device and the command is read (step 82). Then, the first conversion table 50 is accessed by using the device address (CCP-DA) of the own device as a key, and the logical control device address (LG
CUA) and device address on the host side (CH-DA),
And the address of the device control block (DCBA)
Is calculated (step 83). Using this device control block address (DCBA) as a key, the device control block (DCB) 29 is accessed to read the device control information, the status to be sent to the host 10d is determined, and the device state is rewritten (step 84). ).

If it is necessary to send the status to the host 10d, the link address (D-
LKA) and the logical channel address (D-LGA) to obtain the read logical controller address (LGCU).
The link address table 70 is accessed using the key A) (step 85). The link control mechanism 16b obtains the fields of the transfer destination link address, the transfer destination logical address, the transfer source logical address, and the device address of the own device in the transmission frame register 38 by the above-mentioned table access, respectively. Link address of the host (D-LK
A), the logical channel address (D-LGA), the logical control device address (LGCUA), and the host-side device address (CH-DA) are set (step 86) and transmitted to the host side (step 87).

FIG. 11 is a sequence diagram showing a second specific example of the processing operation according to the present invention of the link control mechanism in FIG. This example shows the processing of the link control mechanism 16b until the activation frame is received from the host 10d and interrupts the communication control processor 20, and when the activation from the host 10d to the communication control processing device is performed. (Step 91), the link control mechanism 16b, the transfer destination logical address (D-LGA) in the reception frame register 28, the transfer source link address (S-LKA), the transfer source logical address (S-LGA), the host side. Device address (CH-D
A) is read (step 92).

Then, in order to report to the communication control processor 20 that the activation has occurred, first, the transfer destination logical address (D-LGA) and the host side device address (CH-
DA) as a key to access the second conversion table 60, and the corresponding device address on the device side (CCP-D)
A) and the device control block address (DCBA) are obtained (step 93). Next, the device control block (DCB) is accessed by using the obtained device control block address (DCBA) as a key, and the device state is rewritten according to the activation contents of the host (step 9).
4). Further, the link control mechanism 16b writes the device address (CCP-DA) of its own device in the communication processor start / interrupt control unit 36 (step 95),
An interrupt is generated (step 96). The communication control processor 20 identifies from which host the activation is started by the device address (CCP-DA) of the own device in this interrupt information (step 97).

As described above with reference to FIGS. 1 to 11, in the communication control processing device as the input / output control processing device of this embodiment, a plurality of link control mechanisms in the communication control processing device are provided for each host. Of the host computer, and each logical control device is given a logical address (logical control device address) for addressing from the host. It should be the same as the address specified by the controller address parameter in the system generation controller macro definition statement. Then, in order to address the communication path with the host from the communication control processor side, the device address of the self device (communication control processor) is assigned to the link control mechanism, and the logical control device address of the host and the device address of the self device are assigned. Correspondence is provided as configuration information of the communication control processing device.

In this way, the link control mechanism can associate the logical communication path between the host and the device address on the communication control processor side, and the physical path information between the hosts, that is, The link address and logical channel address information are stored in the communication control processing unit by using the transfer source link address and the logical address of the logical path establishment frame sent from the host for each logical control unit. There is no need to have configuration information such as addresses or logical channel addresses.
As a result, it is possible to reduce the number of man-hours required to set the configuration information at the time of factory shipment, reduce the number of man-hours required to change the settings associated with the change of the system configuration at the user site, and avoid the online planned suspension.

The present invention is not limited to the embodiment described with reference to FIGS. 1 to 11, and various modifications can be made without departing from the scope of the invention. For example, as a desirable usage of the present invention, if the correspondence between the device address on the device side and the logical control device address is fixed and only the device address on the host side is used as the configuration information, there is no difference from the conventional parallel interface. I / O controller can be used.

[0039]

According to the present invention, in the input / output control device for connecting a plurality of hosts by the serial interface via the dynamic switch, the link address and logical channel address of the host are configured in the input / output control device. Since there is no need to have it as information, the cost related to the work of setting the configuration of the input / output control device can be reduced, and the change of the set configuration information due to the change of the system configuration after the start of the user operation and the reduction of the additional work cost Further, it is possible to avoid the planned stoppage of the online system due to the work of changing the configuration information, and it is possible to improve the performance of the computer system using the input / output control device.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a configuration according to the present invention of an input / output control device of the present invention.

FIG. 2 is a block diagram showing a specific example of the configuration of a computer system using the input / output control device of the present invention.

FIG. 3 is a block diagram showing a specific example of the internal configuration of the input / output control device in FIG.

4 is an explanatory diagram showing a configuration example of a configuration information table in a configuration information area in FIG.

5 is an explanatory diagram showing a configuration example of a first conversion table in FIG.

FIG. 6 is an explanatory diagram showing a configuration example of a second conversion table in FIG.

FIG. 7 is a flowchart showing an example of a process of creating a first conversion table and a second conversion table in FIGS. 5 and 6.

8 is an explanatory diagram showing a configuration example of a link address table in FIG.

9 is a flowchart showing an example of a process of creating a link address table in FIG.

10 is a sequence diagram showing a first specific example of the processing operation of the link control mechanism in FIG. 1 according to the present invention.

11 is a sequence diagram showing a second specific example of the processing operation of the link control mechanism in FIG. 1 according to the present invention.

FIG. 12 is a block diagram showing a configuration example of an input / output system using a conventional input / output control device.

[Explanation of symbols]

 10a to 10c Processing device 10d Host 11a to 11c Serial channel 12 Serial interface cable 13a to 13f Dynamic switch port 14 Dynamic switch 15a to 15c Input / output control device 16a to 16c Link control mechanism 17 Disk device 18 Communication line 19 Printer 20 Communication control processor 21 Main storage 22 Service processor 24 Line control mechanism 25 Hard disk 26 Hardware system area 28 Receive frame register 29 Device control block 30 Microprocessor 31 Local memory 32 First Conversion table 33 Second conversion table 34 Link address table 35 Configuration information area 36 Communication control processor start / interrupt control unit 37 Main storage DMA Control part 38 Transmission frame register 39 Serial para converter 40 Configuration information table 41 Validity flag field 42 Logical control device address field 43 Self device side device address field 44 Host side device address field 50 First conversion table 51 Validity flag field 52 logical control device address field 53 host side device address field 54 device control block address field 60 second conversion table 61 validity flag field 62 own device side device address field 63 device control block address field 70 link address table 71 Validity Flag Field 72 Logical Path Establishment Flag Field 73 Link Address Field 74 Logical Channel Address Field 120a-120c Processing device 121a-121d Host 122a-122c Serial channel 123 Input / output control device 124 Dynamic switch

Claims (5)

[Claims] 1. A serial interface input via a dynamic switch for dynamically controlling connection between a channel and an input / output control device based on a transfer destination link address and a transfer source link address in a header of a transfer frame. In the input / output control device that controls the connection between the output device and the host channel, the value of the transfer source link address field and the value of the transfer source logical address field in the logical path establishment frame from the host channel, and the transfer destination logical address A link for registering the value of the field for each logical path as a link address and a logical channel address of the dynamic switch port to which the host channel is connected, and identification information of an input / output device corresponding to the logical path. Address table is provided, and the above-mentioned entry and exit At the time of status transfer from the input device to the host channel, the link channel and the logical channel address retrieved from the link address table are used as a key with the value of the transfer destination logical address field corresponding to the input / output device as the host channel. An input / output control device that creates a frame for transmission to and sends it to the dynamic switch. 2. The input / output control device according to claim 1, wherein the identification information of the input / output device arbitrarily determined in the input / output control device is used as a key item, and a device address defined in the host channel, A first conversion table is provided for registering the value of the transfer destination logical address field in the logical path establishment frame in association with each other, and at the time of status transfer from the input / output control device to the host channel, identification information of the input / output device. With the key as a key, the first conversion table is searched, the value of the transfer destination logical address field in the logical path establishment frame is read, and the value of the read transfer destination logical address field is used as a key.
An input / output control device which searches the link address table. 3. The input / output control device according to claim 2, wherein the first conversion table stores control information indicating an operating state of the input / output device corresponding to identification information of the input / output device. When an access request from the input / output device to the host channel is made, the first conversion table is searched by using the identification information of the input / output device as a key, and the address item of the input / output device An input / output control device characterized by reading an address of a block storing control information and rewriting control information of a corresponding input / output device. 4. The input / output control device according to claim 1, wherein a value of a transfer destination logical address field in the logical path establishment frame and an activated device address are used as key items. , A second conversion table for registering the identification information of the input / output device and the address item of the block storing the control information indicating the operating state of the input / output device in association with each other, When requesting access to the output device, the second conversion table is searched using the identification information of the host channel and the value of the transfer destination logical address field in the logical path establishment frame as a key to control the input / output device. The input is characterized by reading the address of the block storing the information and rewriting the control information of the corresponding input / output device. Output control device. 5. The input / output control device according to claim 1, further comprising input / output control device control means for independently performing protocol control of the serial interface corresponding to a plurality of host channels. An input / output control device, wherein the input / output control device control means is provided to perform a search of each of the tables with a logical control device address used as a key for identifying each control operation for the plurality of host channels.