JPH0744463A - One-chip microcomputer incorporating eeprom - Google Patents

Abstract

PURPOSE:To conduct free rewrite and to inhibit write on the occurrence of a runaway by allowing write to an EEPROM only for a period when a CPU accesses periodically a control circuit. CONSTITUTION:When a CPU is in normal operation, a counter 9 is cleared for each occasion by programming it that a level '1' is written to a timer control register 6 for a predetermined interval shorter than a period set in a 2nd comparison circuit 8 and a write control F/F 10 is set in the write enable state. If the CPU runs away, '1' is not written in the timer control register 6 and the content of the counter 9 is coincident with the content of the 2nd comparison circuit 8, an interrupt request D to the CPU is generated, a stop control F/F 11 is set and a count clock for the counter 9 is set low to stop the counting. Thus, till an interrupt reply E is returned from the CPU, the writing to the EEPROM is never allowed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-chip microcomputer incorporating an EEPROM, which has a function of restricting writing from the microcomputer to the EEPROM.

[0002]

2. Description of the Related Art Conventionally, in a microcomputer including an EEPROM, it has been proposed to prohibit writing to protect the data of the EEPROM when the CPU runs out of control, but it may be restricted in use. For example, in Japanese Patent Laid-Open No. 3-129446, the EEPROM data is protected by setting a write-protected area in a built-in register. However, the CPU runs away due to some abnormality and the write-protected area is set to the write-protected area. If this happens, even if a runaway of the CPU is detected, the writable area cannot be re-set except for a hardware reset, so that it is not possible to utilize the advantage of the EEPROM, and the effect of the built-in EEPROM is diminished. .

[0003]

A conventional microcomputer with a built-in EEPROM can be freely programmed by an E program.
It was possible to write to the EPROM. As clarified in the section of the prior art, in case the microcomputer runs out of control for some reason, it is possible to lose the feature of the EEPROM that the write-protection state is set in order to protect the internal data and rewriting is possible. It was the current response method. The present invention makes it possible to inhibit writing during a runaway while making full use of the feature of the EEPROM that rewriting can be freely performed.

[0004]

The present invention has been made in view of the above problems, and the EEP is provided only while the CPU regularly accesses the control circuit according to the present invention.
By having the function of permitting writing to the ROM, the EEPROM is protected from erroneous writing during abnormal operation. Further, according to the present invention, the built-in EE during normal operation
There is no restriction on writing to the entire area of the PROM. Further, by providing means for permitting writing from the CPU to the EEPROM only for a certain period and means for storing the write address data even for the writing during the period other than the permission period, there is no waiting time for the CPU.
Can perform other processing.

[0005]

According to the present invention, erroneous writing to the built-in EEPROM at the time of CPU runaway can be prohibited by the above means, and the EEPROM can be freely rewritten in other cases, so that the EEP
Data can be protected without losing the features of ROM.

[0006]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram of the present invention. 1
Is a built-in CPU, 2 is a built-in functional block (ROM, RA
M, I / O, etc.), 3 is a write inhibit / read control circuit according to the present invention, and 4 is a built-in EEPROM. 1,
2 and 3 are a read signal A, a write signal B, and a data bus D
B and an address bus AB are connected, and data transfer between 1-2 and 1-3 is possible. Built-in EEPR
Read / write to OM4 is A, B, DB, AB
By the respective signals of, the read A ', the write B', the data DB ', the write DB', and the read control circuit 3 are passed.
The built-in EEPROM 4 is accessed through the address AB '. When a runaway is detected, an interrupt request D is issued to the CPU 1. When the interrupt is accepted, the interrupt response E is returned and the control circuit 3 is initialized.

2, 3, 4, and 5 are detailed embodiments of the present invention.

FIG. 2 shows a runaway detection and EEPROM write permission signal generating section, which includes a timer read / write control section 5, a timer control register 6, first and second compare circuits 7 and 8, a counter 9, and a write control F. / F10, stop control F / F11, and gates.

In the initial state, the write control F / F 10 is cleared by the RESET signal F, the write enable signal J is inactive, and writing to the EEPROM is prohibited. In addition, the timer control register 6
Is initialized, the counter 9 is also reset and the counting operation is stopped. Timer R / W
The control unit 5 decodes AB, A and B output from the CPU to create 7, 8 and 9 read / write signals.

FIG. 3 shows the configurations of the timer R / W controller 5 and the timer control register 6. When the reset signal F becomes active, the prohibition release R shown in FIG. 2 also becomes active, the timer control register 6 and the compare register control F / F 61 are cleared, and writing to the compare circuits 7 and 8 is enabled. . By writing "1" to the timer control register 6 after setting 7 and 8, the compare register control F / F 61 is set, and H becomes inactive. As a result, writing to 7 and 8 is prohibited, and writing to 7 and 8 cannot be performed until the interrupt response E or the reset signal F becomes active. Figure 3
In the figure, only the write signals for 7 and 8 are shown, but the read signal can also be created by the logical product of the output of the address decoder 51 and the read signal A. Clear "H" by writing "1" from the CPU to the timer control register 6 and writing "1" again when the counter 9 is in the operating state.
The set H'becomes active, the counter 9 is initialized, and the write control F / F 10 is also enabled.

FIG. 4 shows the configuration of the compare circuits 7 and 8. A compare register in 7 and 8 is set by the compare register write signal, each bit of the compare register and the counter 9 is matched, and when all the bits match,
It is output as the coincidence signal K. In FIG. 4, only the -sets of the comparison circuits and the like are shown, but the compare circuits 7 and 8 have the same configuration.

FIG. 5 shows the operation timing. Counter 9
Contents of the first compare circuit 7 written by the CPU
If the contents of the above condition match, the write control F / F10 is cleared by the match signal K, the write permission J becomes inactive, and writing to the EEPROM is prohibited. That is, writing to the EEPROM is enabled only for a certain period set in the first compare circuit 7 after the counter starts. Also, one piece of data is EEP
By the write end signal M indicating that the data is written in the ROM,
The write control F / F10 is cleared, and the write prohibition state is set. If the CPU is operating normally, program the timer control register 6 to write "1" at a constant interval shorter than the period set in the second compare circuit 8. 9 is cleared, the write control F / F 10 is set, and the write enabled state is entered.

When the CPU goes out of control and "1" is no longer written in the timer control register 6 and the content of the counter 9 matches the content of the second compare circuit 8, it is recognized as a runaway state,
The interrupt request D to the CPU is generated, the stop control F / F 11 is set, the count clock L for 9 is set to the LOW state, and the count operation of 9 is stopped.
As a result, until the interrupt response E is returned from the CPU, the 9 continues to be in the stopped state, and writing to the EEPROM is not permitted at all. As a result, the EEPROM operates only immediately after the CPU normally operates and clears 9.
Since no data is written to, it is possible to eliminate erroneous writing during runaway.

FIG. 6 shows a read / write operation for the EEPROM.
It is a write control unit.

This block is composed of a memory 13 with a comparator and a control unit 12. Reference numeral 13 includes an address and data storage memory, a tag bit indicating data validity, and a comparator for detecting a match between input and storage addresses. The control unit 12 is composed of a pointer for designating a writing / reading position to the memory 13 with a comparator, a generation circuit of a write end signal M indicating the end of the EEPROM writing, and the like.

When data is written to the EEPROM, if there is no data waiting to be written in the memory 13, the data is written as it is to the EEPROM through A ', B', DB 'and AB'. After the writing is completed, the end of writing M is output from the control unit 12, and the write control F / F
10 is cleared and the write-protected state is set. Memory 13
If there is data waiting to be written in, the data is latched by the memory R / W signal P output from the control unit 12, and a write waiting state is set. At that time, the tag bit in the memory with the comparator is also set, and it is set that writing is waiting. As a result, the presence or absence of writing waiting is determined in the control unit 12 based on the output Q of each tag bit in the memory 13.
At the time when the timer control register 6 is set and the write-enabled state is reached, if the write-waiting data is in the memory 13, the data indicated by the write pointer in the control unit 12 is written in the EEPROM. When the writing is completed, the write pointer in 12 is updated. At the same time, the M signal becomes active, the write permission J becomes inactive, and writing is prohibited. In this way, by writing only one data from the time when the timer is cleared to the time when the timer is next cleared, it is possible to prevent erroneous writing of the data written in the memory 13 during a runaway.

Furthermore, when a read request for the same address is written in 13 while waiting for writing to the EEPROM, the effective storage address (determined by the tag bit) in the input address memory 13 and the comparator are always compared. Since it is done, if there is the same address, the memory 13
Output the data in. If it is not in the buffer, data is read from the control unit to the EEPROM. This feature ensures data consistency.

[0019]

As described in detail above, according to the present invention, the EEPROM is not restricted during normal operation.
Can be written, and erroneous data can be prohibited from being written in the built-in EEPROM when the CPU runs out of control.
The data in the PROM can be protected.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a one-chip microcomputer containing an EEPROM embodying the present invention.

FIG. 2 is a configuration diagram of a runaway detection and EEPROM write permission signal generation unit.

FIG. 3 is a detailed configuration diagram of a timer R / W control unit and a timer control register.

FIG. 4 is a detailed configuration diagram of a compare circuit.

FIG. 5 is an operation timing chart of the present invention.

FIG. 6 is a configuration diagram of a read / write control unit for the EEPROM.

[Explanation of symbols]

 1 CPU 3 write inhibit and read control circuit 4 EEPROM

Claims (2)

[Claims] 1. An EEPROM having a built-in EEPROM, further comprising: a runaway detecting means; and a means for inhibiting writing to the EEPROM on the basis of a runaway detection signal from the means.
1-chip microcomputer with built-in ROM. 2. A one-chip microcomputer having a built-in EEPROM is provided with means for permitting writing to the EEPROM only during a preset period and for inhibiting writing to the EEPROM during periods other than the permitted period. A one-chip microcomputer with a built-in EEPROM.