JPH0740603B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0740603B2 JPH0740603B2 JP60022924A JP2292485A JPH0740603B2 JP H0740603 B2 JPH0740603 B2 JP H0740603B2 JP 60022924 A JP60022924 A JP 60022924A JP 2292485 A JP2292485 A JP 2292485A JP H0740603 B2 JPH0740603 B2 JP H0740603B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- substrate
- semiconductor device
- mirror
- surface side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 78
- 238000000034 method Methods 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000000758 substrate Substances 0.000 claims description 50
- 238000010438 heat treatment Methods 0.000 claims description 11
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 11
- 238000005498 polishing Methods 0.000 claims description 9
- 230000003746 surface roughness Effects 0.000 claims description 7
- 238000005406 washing Methods 0.000 claims description 5
- 238000001035 drying Methods 0.000 claims description 4
- 239000000428 dust Substances 0.000 claims description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 2
- 239000013078 crystal Substances 0.000 description 20
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 17
- 150000001875 compounds Chemical class 0.000 description 8
- 230000003287 optical effect Effects 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 238000005253 cladding Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 230000018044 dehydration Effects 0.000 description 2
- 238000006297 dehydration reaction Methods 0.000 description 2
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- 229910000661 Mercury cadmium telluride Inorganic materials 0.000 description 1
- 241000700560 Molluscum contagiosum virus Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000572 ellipsometry Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000005871 repellent Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
- H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/10—Integrated devices
- H10F39/103—Integrated devices the at least one element covered by H10F30/00 having potential barriers, e.g. integrated devices comprising photodiodes or phototransistors
Landscapes
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、発光素子や受光素子等の光半導体素子と電子
素子とを一体形成した半導体装置の製造方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device in which an optical semiconductor element such as a light emitting element or a light receiving element and an electronic element are integrally formed.
半導体レーザ(LD),発光ダイオード(LED),光検出
器等の発・受光デバイスと、FET,バイポーラトランジス
タ等の電子デバイスとを同一基板上にモノリシックに集
積化した、所謂集積化光デバイスは、動作の高速化がは
かれることによる性能向上,集積化による信頼性向上,
コストダウン等の多くの長所を有するため、光通信の分
野でのその実現が望まれている。また、半導体電子デバ
イスの高速化に伴い、高密度に集積化されたLSIチップ
間の信号伝達遅延が無視できなくなりつつある。このた
め、LSIチップ上に光半導体デバイスをモノリシックに
集積化し、電気信号に変えて光信号によりチップ間の信
号伝送を行うことが論理演算回路の高速化をはかる上で
極めて有力な手段となる。このような点から、発・受光
デバイスを電子デバイスと同一基板上にモノリシックに
集積化する技術の実現が強く望まれている。A so-called integrated optical device in which a light emitting / receiving device such as a semiconductor laser (LD), a light emitting diode (LED), and a photodetector and an electronic device such as a FET and a bipolar transistor are monolithically integrated on the same substrate is Performance improvement due to high-speed operation, reliability improvement due to integration,
Since it has many advantages such as cost reduction, its realization in the field of optical communication is desired. In addition, with the increase in speed of semiconductor electronic devices, the signal transmission delay between high-density integrated LSI chips is becoming non-negligible. For this reason, monolithically integrating optical semiconductor devices on an LSI chip and performing signal transmission between chips by optical signals instead of electrical signals is an extremely effective means for increasing the speed of a logical operation circuit. From this point of view, it is strongly desired to realize a technique for monolithically integrating a light emitting / receiving device on the same substrate as an electronic device.
しかしながら、電子デバイスが形成されているSi基板
と、発・受光デバイスを構成する直接遷移型のGaAs,GaA
lAs,InP,InGaAsP,InGaAs等の化合物半導体混晶とは格子
定数が著しく異なるため、Si基板上にエピタキシャル成
長法によって高品質な上記化合物半導体混晶を得ること
は極めて困難である。即ち、両者の格子定数が異なるた
めに、結晶成長界面に転位等の格子欠陥が高密度に導入
され、これらが結晶成長と共に、エピタキシャル成長層
中にも侵入し、非発光結合中心として働く結果、特に発
・受光デバイスにおいては発光効率,受光感度の低下や
素子寿命の劣化を招き、素子特性に致命的な悪影響を与
えていた。このことが、発・受光デバイスを電子デバイ
スと同一基板上に集積化する上での大きな障害になって
いる。However, the Si substrate on which electronic devices are formed and the direct transition type GaAs, GaA that constitutes the light emitting and receiving devices.
Since the lattice constant is remarkably different from that of the compound semiconductor mixed crystal such as lAs, InP, InGaAsP and InGaAs, it is extremely difficult to obtain the above compound semiconductor mixed crystal of high quality on the Si substrate by the epitaxial growth method. That is, since the lattice constants of the two are different, lattice defects such as dislocations are introduced at a high density at the crystal growth interface, and these penetrate into the epitaxial growth layer together with the crystal growth, and as a result, they act as non-radiative coupling centers. In the light emitting / receiving device, the luminous efficiency and the light receiving sensitivity are deteriorated and the device life is deteriorated, which has a fatal adverse effect on the device characteristics. This is a major obstacle in integrating the light emitting / receiving device with the electronic device on the same substrate.
一方、電子デバイスの形成された半導体基板と発・受光
デバイスの形成された半導体基板とを電極を介して積層
一体化した従来のハイブリッド集積回路は、容易に実現
できるが、この場合配線が長くなったり接触部の電極面
積が大きくなったりする。このため、モノリシック集積
化半導体装置に比べて寄生容量やインダクタンスが大き
くなり、素子本来の性能を引出せないという欠点があっ
た。On the other hand, a conventional hybrid integrated circuit in which a semiconductor substrate on which an electronic device is formed and a semiconductor substrate on which a light emitting / receiving device is formed are laminated and integrated via electrodes can be easily realized, but in this case the wiring becomes long. Or the electrode area of the contact part becomes large. Therefore, the parasitic capacitance and the inductance are larger than those of the monolithic integrated semiconductor device, and there is a drawback that the original performance of the element cannot be obtained.
本発明は上記の事情を考慮してなされたもので、その目
的とするところは、従来のエピタキシャルによらず、発
・受光デバイスと電子デバイスとの集積一体化を容易に
行うことのできる半導体装置の製造方法を提供すること
にある。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device that can easily integrate and integrate a light emitting / receiving device and an electronic device without using a conventional epitaxial method. It is to provide a manufacturing method of.
本発明の骨子は、化合物半導体混晶等により形成された
発・受光デバイスを、これと格子定数が極めて近い半導
体基板上に形成し、これを電子デバイスの形成に適した
半導体基板上に接合させることにより、発・受光デバイ
スと電子デバイスとを集積一体化することにある。The essence of the present invention is to form a light emitting / receiving device formed of a compound semiconductor mixed crystal or the like on a semiconductor substrate having a lattice constant extremely close to that of the light emitting / receiving device, and to bond it to a semiconductor substrate suitable for forming an electronic device. Thus, the light emitting / receiving device and the electronic device are integrated and integrated.
本発明者等は、2種の異なる結晶体、例えば発・受光デ
バイスの形成された化合物半導体混晶基板表面と電子デ
バイスの形成に適したSi基板表面とが、表面粗さ500
[Å]以下の平坦面である場合、それら表面を水洗・乾
燥した後、これらを例えばゴミ浮遊量20[個/m3]以下
のクリーンルーム内で、上記各平坦表面間に実質的に異
物が介入しない条件下で相互に密着させて200[℃]以
上の温度で加熱することによって、2つの結晶体が強固
に接合することを見出した。The inventors of the present invention have found that two different types of crystal bodies, for example, a compound semiconductor mixed crystal substrate surface on which a light emitting / receiving device is formed and a Si substrate surface suitable for forming an electronic device have a surface roughness of 500.
In the case of flat surfaces of [Å] or less, after washing and drying those surfaces, for example, in a clean room with a dust floating amount of 20 [pieces / m 3 ] or less, substantially no foreign matter is present between the flat surfaces. It has been found that the two crystals are strongly bonded by bringing them into close contact with each other and heating at a temperature of 200 [° C.] or more under the condition of not intervening.
従来、鏡面研磨された半導体ウェハ同志を水やアルコー
ル等で濡れた状態で接触させると、両者が接着する現象
はしばしば経験するところである。しかしながら、これ
は水等の液体の表面張力によるものであり、乾燥させた
ウェハでは観察されていない。本発明者等は、鏡面研磨
されたGaAs,InP等の化合物半導体やシリコンの表面を十
分に清浄にし、且つ高度にクリーンな雰囲気の下で同種
或いは異種の2つの面を接触させると強固な接合体が得
られることを見出した。さらに、このようにして得られ
た接合体の接着強度を十分と高めるには、200[℃]以
上の熱処理が必須であることが判った。この接着の現象
を更に詳しく調べた結果、これら結晶の表面に自然酸化
膜が形成されていることが接着させるための必須の条件
であることが判った。この自然酸化膜の存在は、例えば
エリプソメトリー等の方法で確められるが、より簡便に
は清浄化された表面に水滴を置き、それが広がることで
容易に判定できる。即ち、表面が揮発性から親水性に変
わることが自然酸化膜の存在の証拠になる。この自然酸
化膜はさまざまな条件下で形成されるが、本発明者等の
実験によれば高々数分の通常の水洗工程で十分であっ
た。Conventionally, when mirror-polished semiconductor wafers are brought into contact with each other in a wet state with water, alcohol or the like, a phenomenon in which the two adhere to each other is often experienced. However, this is due to the surface tension of liquids such as water and has not been observed on dried wafers. The inventors of the present invention have made the surface of a compound semiconductor such as GaAs, InP or the like, which has been mirror-polished, or silicon surfaces sufficiently clean, and when two surfaces of the same kind or different kinds are brought into contact with each other under a highly clean atmosphere, a strong bond is obtained. It was found that the body can be obtained. Furthermore, it has been found that a heat treatment of 200 [° C.] or higher is indispensable in order to sufficiently enhance the adhesive strength of the bonded body thus obtained. As a result of further detailed investigation of this adhesion phenomenon, it was found that the formation of a natural oxide film on the surface of these crystals is an essential condition for adhesion. The presence of this natural oxide film is confirmed by, for example, a method such as ellipsometry, but more simply, it can be easily determined by placing a water droplet on the cleaned surface and spreading it. That is, the change of the surface from volatile to hydrophilic is evidence of the existence of a natural oxide film. This natural oxide film is formed under various conditions, but according to the experiments conducted by the present inventors, a normal water washing step of at most several minutes was sufficient.
このようにして得られた親水性且つ正常な面を持つウェ
ハ同志は容易に接着できるのに対し、例えば弗酸等に浸
漬して自然酸化膜を除去し、さらに再び自然酸化膜が形
成されないよう注意深く取扱い、表面が発水性を保って
いる面について接着を試みたが、十分な接着体が得られ
ないことが判った。また、十分な接着強度を得るために
200[℃]以上の熱処理が必要な理由は、この温度付近
で自然酸化膜の表面に存在する活性なOH基同志が反応
し、半導体−O−半導体の強固な結合を作るためと考え
られる。なお、このようにして接着された半導体同志は
電気的に導通状態になることも確認された。While the wafers thus obtained having hydrophilic and normal surfaces can be easily bonded to each other, the natural oxide film is removed by immersing it in hydrofluoric acid or the like so that the natural oxide film is not formed again. After careful handling, an attempt was made to adhere to the surface having a water-repellent surface, but it was found that a sufficient adhesive body could not be obtained. Also, to obtain sufficient adhesive strength
It is considered that the reason why the heat treatment of 200 [° C.] or more is necessary is that active OH groups existing on the surface of the natural oxide film react around this temperature to form a strong bond of semiconductor-O-semiconductor. In addition, it was also confirmed that the semiconductors bonded in this way are electrically connected.
本発明はこのような点に着目し、発光素子及び受光素子
等の光半導体素子と通常の電子素子とを含む半導体装置
の製造方法において、第1の半導体基板の表面側に半導
体発光素子或いは半導体受光素子を形成し且つその表面
側を平坦化し、第2の半導体基板の表面側に電子素子を
形成し且つその表面側を平坦化し、次いで上記平坦化さ
れた平坦面を水洗したのち乾燥し、しかるのち清浄な雰
囲気下で上記各平坦面を直接密着させ、この状態で200
[℃]以上の温度で熱処理して各基板同志を接着するよ
うにした方法である。The present invention focuses on such a point, and in a method of manufacturing a semiconductor device including an optical semiconductor element such as a light emitting element and a light receiving element and an ordinary electronic element, a semiconductor light emitting element or a semiconductor is provided on the front surface side of a first semiconductor substrate. Forming a light receiving element and flattening the surface side thereof, forming an electronic element on the surface side of the second semiconductor substrate and flattening the surface side thereof, and then washing the flattened flat surface with water and then drying; Then, in a clean atmosphere, directly attach the above flat surfaces to each other, and
This is a method in which each substrate is bonded by heat treatment at a temperature of [° C.] or higher.
本発明によれば、発・受光デバイスと電子デバイスとを
独立なプロセスで製造できるので、その製造が極めて容
易となる。また、それぞれの素子の特性を最適化するこ
とができるので、一体化後の素子性能を従来のモノリシ
ック光電子集積化半導体装置に比べて大幅に向上させる
ことができる。さらに、接着面は鏡面研磨されたままの
面なので、上部に電極や絶縁膜の凸部がなく、接着は容
易である。しかも、不要な電極が接着面にないため、寄
生容量を減らすことができる。この効果は、特に半絶縁
性基板を用いると顕著に現われる。According to the present invention, since the light emitting / receiving device and the electronic device can be manufactured by independent processes, the manufacturing thereof becomes extremely easy. Further, since the characteristics of each element can be optimized, the element performance after integration can be greatly improved as compared with the conventional monolithic optoelectronic integrated semiconductor device. Further, since the bonding surface is a mirror-polished surface, there is no convex portion of the electrode or the insulating film on the upper portion, and the bonding is easy. Moreover, since there is no unnecessary electrode on the adhesive surface, the parasitic capacitance can be reduced. This effect is particularly remarkable when a semi-insulating substrate is used.
また、従来のエピタキシャル成長法によることなく、電
子デバイスの形成に適した、例えばSi基板上に別基板上
に形成した化合物半導体混晶発・受光デバイスを集積化
形成できるので、両者の格子定数が著しく異なる場合で
も、良好な結晶により発・受光デバイスを構成でき、こ
れらのデバイスの特性劣化を招くこともない。このた
め、格子定数の差異にとらわれることなく、発・受光デ
バイス及び電子デバイスそれぞれに適した基板上にそれ
らを形成することができ、発・受光デバイス−電子デバ
イス集積化デバイスの特性の向上及び組合わせ自由度の
拡大による応用範囲の拡大をはかることができる。その
結果、これらデバイスを利用した光通信及び計算機の分
野に与える効果は絶大である。Further, since it is possible to integrate and form a compound semiconductor mixed crystal emitting / receiving device, which is suitable for forming an electronic device, for example, on a Si substrate and formed on another substrate, without using the conventional epitaxial growth method, the lattice constants of both are significantly increased. Even if they are different, a light emitting / receiving device can be formed of a good crystal, and the characteristics of these devices are not deteriorated. Therefore, it is possible to form them on a substrate suitable for each of the light emitting / receiving device and the electronic device without being affected by the difference in lattice constant, and it is possible to improve the characteristics of the light emitting / receiving device-electronic device integrated device and to combine them. The range of application can be expanded by expanding the degree of freedom in alignment. As a result, the effects on the fields of optical communication and computers using these devices are enormous.
まず、実施例を説明する前に、本発明の基本原理につい
て説明する。First, before describing the embodiments, the basic principle of the present invention will be described.
従来、ガラス板の平滑な面を極めて正常に保ち、このよ
うな2枚のガラス板を直接密着させると、その間の摩擦
係数が増大して接合状態が得られることが知られてい
る。そして、これに逆らって上記ガラス板の面同志を滑
らすと、その接合面のむしり取りによるクラックが発生
することも知られている。これに対して従来、半導体結
晶体同志の上記ガラスの如き接合法が知られていないこ
とは、半導体結晶体の接合すべき面の平滑性とその清浄
性を厳密に保つころが難しかったことが最大の原因であ
ったと言える。Conventionally, it is known that when the smooth surface of a glass plate is kept extremely normal and such two glass plates are directly brought into close contact with each other, the friction coefficient between them is increased and a bonded state is obtained. It is also known that when the surfaces of the glass plates are slid against each other, cracks are generated due to the peeling of the bonding surface. On the other hand, it has been difficult to keep the smoothness and the cleanliness of the surfaces of the semiconductor crystals to be bonded strictly because the bonding method of the above-mentioned glass of semiconductor crystals is not known. It can be said that it was the biggest cause.
そこで本発明者等は、次のような処理を施すことによ
り、ガラス同志の接合のように半導体結晶体同志の接合
も可能なことを見出した。即ち、2つの半導体結晶体の
接合すべき面を表面粗さ500[Å]以下に平滑化し、5
分間水洗した。平滑化の方法は、鏡面研磨或いは鏡面研
磨した表面上にその平坦さを損わない方法、例えばMOCV
D法或いはMBE法によってエピタキシャル成長層を形成し
て行う。得られた半導体の面は水に良く濡れ、自然酸化
物の層が形成されていることが推定された。その後、メ
タノール置換、フレオン乾燥を行い、このようにして得
られた半導体結晶体を、ゴミ浮遊量20[個/m3]の実質
的にゴミのないクリーンルーム中で上記接合面を相互に
直接密着させて200[℃]以上の温度で熱処理したとこ
ろ、両者は極めて強固に接合した。この接合体の接着強
度は、熱処理温度200[℃]以上で特に著しく上昇す
る。Therefore, the present inventors have found that the semiconductor crystal members can be bonded to each other like the glass members by performing the following process. That is, the surfaces to be joined of the two semiconductor crystal bodies are smoothed to have a surface roughness of 500 [Å] or less, and 5
It was washed with water for a minute. The smoothing method is a mirror-polished method or a method that does not impair the flatness on the mirror-polished surface, such as MOCV.
The epitaxial growth layer is formed by the D method or the MBE method. It was presumed that the surface of the obtained semiconductor was well wetted with water and a layer of natural oxide was formed. After that, methanol replacement and freon drying are performed, and the semiconductor crystal bodies thus obtained are directly adhered to each other in the above-mentioned bonding surface in a substantially dust-free clean room with a dust floating amount of 20 [pieces / m 3 ]. Then, when heat-treated at a temperature of 200 [° C.] or higher, the two were extremely strongly bonded. The adhesive strength of this bonded body increases remarkably at a heat treatment temperature of 200 ° C. or higher.
以上のことから、研磨した清浄な半導体の面は水洗だけ
で表面が親水性となり、清浄な環境下で且つ200[℃]
以上の温度下で接合すれば強固に接着体を得ることがで
きる。From the above, the surface of a clean, polished semiconductor becomes hydrophilic only by washing with water, and the surface becomes 200 [° C] in a clean environment.
If bonded under the above temperature, an adhesive body can be strongly obtained.
一方、200[℃]程度の加熱温度では、半導体構成原子
ついてはもとより、最も拡散し易い1価イオンでも、半
導体結晶中における拡散速度は通常無視できる程度に小
さいことは周知である。On the other hand, at a heating temperature of about 200 ° C., it is well known that the diffusion rate in a semiconductor crystal is usually small enough to be ignored, not only for the semiconductor constituent atoms but also for the most easily diffused monovalent ions.
また、この200[℃]付近の温度では、酸化膜の表面に
吸着された水分子が殆ど脱離し、化学吸着により形成さ
れた−OH基の脱水結合が起こり始めることも知られてい
る。これらのことを考え合わせれば、前記半導体結晶体
相互の結合は、金属同志の接合として知られている相互
拡散によるものではなく、半導体結晶体の表面酸化膜の
水和層間の相互作用や、−OH基の脱水重合によって半導
体−OH−半導体なる強固な接合構造を成しているものと
考えられる。It is also known that at a temperature of around 200 [° C.], most of the water molecules adsorbed on the surface of the oxide film are desorbed, and the dehydration bond of the —OH group formed by chemisorption starts to occur. Considering these facts, the mutual bonding of the semiconductor crystal bodies is not due to mutual diffusion known as metal-metal bonding, but the interaction between hydrated layers of the surface oxide film of the semiconductor crystal body, It is considered that a strong junction structure of semiconductor-OH-semiconductor is formed by dehydration polymerization of OH groups.
このような事実は、半導体結晶体の表面を親水性にし、
その密着接合後に200[℃]以上の加熱処理を施せば、
高い接着強度が得られることを意味している。This fact makes the surface of the semiconductor crystal hydrophilic,
If heat treatment of 200 [℃] or more is performed after the close bonding,
This means that high adhesive strength can be obtained.
以下、本発明の詳細を図示の実施例によって説明する。Hereinafter, the details of the present invention will be described with reference to the illustrated embodiments.
第1図(a)〜(e)は本発明の一実施例に係わる半導
体装置の製造工程を示す斜視図及び側面図である。この
実施例は、GaAlAs系半導体レーザと電子デバイスとを集
積一体化し、モノリシックに形成したものである。1A to 1E are a perspective view and a side view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. In this embodiment, a GaAlAs semiconductor laser and an electronic device are integrated and monolithically formed.
まず、第1図(a)に示す如くN−GaAs基板11の上面を
表面粗さ500[Å]以下に鏡面研磨したのち、この基板1
1上にN−Ga0.65Al0.35Asクラッド層12,アンドープGaAs
活性層13,P−Ga0.65Al0.35Asクラッド層14及びN−GaAs
コンタクト層15を順次成長形成する。このとき、成長層
表面が当初の鏡面研磨した基板表面の平坦性を損うこと
のないようMOCVD法或いはMBE法によって成長形成するこ
とが望ましい。First, as shown in FIG. 1 (a), the upper surface of the N-GaAs substrate 11 is mirror-polished to have a surface roughness of 500 [Å] or less, and then the substrate 1
N-Ga 0.65 Al 0.35 As cladding layer 12, undoped GaAs on 1
Active layer 13, P-Ga 0.65 Al 0.35 As cladding layer 14 and N-GaAs
The contact layer 15 is sequentially grown and formed. At this time, it is preferable that the growth layer is grown and formed by the MOCVD method or the MBE method so as not to impair the flatness of the initially mirror-polished substrate surface.
次いで、SiNをマスクとして、第1図(b)に示す如く
幅5[μm]程度のストライプ状部分の表面にZn拡散を
行い、N−GaAsコンタクト層15の一部をP型化してP−
GaAsコンタクト層16を形成する。これは、GaAs活性層13
に流れる電流をストライプ状に狭窄するためのものであ
る。Then, using SiN as a mask, Zn diffusion is performed on the surface of a stripe-shaped portion having a width of about 5 [μm] as shown in FIG.
The GaAs contact layer 16 is formed. This is the GaAs active layer 13
It is for narrowing the current flowing through the stripes.
次いで、フォトレジスト等をマスクとして、BCl3+Cl2
混合ガスによる反応性イオンエッチング法により、第1
図(c)に示す如く電流ストライプ(P型コンタクト
層)16と垂直に共振器端面18を形成すると共に、不要な
部分をエッチング除去する。これにより、半導体レーザ
基体10が形成される。Then, using the photoresist as a mask, BCl 3 + Cl 2
First by reactive ion etching method with mixed gas
As shown in FIG. 3C, the resonator end face 18 is formed perpendicular to the current stripe (P-type contact layer) 16 and the unnecessary portion is removed by etching. As a result, the semiconductor laser substrate 10 is formed.
次に、第1図(d)に示す如く、電子デバイスの製造に
適したSi基板19の表面を表面粗さ500[Å]以下に鏡面
研磨し、先に述べた手順により、半導体レーザ基体10と
接着した。熱処理は、H2雰囲気中500[℃]で1時間行
った。また、Si基板19としては、B等の適当な不純物の
イオン打込み或いは拡散により、表面をP型伝導とした
ものを用いた。かくして、Si基板19上にGaAs−GaAlAs半
導体レーザが得られることになる。Next, as shown in FIG. 1 (d), the surface of the Si substrate 19 suitable for manufacturing an electronic device is mirror-polished to have a surface roughness of 500 [Å] or less, and the semiconductor laser substrate 10 is manufactured by the procedure described above. I glued it. The heat treatment was performed at 500 [° C.] in H 2 atmosphere for 1 hour. Further, as the Si substrate 19, a substrate whose surface is P-type conductive by ion implantation or diffusion of an appropriate impurity such as B is used. Thus, a GaAs-GaAlAs semiconductor laser can be obtained on the Si substrate 19.
なお、Si基板19上に形成する電子デバイスは、上記の接
着工程前に予め形成しておくのが望ましい。また、必要
があれば、NH4−H2O2−H2O系等のエッチング液を用い
て、第1図(e)に示す如くN−GaAs基板11を最終的に
除去するようにしてもよい。The electronic device formed on the Si substrate 19 is preferably formed in advance before the above-mentioned bonding step. If necessary, the N-GaAs substrate 11 is finally removed by using an etching solution such as NH 4 —H 2 O 2 —H 2 O system as shown in FIG. 1 (e). Good.
かくして得られた半導体装置においては、半導体レーザ
10が良好な特性を示し、またP−GaAsコンタクト層16と
P型Si基板19の表面とは良好な電気伝達特性を示した。
従って本実施例によれば、半導体レーザと通常の電子デ
バイスとをモノリシックに形成することができ、しかも
半導体レーザ及び電子デバイスをそれぞれ単体で作製し
たときと同等の特性にすることができる。このため、半
導体レーザー電子デバイスの集積化デバイスの特性の向
上及び組合わせ自由度の拡大をはかることができ、光通
信の分野に与える効果は絶大である。In the semiconductor device thus obtained, a semiconductor laser
No. 10 showed good characteristics, and the P-GaAs contact layer 16 and the surface of the P-type Si substrate 19 showed good electric transfer characteristics.
Therefore, according to this embodiment, the semiconductor laser and the ordinary electronic device can be formed monolithically, and the characteristics can be the same as those obtained when the semiconductor laser and the electronic device are individually manufactured. Therefore, the characteristics of the integrated device of the semiconductor laser electronic device can be improved and the degree of freedom in combination can be increased, and the effect on the field of optical communication is great.
第2図(a)〜(h)は他の実施例に係わる半導体装置
の製造工程を示す断面図である。この実施例は、InGaAs
P系半導体レーザとこのレーザを駆動するGaAs系MESFET
とを集積一体化したものである。2A to 2H are cross-sectional views showing the manufacturing process of a semiconductor device according to another embodiment. In this example, InGaAs
P-based semiconductor laser and GaAs-based MESFET driving this laser
It is an integrated integration of and.
まず、第2図(a)に示す如く、半絶縁性InP基板21の
表面に凹部22を形成し、この凹部22内に同図(b)に示
す如くP+−In1-uGauASvP1-v電極取出し層23,P−InPクラ
ッド層24,アンドープIn1-xGaxASyP1-y活性層25及びN−
InPクラッド層26を順次成長形成する。First, as shown in FIG. 2 (a), a recess 22 is formed on the surface of a semi-insulating InP substrate 21, and in this recess 22, as shown in FIG. 2 (b), P + -In 1-u Ga u AS v P 1-v electrode extraction layer 23, P-InP clad layer 24, undoped In 1-x Ga x AS y P 1-y active layer 25 and N-
The InP clad layer 26 is sequentially grown and formed.
次いで、第2図(c)に示す如くクラッド層24,26及び
活性層25を、レーザ発振領域部を除いてメサエッチング
し、その後同図(d)に示す如くメサの側部をN−InP
埋込み層27及びP−InP埋込み層28で埋込んだ。次い
で、第2図(e)に示す如く凹部22内の不要部を全てメ
サエッチングで除去し、最後にP+型電極取出し層23上に
オーミック電極29を形成する。これにより、半導体レー
ザ基体20が形成されることになる。Next, as shown in FIG. 2 (c), the cladding layers 24, 26 and the active layer 25 are mesa-etched except for the laser oscillation region portion, and then the side portions of the mesa are N-InP as shown in FIG. 2 (d).
The buried layer 27 and the P-InP buried layer 28 were buried. Next, as shown in FIG. 2 (e), all unnecessary portions in the recess 22 are removed by mesa etching, and finally an ohmic electrode 29 is formed on the P + -type electrode extraction layer 23. As a result, the semiconductor laser substrate 20 is formed.
ここで、成長するメサ部の高さは略凹部22の外側と同じ
高さになるよう調整し、最後の鏡面研磨で完全に同一高
さとする。図には示さないが、最後に研磨を行うため
に、半導体レーザ基体及び後述する電子素子部基体共に
凹部内の素子主要部には、必要に応じて研磨の前に保護
膜を付けるものとする。Here, the height of the growing mesa portion is adjusted to be substantially the same as the outside of the concave portion 22, and the same height is obtained by the final mirror polishing. Although not shown in the figure, in order to carry out polishing lastly, a protective film is to be attached to the semiconductor laser substrate and the electronic element substrate described later on the element main portion in the recess before polishing if necessary. .
一方、第2図(f)に示す如く半絶縁性GaAs基板31上に
凹部32を形成し、この凹部32の表面にSiイオン注入でN
型活性層33を形成する。次いで、第2図(g)に示す如
くゲート部ショットキー電極34をFETチャネル部上部に
作り、該ゲート電極をマスクとしてN+型領域35をイオン
注入で形成し、ソース電極36を作製する。これにより、
電子デバイス基体30が形成されることになる。On the other hand, a recess 32 is formed on the semi-insulating GaAs substrate 31 as shown in FIG.
The mold active layer 33 is formed. Then, as shown in FIG. 2 (g), a gate Schottky electrode 34 is formed on the upper portion of the FET channel, and an N + type region 35 is formed by ion implantation using the gate electrode as a mask to form a source electrode 36. This allows
The electronic device substrate 30 will be formed.
以上のようにして作製した基体20,30の表面を鏡面研磨
して、先に述べた手順により水洗洗浄後位置合わせして
圧着すると、2つの基体は一体の半導体装置となる。こ
こで、鏡面研磨は表面粗さが500[Å]以下となる条件
とし、熱処理はH2雰囲気中500[℃]で1時間行った。When the surfaces of the bases 20 and 30 manufactured as described above are mirror-polished, washed with water and aligned and then pressure-bonded by the procedure described above, the two bases become an integrated semiconductor device. Here, the mirror polishing was performed under the condition that the surface roughness was 500 [Å] or less, and the heat treatment was performed in an H 2 atmosphere at 500 [° C] for 1 hour.
かくして製造された半導体装置は、製造方法が簡単であ
るため、製造歩留りや信頼性が高く、また半導体レーザ
と電子デバイスとの特性をそれぞれ最適化することがで
きる。さらに、半導体レーザのN−InPクラッド層26と
電子デバイスのN+型層35との接続配線が不要となり、寄
生容量等も小さくできる構造を持つので、高いパフォー
マンスを有する。Since the semiconductor device thus manufactured has a simple manufacturing method, the manufacturing yield and reliability are high, and the characteristics of the semiconductor laser and the electronic device can be optimized respectively. Further, since the connection wiring between the N-InP clad layer 26 of the semiconductor laser and the N + type layer 35 of the electronic device is unnecessary, and the structure in which the parasitic capacitance and the like can be reduced, high performance is achieved.
なお、本発明は上述した各実施例に限定されるものでは
ない。例えば、前記発・受光デバイスとしては、半導体
レーザの代りに発光ダイオード、PINフォトダイオード
及びアバランシェフォトダイオード等を用いることが可
能であり、またそれらの材料としてはGaAs/GaAlAs,InP/
InGaAsP等のIII−V族化合半導体の他に、HgCdTe,ZnS,Z
nSe等のII−VI族化合物半導体にも適用可能である。同
様に、電子デバイス形成に適した基板としては、Si,InP
の他に、GaAs等の半導体を用いることが可能である。ま
た、半導体基板の表面に素子形成を行った後その表面が
鏡面状態であれば、鏡面研磨工程を省略してよいのは明
らかであり、このことから鏡面研磨工程と素子形成工程
の順序を入替えてもよい。その他、本発明の要旨を逸脱
しない範囲で、種々変形して実施することができる。The present invention is not limited to the above-mentioned embodiments. For example, as the light emitting / receiving device, a light emitting diode, a PIN photodiode, an avalanche photodiode, or the like can be used instead of the semiconductor laser, and the material thereof is GaAs / GaAlAs, InP /
In addition to III-V compound semiconductors such as InGaAsP, HgCdTe, ZnS, Z
It is also applicable to II-VI group compound semiconductors such as nSe. Similarly, as a substrate suitable for forming electronic devices, Si, InP
Besides, a semiconductor such as GaAs can be used. In addition, it is clear that the mirror polishing step may be omitted if the surface of the semiconductor substrate is in a mirror surface state after the elements are formed on the surface. Therefore, the order of the mirror polishing step and the element forming step is interchanged. May be. In addition, various modifications can be made without departing from the scope of the present invention.
第1図(a)〜(e)は本発明の一実施例に係わる半導
体装置の製造工程を示す斜視図及び側面図、第2図
(a)〜(h)は他の実施例に係わる半導体装置の製造
工程を示す断面図である。 10…半導体レーザ基体、11…N−GaAs基板、12…N−Ga
AlAsクラッド層、13…アンドープGaAs活性層、14…P−
GaAlAsクラッド層、15…N−GaAsコンタクト層、16…P
−GaAsコンタクト層、18…共振器端面、19…Si基板、20
…半導体レーザ基体、21…半絶縁性InP基板、22…凹
部、23…P+−InGaAsP電極取出し層、24…P−InPクラッ
ド層、25…アンドープInGaAsP活性層、26…N−InPクラ
ッド層、27…N−InP埋込み層、28…P−InP埋込み層、
29…オーミック電極、30…電子デバイス基体、31…Si基
板、32…凹部、33…N型活性層、34…ショットキー電
極、35…N+型領域、36…ソース電極。1 (a) to 1 (e) are perspective views and side views showing a manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIGS. 2 (a) to 2 (h) are semiconductors according to another embodiment. It is sectional drawing which shows the manufacturing process of an apparatus. 10 ... Semiconductor laser substrate, 11 ... N-GaAs substrate, 12 ... N-Ga
AlAs clad layer, 13 ... Undoped GaAs active layer, 14 ... P-
GaAlAs cladding layer, 15 ... N-GaAs contact layer, 16 ... P
-GaAs contact layer, 18 ... Resonator end face, 19 ... Si substrate, 20
... semiconductor laser substrate, 21 ... semi-insulating InP substrate, 22 ... recess, 23 ... P + -InGaAsP electrode extraction layer, 24 ... P-InP clad layer, 25 ... undoped InGaAsP active layer, 26 ... N-InP clad layer, 27 ... N-InP buried layer, 28 ... P-InP buried layer,
29 ... Ohmic electrode, 30 ... Electronic device base, 31 ... Si substrate, 32 ... Recess, 33 ... N type active layer, 34 ... Schottky electrode, 35 ... N + type region, 36 ... Source electrode.
Claims (6)
子或いは半導体受光素子を形成し、且つその表面側を平
坦化する工程と、第2の半導体基板の表面側に電子素子
を形成し且つその表面側を平坦化する工程と、上記平坦
化した平坦面を水洗したのち乾燥する工程と、次いで清
浄な雰囲気下で上記各平坦面を直接接着し、この状態で
200[℃]以上の温度で熱処理して上記各基板同志を接
着する工程とを含むことを特徴とする半導体装置の製造
方法。1. A step of forming a semiconductor light emitting element or a semiconductor light receiving element on the front surface side of a first semiconductor substrate and flattening the front surface side, and forming an electronic element on the front surface side of a second semiconductor substrate. And the step of flattening the surface side, the step of washing the flattened flat surface with water and then drying, and then directly bonding the flat surfaces under a clean atmosphere, and in this state
And a step of adhering the substrates to each other by heat treatment at a temperature of 200 ° C. or higher.
たのち前記基板の表面側を表面荒さ500[Å]以下に鏡
面研磨することである特許請求の範囲第1項記載の半導
体装置の製造方法。2. The semiconductor device according to claim 1, wherein the step of flattening comprises mirror-polishing the surface side of the substrate to a surface roughness of 500 [Å] or less after forming the element. Production method.
る前に前記基板の表面を表面荒さ500[Å]以下に鏡面
研磨することである特許請求の範囲第1項記載の半導体
装置の製造方法。3. The semiconductor device according to claim 1, wherein the step of planarizing is mirror-polishing the surface of the substrate to have a surface roughness of 500 [Å] or less before forming the element. Production method.
のち、該研磨面上にMOCVD法或いはMBE法によりエピタキ
シャル成長層を形成することである特許請求の範囲第3
項記載半導体装置の製造方法。4. The flattening step is to form the epitaxial growth layer on the polished surface by the MOCVD method or the MBE method after the mirror surface polishing.
Item 7. A method for manufacturing a semiconductor device.
[個/m3]以下の雰囲気であることを特徴とする特許請
求の範囲第1項記載の半導体装置の製造方法。5. The clean atmosphere means that the amount of dust floating is 20.
The method of manufacturing a semiconductor device according to claim 1, wherein the atmosphere is not more than [pieces / m 3 ].
った後、前記第1の半導体基板の一部或いは全部を除去
することを特徴とする特許請求の範囲第1項記載の半導
体装置の製造方法。6. The semiconductor device according to claim 1, wherein part or all of the first semiconductor substrate is removed after the flat surfaces are bonded by the heat treatment. Production method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60022924A JPH0740603B2 (en) | 1985-02-08 | 1985-02-08 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60022924A JPH0740603B2 (en) | 1985-02-08 | 1985-02-08 | Method for manufacturing semiconductor device |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6262442A Division JP2747232B2 (en) | 1994-10-26 | 1994-10-26 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61182256A JPS61182256A (en) | 1986-08-14 |
JPH0740603B2 true JPH0740603B2 (en) | 1995-05-01 |
Family
ID=12096184
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60022924A Expired - Lifetime JPH0740603B2 (en) | 1985-02-08 | 1985-02-08 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0740603B2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3668979B2 (en) * | 1993-08-31 | 2005-07-06 | ソニー株式会社 | Method for manufacturing optoelectronic integrated circuit device |
JP2675519B2 (en) * | 1993-11-17 | 1997-11-12 | 株式会社日立製作所 | Semiconductor substrate, semiconductor device, and manufacturing method thereof |
JP3474917B2 (en) * | 1994-04-08 | 2003-12-08 | 日本オプネクスト株式会社 | Method for manufacturing semiconductor device |
WO2003034508A1 (en) | 2001-10-12 | 2003-04-24 | Nichia Corporation | Light emitting device and method for manufacture thereof |
KR101030068B1 (en) | 2002-07-08 | 2011-04-19 | 니치아 카가쿠 고교 가부시키가이샤 | Nitride semiconductor device manufacturing method and nitride semiconductor device |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4926455A (en) * | 1972-07-11 | 1974-03-08 | ||
JPS58139467A (en) * | 1982-02-15 | 1983-08-18 | Nec Corp | Semiconductor device |
JPS58195276U (en) * | 1982-06-23 | 1983-12-26 | 株式会社日立製作所 | flat display device |
-
1985
- 1985-02-08 JP JP60022924A patent/JPH0740603B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS61182256A (en) | 1986-08-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Mathine | The integration of III-V optoelectronics with silicon circuitry | |
US6261859B1 (en) | Method for fabricating surface-emitting semiconductor device, surface-emitting semiconductor device fabricated by the method, and display device using the device | |
Demeester et al. | Epitaxial lift-off and its applications | |
US7843074B2 (en) | Underfill for light emitting device | |
JP3230785B2 (en) | Semiconductor laser and method of manufacturing the same | |
WO1986003342A1 (en) | ASYMMETRIC CHIP DESIGN FOR LEDs | |
JP2005159071A (en) | Semiconductor device, its manufacturing method and optical transmission system | |
Wada et al. | 1.3-/spl mu/m InP-InGaAsP lasers fabricated on Si substrates by wafer bonding | |
JPH0740603B2 (en) | Method for manufacturing semiconductor device | |
JP3474917B2 (en) | Method for manufacturing semiconductor device | |
JPS6223163A (en) | Hybrid optical ic device | |
JP2747232B2 (en) | Semiconductor device | |
JPH09127352A (en) | Semiconductor device and manufacturing method thereof | |
US5374588A (en) | Process for fabricating a compound semiconductor device | |
JP3668979B2 (en) | Method for manufacturing optoelectronic integrated circuit device | |
JP2002176229A (en) | Semiconductor laser device and its manufacturing method | |
JP2948967B2 (en) | Semiconductor light emitting device | |
CN115881555B (en) | Method for manufacturing semiconductor device | |
JPS59114885A (en) | Manufacture of semiconductor device | |
JPH06349692A (en) | Semiconductor device and manufacturing method thereof | |
Chan et al. | EPITAXIAL LIFT-OFF AND RELATED TECHNIQUES | |
JP2692557B2 (en) | Manufacturing method of semiconductor laser | |
KR940008022B1 (en) | Bonding Method between Heterogeneous Semiconductors Using Compound Semiconductors | |
Fan et al. | Stripe-geometry GaAs-InGaAs laser diode with back-side contact on silicon by epitaxial lift-off | |
Zimmermann et al. | III–V Semiconductor Materials on Silicon |