JPH0740435B2 - Memory read circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory read circuit, and more particularly to a current detection type memory read circuit which has a small detection current and is suitable for high-speed reading.

[Background of the Invention]

 FIG. 6 shows a read circuit of a conventional nonvolatile memory.

In FIG. 6, 11 is a memory element, 21 and 22 are field effect transistors, 23 is a normally-off type N.MOS transistor, 24 is a normally-on type P.MOS transistor, 25 is a P.MOS transistor, and 31 is a level. Detection circuit, 3
2 is a waveform shaping circuit.

The transistors 23 and 24 forming the inverter and one end
The closed circuit composed of the transistor 22 connected to V _CC has a drain voltage V _D
Is raised at a high speed and then operated to maintain a constant value,
To one of the transistors 25, the current flowing in the memory element 11 is converted into a voltage and supplied to the level detection circuit 31, and this is output through the level detection circuit 31 and the waveform shaping circuit 32 (JP-A-58-58). See Japanese Patent No. 208995, "Memory Element Reading Method").

Since the transistor 22 is set so that a large current can flow from the viewpoint of operation, when the memory element 11 is in the ON state, a large current corresponding to the ON resistance of the memory element 11 continuously flows. This is a reactive current with respect to the current flowing through the current detection transistor 25, and is not desirable in configuring a low power consumption circuit.

As a circuit in which the above-mentioned drawbacks are eliminated, there is Japanese Patent Application No. 58-134427, "Memory Read Circuit" proposed by the present inventors. FIG. 1 is a block diagram of the above memory read circuit.

In FIG. 1, 111 is a memory element, 121 is an N.MOS type field effect transistor, 123 is an N.MOS transistor, 124,
125 is a P-MOS transistor, 131 is a level detection circuit, 132
Is a waveform shaping circuit, C1 is a data line capacitance, and C2 is a sense circuit capacitance. The difference between FIG. 6 and FIG. 1 is that the circuit corresponding to the transistor 22 is removed, and as shown in the drain current-voltage characteristics of FIG.
The difference is that a current driving capability difference of 1: 3 to 5 is provided between the drain current (ID) of the memory element 111 and the drain current (ID) of the memory element 111.

When the memory element 111 is in the off state, the transistor 1
A low-power read circuit can be realized by cutting 21 off, but this greatly affects the read time when the memory element 111 changes from the ON state to the OFF state, and the memory element that cuts off the transistor 121. Since the drain voltage of 111, that is, the inverter configured by the transistors 123 and 124 has no limit condition for the logical threshold value (V _cut ), there is a problem that the V _cut value delays the read time.

[Object of the Invention]

An object of the present invention is to solve such a conventional problem, and by a simple and inexpensive method, a memory capable of accelerating the memory reading speed with low power consumption without destabilizing the memory reading time. It is to provide a readout circuit.

[Outline of Invention]

To achieve the above object, the memory read circuit of the present invention is
One end of a switch composed of an N-channel field effect transistor (121) is connected to the drain terminal of the memory element (111), and the other end of the switch (121) is connected to the source or drain of the current detection field effect transistor (125). Connect the drain or source of the current detection field effect transistor (125) to the power supply (V _cc ), and configure the switch by the output of the inverter (123,124) whose input is connected to the drain of the memory element (111). In the memory read circuit, the level detection circuit (131) controls the gate of the field effect transistor (121) to operate, and detects the voltage change at the connection point between the current detection field effect transistor (125) and the switch (121). When the element (111) is in the ON state, the memory element (111) is set in the non-saturation region, the current detection transistor (125).
Is set to operate in the saturation region, and when operated under the above operating conditions, the logical threshold value of the inverter (123,124) is set to be equal to or lower than the voltage at which the drain voltage of the memory element (111) becomes an equilibrium state. Gate common PMOS with a channel conductance ratio (β ₁₂₄ : β ₁₂₃ ) of 1: 400 to 1:25
The inverter is composed of the transistor (124) and the NMOS transistor (123).

Example of Invention

Embodiments of the present invention will be described below with reference to the drawings. The memory read circuit shown in FIGS. 1 and 2 can be applied to one embodiment of the present invention.

FIG. 3 is an operation time chart of FIG.

In FIG. 1, when the memory element 111 is in the ON state, the drain voltage of the memory element 111, that is, the data line potential (V _OL ) is determined by the on-resistance ratio of the transistors 125 and 121 and the memory element 111. The on-resistance of the transistor 121 is set to a value sufficiently smaller than the on-resistance of the transistor 125 in order to eliminate the voltage drop between the source and drain of the transistor 121 and to increase the switching speed of the transistor. Also, in this state,
The transistor 123 is off, the transistor 124 is on, the output of the level detection circuit 131 is “H”, and the output of the waveform shaping circuit 132 is “L”. When the memory element 111 is turned off from this state, the transistor 125 charges the data line capacitance C1 and the sense circuit capacitance C2 to raise the line potential.

When the data line potential reaches the logical threshold value (V _cut ) of the inverter composed of the transistors 123 and 124, the transistor 123 is turned on and the drain voltage (V ₂ ) is lowered to "L" as shown in FIG. Then, the transistor 121 is cut off. Therefore, the charging of the data line capacitance C1 is stopped, and the data line potential is held at V _D (≈V _cut ). Since charging to one sense circuit capacitance C2 is continued, the detection end potential further rises, and when the value of V _D1 is reached, the output of the level detection circuit 131 becomes “L” and the output of the waveform shaping circuit 132 becomes It becomes “H”. Data line capacitance C1 and sense circuit capacitance
Since the relationship of C1 >> C2 is generally present between C2, the sense circuit capacitor C2 is rapidly charged after the transistor 121 is cut off, and reaches V _D1 in a short time. Therefore, the memory read time is the charge period for the data line capacitance C1,
That is, the data line potential is changed from V _OL to V _cut (ΔV in Fig. 2)
It's considered time to go. Transistor 121
The logic threshold value (V _cut ) of the inverter composed of the transistors 123 and 124 for turning off the
The N · MOS threshold of 3 is V _TN , the P · MOS threshold of the transistor 124 is V _TP , and the gain constants of the transistors 123 and 124: When the channel conductance reaches β ₁₂₃ and β ₁₂₄ , respectively, the following equation is obtained. . However, V _TN , V _TP , and V _cut are values standardized by the power supply voltage V _CC , and β _R1 = β ₁₂₄ / β ₁₂₃ .

The variation of V _cut with respect to the variations of V _TN , V _TP , and β _R1 is given by the following equation.

FIG. 4 is a diagram showing the relationship between β _R1 and V _cut of the transistors 123 and 124.

As shown in Fig. 4, as β _R1 is decreased, the logical threshold value (V _cut ) approaches V _TN and V _TP and stabilizes, and ΔV
_{The cut is} also small, and the effect of speeding up is great.

However, even if β _R1 is made extremely small, the effect on V _cut is weakened and the inverter size is increased, which is not preferable in manufacturing. Since V _TN and V _TP are usually used in the range of 0.05 to 0.2 V, the optimum value range of β _R1 is 1/400 to 1/50 as shown by the shaded area in FIG.

FIG. 5 shows the relationship between β _R1 and ΔV _cut in the shaded area in FIG.

When β _R1 is set in the shaded area in Fig. 4, the variation values (ΔV _cut ) of ΔV _TN , ΔV _TP , Δβ _R1 / β _R1 due to the manufacturing parameters are the values shown in Fig. 5, N ・ MOS
Only the threshold value of the transistor 123 causes the V _cut value to change.

That is, if only the threshold value V _TN of the N-MOS transistor 123 is sufficiently controlled and manufactured, the value of V _cut becomes a stable value with little fluctuation, and ΔV (= V _cut −V _OL ) can also be made small. This leads to reduction in power consumption and read time.

Next, a condition for determining the data line potential V _OL when the memory element 111 is in the ON state, which is determined by the ON resistances of the memory element 111 and the current detection transistor 125, and is stable, will be described.

In conclusion, point a in FIG. 2, that is, the non-saturation region in the V _D −I _D characteristic of the memory element 111 and the transistor 1
Set within the saturation region of 25 V _D1 −I _D characteristics. Under such setting conditions, the V _D -I _D characteristic of the memory element 111 rises sharply, and the I _D of the transistor 125 on one side is constant in the vicinity of point a, so that V _OL does not change greatly. Stabilize. The relationship between the memory element 111 and the threshold value of the transistor 125 is as follows.

The saturation operation condition of the transistor 125 is as follows: 1-V _OL > 1-V _TP ∴V _OL <V _TP (3) In the non-saturation region of the memory element 111, 1-V _TM > V _OL (4) where V _TM is a threshold value of the memory element 111. From the above expressions (3) and (4), the operating point can be limited by the expression (3). V _OL <V _TP . Also, β _R2 =
If β ₁₂₅ / β ₁₁₁ , β _R2 , V _TM , and V _TP have the following relationship.

And setting V _OL << 1-V _TM , And V _TM ≈ V _TP , Becomes From the above formula (7), β _R2 becomes 1/19 to 1/3 in the range of 0.05 to 0.25 which is generally used as V _TP .

That is, β _R2 is set to 1/3 or less. Also, β _R2 is
On-state current (I
₁₁₁ ) and the on-state current of transistor 125 (I ₁₂₅ ) (I
₁₂₅ / I ₁₁₁ ), so the on-current of transistor 125 (I ₁₂₅ ) is 1/3 of the on-current of memory element 111 (I ₁₁₁ ).
Even with the following design, the effects of lower power consumption and stabilization of V _OL can be obtained.

As described above, the gate voltage V ₂ of the data line cut-off transistor 121 of the memory reading circuit shown in FIG. 1 is controlled, and the gain constant of the transistors 123 and ₁₂₄ is β ₁₂₄ / β ₁₂₃ = 1 for the inverter composed of the transistors 123 and _124. / 400 ~ 1/25
Set to the relationship of (= β _R1 ). On the other hand, regarding the transistor 125 and the memory element 111 that determine the input voltage V _OL of the inverter, when the memory element 111 is in the ON state, the transistor 125 operates in the saturated region and the memory element 111 operates in the non-saturated region. , V _OL at that time is set to be equal to or lower than the threshold value V _TN of the N-MOS transistor 123. By both setting conditions of the above, close the V _cut V _TN, the V _TP, performs stabilized with V _OL, V _cut, it is possible to reduce the variation of V _OL, (V _cut -
V _OL ) · (C1 + C2) / I ′ ₁₂₅ capacity charging time, that is, the memory read time when the memory element 111 changes to the off state is made short and stable. Further, since the current that flows when the memory element 111 is in the on state is limited by the transistor 125, power consumption can be reduced. The above I '
₁₂₅ is the charging current from the transistor 125. The read time when the memory element 111 is ON is faster than the read time when the memory element 111 is OFF because the ON current of the memory element 111 is 3 to 5 times that of the transistor 125.

〔The invention's effect〕

As described above, according to the present invention, the memory device 111
The change in the on / off state of the transistor is set to 1: 400 to 1:25 by the gain constant ratio of the transistors 123 and 124, and when the memory element 111 is in the on state, the memory element 111 is in the unsaturated region and the transistor 125 is in the saturated region. Since the reading is performed by operating the memory device, the power consumption of the circuit can be reduced and the memory reading time can be stabilized and speeded up without making the memory reading time unstable.

[Brief description of drawings]

FIG. 1 is a memory read circuit diagram to which the present invention is applied, and FIG. 2 is V _D − of the transistor 125 and the memory element 111 shown in FIG.
V _D characteristic diagram, Fig. 3 shows operation time chart of Fig. 1, 4
FIG. 5 is a V _cut −β _R1 characteristic diagram of the transistors 123 and 124 shown in FIG. 1, FIG. 5 is a ΔV _cut −β _R1 characteristic diagram in the shaded portion of FIG. 4, and FIG. 6 is a conventional memory read circuit diagram. 11,111: Memory element, 21,22: FET transistor, 23,121,1
23: N-MOS transistor, 24, 25, 124, 125: P-MOS transistor, 31, 131: Level detection circuit, 32, 132: Waveform shaping circuit, C1: Data line capacitance, C2: Sense circuit capacitance.

Front Page Continuation (72) Inventor Terumi Sawase 1-280, Higashi Koikekubo, Kokubunji City, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-60-28098 (JP, A)

Claims (2)

[Claims] 1. A drain terminal of a memory element is connected to one end of a switch composed of an N-channel field effect transistor, and the other end of the switch is connected to a source or a drain of a field effect transistor for current detection. The drain or source of the field effect transistor for power supply is connected to a power source, and the gate of the field effect transistor forming the switch is controlled by the output of an inverter whose input is connected to the drain of the memory element, and the electric field for current detection is controlled. In a memory read circuit that detects a voltage change at a connection point between an effect transistor and the switch by a level detection circuit, when the memory element is in an ON state, the memory element is in a non-saturation region and the current detection transistor is in a saturation region. It was set to operate with, and operated under the above operating conditions In this case, the common gate PMOS transistor and NMOS transistor whose channel conductance ratio is 1: 400 to 1:25 are set so that the logical threshold value of the inverter becomes equal to or lower than the voltage at which the drain voltage of the memory element is in an equilibrium state. A memory read circuit characterized in that the inverter is constituted by the following. 2. The field effect transistor forming the switch has an on resistance sufficiently smaller than the on resistance of the current detecting field effect transistor when the memory element is in an on state. Range first
A memory reading circuit according to the item.