JPH0738098A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Purpose] Stable extraction of the back gate region, and
Power MOS with sufficient electrical connection area of source region
An FET (semiconductor device) and a method for manufacturing the same are provided. A semiconductor device includes a base region B formed on a semiconductor substrate of one conductivity type, a source region formed in the base region B, a gate oxide film 3, a gate electrode G, and an interlayer formed on the substrate 2. The insulating layer 4 is provided with a wiring groove 5 and a concave groove portion 16 having a tapered inner wall surface Tb formed by punching the inside of the substrate 2 from a window opening formed by selectively removing the source region S. . The manufacturing method includes a step of forming a gate oxide film 3 and a gate electrode G on the substrate 2 to form a window and opening a window to form a base region B from the window opening portion, and a source region S from the entire surface of the window opening to the base region B. Then, the interlayer insulating film including the window opening is deposited to selectively remove the upper surface of the source region S, and the interlayer insulating film 4 is used as a mask to perform the taper etching to form the concave groove portion 1.
6 and electrically draw out the base region B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a vertical power field effect transistor (hereinafter referred to as FET) and a manufacturing method thereof.

[0002]

2. Description of the Related Art An example of a vertical power FET is shown in FIG.
Next, description will be given with reference to (c). First, in FIG. 3B, (1) is a FET, (2) is a semiconductor substrate, (B) is a base region, (S) is a source region, (G) is a gate electrode, and
(3) is a gate oxide film, (4) is an interlayer insulating film, and (5) is a wiring layer. The semiconductor substrate (2) is an N − -type substrate which will be the drain region (D), and an N − -type impurity region is epitaxially grown on the N + -type substrate or an N + -type impurity region is diffused on the back surface of the N − -type substrate. Then, the N + layer (2
a) is formed. The base region (B) is formed in a plurality in the semiconductor substrate (2) by selectively diffusing P-type impurities at a predetermined arrangement pitch and shape, and in particular, a step is formed at the central portion (Bb) deeper than the peripheral portion. To reduce the diffusion resistance. The source region (S) is formed by selectively diffusing high-concentration N-type impurities in each base region (B), and the source / drain regions (S) (D) are formed near the substrate surface of the base region (B). A channel part (C) for conduction is formed. The gate electrode (G) is made of gate polysilicon, and the gate oxide film (3) is formed on the substrate surface including the channel portion (C).
Base regions (B) that are formed adjacent to each other and are adjacent in terms of manufacturing.
Is also formed over the drain region (D). or,
As shown in FIG. 3C, when the substrate surface is viewed in plan,
A plurality of rectangular frame-shaped source regions (S) are arranged at a predetermined pitch and shape, and a gate electrode (G) consisting of a convex step is continuously formed between them, and the central region of the source region (S) is formed. A back gate (base contact) region (Ba) which is exposed from the base region (B) through the source region (S) to the surface of the substrate is formed. Then, an interlayer insulating film (4) and a wiring pattern (5) are deposited and formed thereon.

When a positive voltage is applied to the gate electrode (G) in the above structure, the channel portion (C) in the base region (B) is inverted to N type and the source region (S) and the drain region (D) are electrically connected. Then, a vertical electron flow (I) flows from the source region (S) to the drain region (D) through the channel portion (C).
d) flows. At this time, since the drain region (D) has a low impurity concentration and the conduction resistance of the electron flow (Id) increases, there is a case where a high-concentration N-type impurity region is thinly formed near the pole surface of the substrate in advance.

Next, a method of manufacturing the FET (1) will be described with reference to FIG.
This will be described with reference to (a) to (e) and FIG. First, as shown in FIG. 2A, a P-type impurity such as boron is ion-implanted into the element formation surface on the surface of the semiconductor substrate (2) in advance to form a central portion (Bb) of the base region (B). rear,
A gate oxide film (3) and a gate electrode (G) are sequentially laminated and deposited / formed on the surface. And FIG. 2 (b)
As shown in (c), the gate electrode (G) and the gate oxide film (3) are sequentially patterned at a predetermined pitch and shape to open a window to form a base region impurity diffusion recess (6). Therefore, as shown in FIG. 2C, P-type impurities such as boron are ion-implanted from the concave portion (6) using the gate electrode (G) as a mask, and by thermal diffusion, laterally up to directly below the gate electrode (G). The base region (B) is formed with a predetermined pitch and shape by spreading.

Therefore, as shown in FIG. 2 (d), a resist pattern (8) is formed on the back gate forming region in the recessed region (6) in the central region of the base region (B), and thermal diffusion is performed. The oxide film (7) generated by etching is removed by etching except under the resist pattern (8). Then, a high-concentration N-type impurity is selectively ion-implanted in a rectangular frame shape into each base region (B) using the gate electrode (G) and the resist pattern (8) as a mask to form a source region (S). The base region (B) is exposed to the substrate surface at the central portion thereof to form the back gate region (Ba). Then, as shown in FIG. 2E, the resist pattern (8)
3A, the oxide film (7) immediately below the resist pattern (8) is removed by etching, and the source region (S) is laterally gated by thermal diffusion, as shown in FIG. Push it to just below the electrode (G). After that, FIG.
As shown in (b), an interlayer insulating film (4) is deposited on the gate electrode (G) including the recess (6), and a window is selectively opened to form an electrode lead-out region (9). To form
An aluminum wiring layer (5) is laminated and deposited.

By the way, according to the method for manufacturing the FET (1), the resist pattern (8) is about 5 μm, which is very small and easily peeled off. When 7) is removed by etching, the oxide film (7) is removed over the entire surface. Therefore, similarly to the above, when the source region (S) is formed by ion implantation and the back gate region (Ba) disappears, as shown in FIG. 6, the regular withstand voltage waveform curve (A) shown by the dotted line in the figure.
However, as shown by the solid curve (B), the snapback waveform shifts to the left, and the breakdown voltage deteriorates, resulting in defective element characteristics. Alternatively, even after the oxide film (7) is removed by etching except under the resist pattern (8), the resist pattern (8) is peeled off, and even if the oxide film (7) immediately below remains, the oxide film (7) is removed. ) Is thin, the implanted ions easily penetrate through the oxide film (7), and the back gate region (Ba) disappears similarly.

Therefore, in order to solve the above problems, a manufacturing method disclosed in Japanese Patent Laid-Open No. 64-108775 is also known. As shown in FIG. 4A, the manufacturing method described above sequentially forms a gate oxide film (3) and a gate electrode (G) on a semiconductor substrate (2) as in FIGS. 2A, 2B and 2C. A layer is formed and a window is opened, and at the same time, a P-type impurity is ion-implanted from the window opening (10) and laterally spread by thermal diffusion to form a base region (B). Therefore, as shown in FIG. 4B, when the oxide film (7) generated by thermal diffusion is removed by etching on the entire surface, N-type impurities are directly ion-implanted from the window opening (10) to the source. A region (S) is formed. Next, as shown in FIG. 4C, the source region (S) is laterally pushed and spread by thermal diffusion, and the window opening (1
0), the interlayer insulating film (4) is formed on the entire surface of the gate electrode (G), and then the interlayer insulating film (4) is removed by etching through the resist pattern (11) formed thereon. The window opening portion (12) is formed again. Therefore, as shown by the dotted line in FIG. 4 (d), the window opening (12)
Then, the semiconductor substrate (2) is removed by etching deeper than the diffusion junction depth of the source region (S) using the resist pattern (11) as a mask to form a groove (13). The back gate region (Ba) is exposed from the base region (B). Then, as shown in FIG. 5, after removing the resist pattern (11), the wiring layer (5) is formed on the interlayer insulating film (4) including the groove (13).
Is deposited and the back gate region (Ba) is electrically drawn out to form the FET (14).

[0008]

As shown in FIG. 5, the problem to be solved is to remove the semiconductor substrate (2) by etching deeper than the diffusion junction depth of the source region (S) to remove the back gate region (Ba). ) Is exposed, the depth of the diffusion junction in the source region (S) is shallow and about 1 μm, while the etching proceeds perpendicularly to the substrate, so that the inner wall surface (Ta) of the source region (S) becomes This is the point that the electrical contact area with the wiring layer (5) is reduced (conventionally 2 to 3 μm), the ohmic contact becomes insufficient, and the electrical characteristics are degraded.

[0009]

The present invention provides, as a semiconductor device, a base region formed by selectively diffusing an electrokinetic impurity in a predetermined region of a one conductivity type semiconductor substrate to be a drain region, and a base region in the base region. A source region formed by selectively diffusing one conductivity type impurity and a source region of a gate oxide film, a gate electrode and an interlayer insulating film, which are sequentially formed by stacking on the substrate, are selectively removed. It is characterized in that it is provided with a concave groove portion having a tapered inner wall surface formed by piercing the inside of the substrate from the formed window opening portion, and a wiring layer deposited on the interlayer insulating film including the inside of the concave groove portion. age,

Further, as a manufacturing method, a gate oxide film and a gate electrode are sequentially laminated on the upper surface of one conductivity type semiconductor substrate to be a drain region, and a window is selectively opened. And then pushing to form a base region, and after implanting one conductivity type impurity into the base region from the entire surface of the window opening to form a source region, the interlayer insulating film including the window opening is covered. And a step of selectively removing the upper surface of the source region, a step of taper etching from the window opening to a predetermined depth from above using the interlayer insulating film as a mask, and forming a groove having a tapered inner wall surface, And a wiring layer is formed on the interlayer insulating film including the groove portion, and the base region is electrically drawn through the source region.

[0011]

According to the above technical means, the source region selectively formed in the base region of the FET is anisotropically etched deeper than the diffusion depth to form a concave groove portion having an inner wall surface tapered. When the wiring layer is deposited inside, the electrically drawn area of the source region increases.

[0012]

Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to FIGS. First, FIG. 1A shows a semiconductor device (15) according to the present invention.
The same parts as those shown in FIG. 5 are designated by the reference numerals and the description thereof will be omitted. The difference is that, like the back gate region (Ba), the recessed groove portion () formed in the source region (S) of the semiconductor substrate (2) so that the base region (B) is exposed from the central portion of the source region (S). 16), which is characterized in that it is deeper than the source diffusion junction depth and the inner wall surface (Tb) is tapered.

According to the above-mentioned structure, as in FIG. 5, after the resist pattern (11) is removed, the wiring layer (5) is formed on the interlayer insulating film (4) including the concave groove (16). When the base region (B) is electrically pulled out, the contact area between the inner wall surface (Tb) of the source region (S) and the wiring layer (5) is significantly increased.

Next, a method of manufacturing the semiconductor device (15) will be described with reference to FIGS. Figure 1
FIG. 4B shows a process similar to that of FIG. 4C in the conventional manufacturing method, and the different point is the process shown in FIG. The feature thereof is that when the semiconductor substrate (2) is etched deeper than the diffusion junction depth of the source region (S) using the resist pattern (11) as a mask from the window opening (12) to form the concave groove (16). That is, anisotropic wet etching (taper etching) using an alkaline solution such as potassium hydroxide is used. According to the anisotropic etching, as shown in FIG. 1D, the semiconductor substrate (2)
When the etching progresses in the crystal direction of and the etching is stopped at the middle portion (depth of about 2 μm) of the back gate region (Ba), in the case of the (100) crystal, the truncated pyramidal recessed groove (16) ) Is formed and its angle (θ)
Becomes 54.7 °. As a result, the shape of the concave groove portion (16) is deeper than the source diffusion junction depth and the inner wall surface (T
b) is formed in a tapered shape. In addition to the truncated pyramid shape, the etching time can be appropriately controlled, or the truncated pyramid shape can be formed by etching to the maximum depth as shown by the dotted line in the figure. Then, as shown in FIG. 5, after the resist pattern (11) is removed, a wiring layer (5) is formed on the inter-layer insulating film (4) including the recessed groove (16) as in the conventional case by forming a base. It suffices to electrically draw out the region (B).

When the interlayer insulating film (4) is formed by CVD, it can be directly used as a mask for etching.

[0016]

According to the present invention, the source region of the power MOSFET is deeper than the diffusion depth and anisotropically etched to form a groove having a tapered inner wall surface, and a wiring layer is formed in the groove. Since it is deposited and electrically connected to the back gate and the source region, the electrical extraction of the back gate region is stable, and the electrical extraction area of the source region and the wiring layer is increased, so that a stable ohmic contact is obtained. It can be formed and the electrical characteristics are improved. Also, since the number of times the resist pattern is aligned is reduced by one, the number of steps is reduced, and
The element size can be reduced by the alignment margin.

[Brief description of drawings]

FIG. 1A is a side sectional view of an essential part showing an embodiment of a semiconductor device according to the present invention. (B) (c) is process drawing which shows the Example of the semiconductor device which concerns on this invention. (D) is a plan view showing the shape of the concave groove portion according to the present invention.

2A to 2E are process diagrams showing an example of a conventional method for manufacturing a semiconductor device.

FIG. 3A is a process diagram following FIG. 2A to FIG. 2E showing an example of a conventional method for manufacturing a semiconductor device. (B) is a principal part side sectional view showing an example of a conventional semiconductor device.
(C) is a principal part top view which shows an example of the conventional semiconductor device.

4A to 4D are process diagrams showing another example of a conventional method for manufacturing a semiconductor device.

FIG. 5 is a process diagram that continues from FIGS. 4A to 4D and shows another example of a conventional method for manufacturing a semiconductor device.

FIG. 6 is a current-voltage characteristic diagram of a conventional semiconductor device.

[Explanation of symbols]

 2 semiconductor substrate 3 gate oxide film 5 wiring layer 16 recessed groove G gate electrode B base region S source region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/306 21/336 8617-4M H01L 21/265 L 9272-4M 21/306 B 9055-4M 29/78 321 P

Claims (3)

[Claims] 1. A base region formed by selectively diffusing an electrokinetic impurity in a predetermined region of a one conductivity type semiconductor substrate to be a drain region, and a base region formed by selectively diffusing one conductivity type impurity in the base region. The source region and the source region of the gate oxide film, the gate electrode and the interlayer insulating film, which are sequentially deposited and deposited on the substrate, are selectively removed on the source region to form a hole in the substrate through a window opening. A semiconductor device comprising: a concave groove portion having a tapered inner wall surface formed as described above; and a wiring layer deposited on the interlayer insulating film including the inside of the concave groove portion. 2. A gate oxide film and a gate electrode are sequentially stacked on the upper surface of one conductivity type semiconductor substrate to be a drain region and a window is selectively opened, and then an electrokinetic impurity is injected from the window opening. The step of pressing to form the base region, and the step of forming a source region by injecting one conductivity type impurity into the base region from the entire surface of the window opening, and then depositing an interlayer insulating film including the window opening The step of selectively removing the upper surface of the source region, the step of taper-etching from the window opening to a predetermined depth from above using the interlayer insulating film as a mask to form a concave groove portion having a tapered inner wall surface, and the concave groove portion A method of manufacturing a semiconductor device, comprising the steps of: forming a wiring layer on the interlayer insulating film and electrically extracting the base region through the source region. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the taper etching is etching with an alkaline solution.