JPH0737387A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide a data input / output system circuit precharged to a low level for a data input / output line pair in a write control circuit of a memory IC in order to shorten the time required for a write operation. [Structure] Bit line pair BL, via sense amplifier SA
A data input / output line pair DQ, / DQ connected to / BL,
A precharge circuit 1 for equalizing and clamping the data input / output line pair DQ, / DQ is provided, and the power supply of the precharge circuit 1 is provided independently for the read Vr and the write Vw. , / DQ is a semiconductor integrated circuit for precharging to different levels during reading and writing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
The present invention relates to a control circuit effective for speeding up a writing operation in a memory IC such as a DRAM.

[0002]

2. Description of the Related Art A conventional measure for speeding up a write operation will be described. FIG. 5 is a conventional data input / output circuit diagram.
Data input / output line pair (DQ, / D in the data input path
In the write operation after Q), the MOS transistor switches 101 and 102 are turned on and the data input line pair (WDB,
/ WDB) is transmitted to the data input / output line pair to start. When the data appearing on the data input / output line pair and the data appearing on the data input line pair to be written are different, the potential of the data input / output line pair is determined after the MOS transistor switches 101 and 102 are turned on. It takes time to write, and high-speed write operation cannot be performed. Therefore, conventionally, in order to cope with the speeding up of the write operation, the data input / output line pair is connected to the MOS transistor 1
By equalizing with 05, the time from when the MOS transistor switches 101 and 102 are turned on until the write potential of the data input / output line pair is determined is shortened.

Further, in order to improve the layout area efficiency, the sense amplifier has a weaker ability to hold a high level than an ability to hold a low level. Further, in order to improve the layout area efficiency, the column switches 2 and 2 ′ for controlling the connection between the data input / output line pair and the sense amplifier are composed of N channel MOS transistors 108 and 109.
Therefore, the MOS transistor 1 should be read at the time of reading so as not to destroy the read data appearing on the bit line pair.
06 and 107 clamp the data input / output line pair to a high level, and when the data input / output line pair is equalized, M
The data input / output line pair is precharged to a high level by the OS transistors 103 and 104. Similarly during writing, the data input / output line pair was precharged to a high level during equalization of the data input / output line pair.

[0004]

Due to the demand for higher speed, it is required to further shorten the time required for the write operation. When the data input / output line pair is clamped to a high level during writing as in the conventional case, even if the write data is transmitted to the data input / output line pair by closing the MOS transistor switches 101 and 102, the N channel forming the column switch is formed. If the potential on the row side of the data input / output line does not drop below the threshold voltage Vt of the MOS transistors 108 and 109, the write data appearing on the data input / output line pair does not pass through the column switch. In particular, during low voltage operation, the ratio of the threshold voltage of the MOS transistor to the power supply voltage becomes large, and the time from the closing of the MOS transistor switches 101 and 102 until the write data passes through the column switch is delayed. .

The present invention has been made in view of the above problems,
An object of the present invention is to provide a semiconductor integrated circuit in which the writing operation is further speeded up.

[0006]

A first invention is a data input / output line pair connected to a bit line pair via a sense amplifier, and a precharge circuit for equalizing and clamping the data input / output line pair. A semiconductor integrated circuit having a power supply of the precharge circuit independently for reading and writing, and precharging the data input / output line pair to different levels during reading and writing. Is.

A second invention has a data input / output line pair, a data input line pair, and a switch circuit for controlling data transfer from the data input line pair to the data input / output line pair, Before the write data is transmitted to the data input line pair, the switch circuit connects the data input line pair and the data input / output line pair to set the potential of the data input line pair before the write data is transmitted. The semiconductor integrated circuit is characterized in that the data input / output line pair is precharged at the time of writing by transferring the data input / output line pair.

[0008]

In the first invention, the power supply of the precharge circuit is independently provided for reading and writing, and in the second invention, the data is set by setting the potential of the data input line input to the switch circuit. The precharge level of the I / O line pair can be set independently for reading and writing. If the precharge level of the data input / output line pair at the time of writing is set to the ground potential or a sufficiently low potential, the write data appearing on the data input / output line pair immediately passes through the column switch composed of N-channel MOS transistors. The data transfer to the sense amplifier can be speeded up.

Further, since the data input / output line pair and the bit line pair are connected through the sense amplifier through the selected column switch, the data input / output line pair is precharged to the ground potential or a sufficiently low potential. Then, the bit line pair is also precharged to the low level. Therefore, the potential difference between the bit line pair before the write data is transferred is small, and the time from the transfer of the write data to the bit line pair to the establishment thereof can be shortened.

[0010]

EXAMPLES Examples of the present invention will be described in detail below.

FIG. 1A is a data input / output system circuit diagram according to an embodiment of the first invention. In the figure, DQ and / DQ are data input / output line pairs, WDB and / WDB are data input line pairs, and B.
L and / BL are bit line pairs, 101 and 102 are switches for connecting the data input line pair and the data input / output line pair, and 103-
Reference numeral 105 is a MOS transistor forming the precharge circuit 1, 108 and 109 are MOS transistors forming the column switches 2 and 2 ′, 201 to 203 are MOS transistors forming the precharge power supply selection switch 3,
Y is a column switch selection signal, SD is a data input / output line pair selection signal, W1 is a write identification signal, W2 is a data input line pair / data input / output line pair connection control signal, EQ is a precharge circuit control signal, and Vr is a read signal. A time precharge power supply, and Vw is a write precharge power supply.

FIG. 1B is a time chart of each signal shown in the data input / output system circuit diagram of FIG. 1A. Figure 1
The operation during writing in the data input / output system circuit of FIG. 1A will be described with reference to FIG.

First, the data input line pair selection signal SD transits to low, and the 1/2 VCC power supply is cut off from the precharge circuit 1 associated with the selected data input / output line pair. Subsequently, W1 transits to low, the read precharge power supply Vr is disconnected from the precharge circuit, and the write precharge power supply Vw is connected to the precharge circuit. The precharge circuit 1 precharges and equalizes the data input / output line pair while EQ is at a low level. At this time, if the precharge power supply Vw for writing is at the ground potential, the data input / output line pair DQ, / DQ is precharged to a low level as shown in FIG. 1B. Further, when Y changes to high while EQ is low level, the potential of the data input / output line pair is transmitted to the bit line pair, and the potential difference between BL and / BL becomes small. W2 rises, and the data on the data input line pair starts to be transferred to the data input / output line pair through the MOS transistor switches 101 and 102. Column switch is N channel MO
Since it is composed of S transistors 108 and 109,
The low level has a faster passage speed than the high level, and the write data that appears on the data input / output line pair that has been precharged to the low level has a faster column switch than when the data input / output line pair is clamped to the high level. To pass. Further, as described above, since the precharge potential of the data input / output line pair is transmitted to the bit line pair and the potential difference between BL and / BL becomes small, the write line passes through the column switch, and then the bit line. The time until it is determined by the pair is also faster than when the data input line pair is clamped to the high level.

FIG. 2A is a data input / output system circuit diagram according to an embodiment of the second invention. In the figure, DQ and / DQ are data input / output line pairs, WDB and / WDB are data input line pairs, and B.
L and / BL are bit line pairs, 108 and 109 are MOS transistors forming the column switch 2, Y is a column switch selection signal, SD is a data input / output line pair selection signal, and W1
Is a write identification signal, W2 is a data input line pair / data input / output line pair connection control signal, and EQ is a precharge circuit control signal. Also, the switch circuit is
NAND gate having DB and W2 as input signals, SD,
The clocked inverter is controlled by W1 and activated only by the switch circuit selected at the time of writing.

FIG. 2B is a time chart of each signal shown in the data input / output system circuit diagram of FIG. 2A. Figure 2
The operation at the time of writing in the data input / output system circuit of FIG. 2A will be described with reference to FIG.

First, SD transits to low, and the data input / output block to be written is selected. Subsequently, W1 transits to low, and the clocked inverter that constitutes the switch circuit is activated. Further, the data input / output line pair precharge circuit selected at the time of writing is SD, W
Not activated by 1. At this time, if W2 has not risen, the output of the NAND gate constituting the switch circuit is high, and DQ and / DQ are precharged to the low level which is the output of the clocked inverter.
Further, even if W2 rises early, if the potential of the data input line pair in the standby state is set to the low level, the NAND gate of the switch circuit is supplied until the write data is transmitted to the data input line pair. Output remains high, and DQ and / DQ are precharged to the low level which is the output of the clocked inverter.

As described above, if the potential of the data input line pair is transmitted to precharge the data input / output line pair, the data input / output line pair is stored until the write data starts to be transferred to the data input / output line pair. You can precharge the pair. Therefore, the timing margin from prohibiting the precharge of the data input / output line pair to connecting the data input line pair and the data input / output line pair becomes unnecessary, and the data input line pair to the data input / output line pair is not required. The data transfer rate is
This is faster than starting data transfer from the data input line pair to the data input / output line pair after prohibiting precharge of the data input / output line pair.

As described in the first embodiment of the present invention, if the precharge level of the data input / output line pair is set to the low level, the write data passes through the column switch composed of N channel MOS transistors. The speed is faster than when the data input / output line pair is precharged to the high level.

Further, as the degree of integration of the memory and the like increases, the capacity of the data input / output line pair increases, and further, when a plurality of data input / output line pairs are used as in a multi-bit configuration, the data input / output line pair is used. The charge / discharge current of the line pair increases the current consumption. If the data input / output line pair is precharged to 1/2 VCC,
The current consumption for charging / discharging the data input / output line pair is half that in the case of precharging the data input / output line pair to VCC or the ground potential. Set the data I / O line pair to 1 when reading
To precharge to / 2VCC, it is necessary to reduce the size of the column switch so that the read data on the bit line is not crushed by the potential of the data input / output line pair and to make it difficult for the data to pass. As described above, according to the present invention, the writing speed is faster than the conventional one, so even if the size of the column switch is set to be small so that data cannot pass easily, the writing operation itself can be sufficiently performed and the power consumption can be reduced. Is also effective.

FIG. 3 shows a simulation waveform when the data input / output line pair according to the second invention of the present application is precharged to the ground potential. FIG. 4 shows the data input / output line pair according to the first invention of the present application is halved. It is a simulation waveform when precharged.

The waveform of FIG. 3 will be described with reference to the data input / output system circuit diagram of FIG. 2A. When W1 rises, DQ is precharged to a low level, and BL also falls to the low side depending on the level of DQ. You can see that
When W2 rises, the potential is inverted at DQ and / DQ, and about 1.5 after the potential at DQ and / DQ is inverted.
After NS, the potentials of BL and / BL are inverted.

The waveform of FIG. 4 will be described with reference to the data input / output system circuit diagram of FIG. 1A. D will be described before W2 rises.
The precharge of Q and / DQ is released and once DQ and / D
The potential difference of Q is increasing. After W2 has started up, D
It can be seen that the potentials are inverted at Q and / DQ, and the potentials at BL and / BL are inverted at about 3.5 NS after the potentials at DQ and / DQ are inverted.

Comparing FIG. 3 and FIG. 4, it is better to precharge the data input / output line pair to the ground potential during the time from when W2 rises to when the potential inversion occurs at DQ and / DQ. It can be seen that it is about 0.5 NS faster than precharging the output line pair to 1/2 VCC. Also, D
Even for the time from the inversion of the potentials of Q and / DQ to the inversion of the potentials of BL and / BL, precharging the data input / output line pair to the ground potential makes the data input / output line pair 1
It can be seen that it is about 2.0 NS faster than precharging to / 2 VCC.

[0024]

According to the first aspect of the present invention, the power supply for the precharge circuit is provided independently for reading and writing.
According to the second aspect of the present invention, by setting the potential of the data input line input to the switch circuit, the data input / output line pair can be precharged to different levels during writing and reading. If the data input / output line pair is precharged to the low level at the time of writing, the write data appearing on the data input line pair passes through the column switch composed of N-channel MOS transistors at a high speed. Faster than precharging to.

Furthermore, since the data input / output line pair and the bit line pair are connected via the sense amplifier through the selected column switch, when the data input / output line pair is precharged to the low level, the bit line pair is also connected. Precharged to low level. Therefore, the potential difference between the bit line pair before the write data is transferred is small, and the time from the transfer of the write data to the bit line pair to the establishment thereof can be shortened.

Further, if the data input line pair is precharged to the low level at the time of writing, the writing ability is increased, so that the ability of the column switch can be kept low. Therefore, it becomes unnecessary to precharge the data input / output line pair to a high level at the time of reading. If the data input / output line pair at the time of reading is precharged to 1/2 VCC, the charge / discharge current related to the data input / output line pair is minimized.

[Brief description of drawings]

FIG. 1A is a configuration diagram centering on a data input / output system of a semiconductor integrated circuit according to a first embodiment of the present invention, and FIG. 1B is a schematic diagram of each signal shown in the data input / output system circuit diagram of FIG. 1A. Time chart

FIG. 2A is a configuration diagram centering on a data input / output system of a semiconductor integrated circuit according to a second embodiment of the present invention, and FIG. 2B is a schematic diagram of each signal shown in the data input / output system circuit diagram of FIG. 2A. ,Time chart

FIG. 3 is a diagram showing a data input system simulation result at the time of writing in the semiconductor integrated circuit according to the second embodiment of the present invention.

FIG. 4 is a diagram showing a data input system simulation result at the time of writing in the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 5 is a block diagram mainly showing a data input / output system of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 1 Precharge circuit 2 Column switch 3 Precharge power supply selection switch 4 Switch circuit 5 Clocked inverter

Claims (4)

[Claims] 1. A power supply for the precharge circuit, comprising: a data input / output line pair connected to a bit line pair via a sense amplifier; and a precharge circuit for equalizing and clamping the data input / output line pair. Is independently provided for reading and writing, and the data input / output line pair is precharged to different levels during reading and writing. 2. A bit line pair selected via a sense amplifier by precharging the data input / output line pair at the time of writing by setting the power supply voltage for writing of the precharge circuit to the ground voltage. 2. The semiconductor integrated circuit according to claim 1, wherein is precharged to a low level. 3. A data input / output line pair, a data input line pair,
A switch circuit for controlling data transfer from the data input line pair to the data input / output line pair, and before the write data is transmitted to the data input line pair, the switch circuit controls the data input line. By connecting the pair of the data input / output line pair and transferring the potential of the data input line pair before the write data is transmitted to the data input / output line pair, the data input / output line pair at the time of writing A semiconductor integrated circuit characterized by precharging. 4. The standby level of the data input line pair before the write data is transmitted to the data input line pair is set to the ground potential, and the write data is transmitted to the data input line pair during writing. 4. The bit line pair selected through the sense amplifier is precharged to a low level by precharging the data input / output line pair to the ground potential through the data input line pair. Semiconductor integrated circuit.