JPH0736151B2 - Full adder circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a full adder circuit which operates at high speed and has a small variation in signal propagation delay time from each input terminal to each output terminal.

[Conventional technology]

FIG. 5 is a diagram showing a conventional full adder circuit disclosed in Japanese Patent Laid-Open No. 61-70636. In this figure, A is the addend signal, is the negative signal of the addend signal, Cin is the carry input signal, and T is the carry input signal.
G1 to TG5 are transmission gate circuits, INV1, INV2, INV3, INV4a, INV4
b is an inverting amplifier circuit, GK1 is a carry signal generation circuit, 1, 3, 5, 7,
9 is a terminal and 101 is a signal line.

The addend signal A is input to the terminal 1, the addend signal negation signal is input to the terminal 3, and the carry input signal Cin is input to the terminal 5. The augend signal A and the negation signal of the addend signal are transmitted to the transfer gate circuit TG1,
The signal is input to the circuit composed of TG2 and the inverting amplifier circuits INV1 and INV2, and the exclusive NOR (hereinafter abbreviated as XNOR) is taken. Terminal 5 and XNOR signal of the augend signal A and negation of the addend signal
The carry input signal Cin input to the transmission gate circuit TG3, T
The exclusive OR (hereinafter abbreviated as XOR) is input to the circuit composed of G4 and the inverting amplifier circuits INV3 and INV4a, and this is output to the terminal 7 as the sum signal S. Carry input signal Ci
n becomes an inverted signal in the inverting amplifier circuit INV4b, and the XNOR signal of the augend signal A and the negation signal of the addend signal and the XNOR signal of the augend signal A and the negation signal of the addend signal generated by the inverting amplifier circuit INV3. It is input to the transmission gate circuit TG5 which is opened / closed by a negative signal of the signal. When the transmission gate circuit TG5 is closed, a carry signal is generated in the carry signal generation circuit GK1 by the augend signal A and the negation signal of the addend signal input to the terminals 1 and 3. Negative signal of the carry input signal Cin that has passed through the transmission gate circuit TG5,
Alternatively, the carry signal generated in the carry signal generation circuit GK1 is output to the terminal 9 as a carry output signal ▲ ▼.

Next, let us consider a case where the sum signal S changes due to a change in the negation signal of the addend signal input to the terminal 3 with the addend signal A and the carry input signal Cin input to the terminals 1 and 5 being constant. .

The negation signal of the addend signal is input to the inverting amplifier circuit INV2 to be the addend signal B, and is input to the gates of the transmission gate circuits TG1 and TG2 together with the negation signal of the addend signal. The change changes the open / closed state of the transmission gate circuits TG1 and TG2 with a delay of the time of passing through the inverting amplifier circuit INV2. The signal on the signal line 101 changes due to the change in the open / close state of the transmission gate circuits TG1 and TG2, and the signal on the signal line 101 is input to the inverting amplifier circuit INV3 to be a negative signal, and together with the signal on the signal line 101, the transmission gate Circuit TG3
Since the signal line 101 is input to the gates of TG4 and TG4, the change of the signal line 101 changes the open / closed state of the transmission gate circuits TG3 and TG4 after a delay of passing the inverting amplifier circuit INV3. Then, the sum signal S changes due to the change in the open / closed state of the transmission gate circuits TG3 and TG4.

Next, a case where this full adder circuit is used for an AND adder circuit in a carry save adder type parallel multiplier will be described.

FIG. 6 shows an example of a 4 bit × 4 bit parallel multiplier circuit based on the carry save adder method. In the figure, X0, X1, X2, X
3 is the input signal of the 0th, 1st, 2nd and 3rd bits of the multiplier X, Y0, Y
1, Y2, Y3 are input signals of 0,1,2,3 bit of multiplicand Y, Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7 are 0,1,2,3 of numerical product Z ,Four,
It is the output signal of the 5th, 6th and 7th bits. Reference numeral 50 denotes an AND adder circuit in which a logical product circuit is connected to one input terminal of the full adder circuit. As is apparent in the figure, the logical product of each bit of the corresponding multiplier X and the multiplicand Y and the AND adder circuit before it. Executes full addition operation of SO and carry signal CO, and performs AND addition signal SO
And carry signal CO is output. Reference numeral 60 is an AND half addition circuit in which a logical product circuit is connected to one input of the half addition circuit, and 70 is a logical product circuit. 80 is a 3-bit full adder circuit, A0, A
1, A2, B0, B1, B2 are input signals of 0,1,2 bits of addend A and augend B respectively, and S0, S1, S2 are outputs of 0,1,2 bits of sum signal S Signal and CO are carry output signals.

FIG. 7 shows an example of the AND addition circuit 50. In the figure, X, Y
Is a 1-bit multiplier and multiplicand input signal, A and B are addition input signals, and SO and CO are numerical sum output signals and carry output signals. Five
1 is a logical product circuit and 52 is a full adder circuit.

In the parallel multiplication circuit as described above, each bit of the multiplier X and the multiplicand Y is logically ANDed by the corresponding AND addition circuit of the AND addition circuits arranged in a matrix (partial product generation of each bit), and sequentially output direction By adding toward, the total sum of the partial products is obtained, and as a result, a numerical product calculation result of the multiplier X and the multiplicand Y is output to the product output Z.

[Problems to be Solved by the Invention]

In the conventional full adder circuit as described above, since the negative signal is generated therein, there is a problem that the time for generating the negative signal delays the addition.

In addition, the conventional full adder circuit compares the carry input signal Cin to the sum output signal S, the carry output signal CO to the signal transmission path, and adds the add input signal A, the summed input signal B to the sum output signal S,
Since the signal transmission path to the carry output signal CO has a larger number of element stages, the addition input signal A and the summed input signal B are compared with the signal propagation delay from the carry input signal Cin.
The signal propagation delay from is large.

On the other hand, considering the speed-up of the parallel multiplication circuit as shown in FIG. 6, the signal propagation delay from the addition input signal A and the summed input signal B of the AND addition circuit in the parallel multiplication circuit to the output signals CO and SO is It is important to be uniform and fast. Therefore, when the conventional full adder circuit is used for the AND adder circuit, the high speed operation from the carry input signal Cin of the full adder circuit is not utilized, but rather is regulated by the low speed operation from the add input signals A and B, There is also a problem that the speed of the entire multiplier decreases.

The present invention has been made in order to solve such a problem, and obtains a full adder circuit suitable for a high-speed parallel multiplication circuit by speeding up and uniforming the propagation delay time from each input signal to each output signal. With the goal.

[Means for Solving the Problems]

A full adder circuit according to the present invention receives a complementary addend signal pair and a complementary augend signal pair as inputs, and outputs a first exclusive OR signal and a first negative exclusive OR signal. And a carry input signal pair complementary to the first exclusive OR signal and the first negative exclusive OR signal, and a second exclusive logic as a complementary OR signal pair. A second circuit for outputting a sum signal and a second NOT exclusive OR signal, and the complementary carry input signal pair respectively for the first circuit.
First and second gate circuits for passing and blocking using at least one of the exclusive OR signal and the first negative exclusive OR signal, and the blocking of the first and second gate circuits. A carry generation signal and a carry cancellation signal by setting one of the carry output signal line pairs to a predetermined potential in accordance with the addend signal pair and the augend signal pair when in the state A carry signal generating circuit and a carry signal erasing circuit, wherein the first and second circuits are composed of first, second, third and fourth MOS type transistors, and first and second The source of each of the MOS type transistors is connected to the first input terminal thereof, and the sources of the third and fourth MOS type transistors thereof are both connected to the second input terminal thereof. Both gates Is connected to the third input terminal, a gate of the second and third MOS transistors are both connected to the fourth input terminal, first and third
The drain of the MOS type transistor is used as the output terminal of the negative exclusive OR, the drains of the second and fourth MOS type transistors are used as the output terminal of the exclusive OR, and the first and second inputs of the second circuit are provided. The complementary carry input signal pair is input to the input terminal pair,
The third and fourth input terminals of the above circuit form a pair, and the pair of the first exclusive OR signal and the first negative exclusive OR signal complementary to the first circuit are connected to the input terminal pair. Is to be input.

[Action]

According to the present invention, in the first circuit, the exclusive OR and negative exclusive OR of the complementary addend signal pair and the complementary addend signal pair are the first exclusive OR signal and the first exclusive OR signal. A first exclusive logical sum signal and a carry input signal pair complementary to the first exclusive logical sum signal and the first negative exclusive logical sum signal, which are output as a negative exclusive logical sum signal and become a complementary sum signal pair in the second circuit. The exclusive OR and the negative exclusive OR are output as the second exclusive OR signal and the second negative exclusive OR signal.

Further, the first and second gate circuits include at least one of the first exclusive OR signal and the first negative exclusive OR signal.
A pair of complementary carry input signals are passed and blocked by one, and at the time of this blocking, a carry generation signal and a carry cancellation signal are generated from the carry signal generation circuit and the carry signal cancellation circuit.

Furthermore, by limiting the connection relationship between the carry input signal pair complementary to the input terminal of the second circuit and the output signal pair of the first circuit as described above, the addend input signal pair B, The electrical load of the preceding circuit that drives the addend input signal pair A is reduced compared to the electrical load of the preceding circuit that drives the complementary carry input signal pair Cin, ▲ ▼. ing.

〔Example〕

FIG. 1 shows a full adder circuit according to an embodiment of the present invention.
In the figure, the same symbols as those in FIG. 5 indicate the same parts, A is the augend signal, B is the addend signal, Cin is the carry input signal, and S is
Is a sum output signal, CO is a carry output signal ,,, ▲
▼ is a negative signal complementary to each signal, 2, 4, 6, 8,
10 is a terminal, 11 and 12 are first and second circuits for making XOR and XNOR, 13 to 15 are level guarantee circuits, 16 to 19 are inverting amplifier circuits, and 20 and 21 are first and second gate circuits. , 22 and 23 are carry signal erasing circuits and carry signal generating circuits, and 201 to 206 are signal lines. Further, the power supply potential V _CC is logic “1” and the ground potential GND is logic “0”.

The augend signal A as a complementary augend signal pair and its negation signal are input to terminals 1 and 2, respectively, and terminals 3 and 4
An addend signal B as a pair of complementary addend signals and its negation signal are input to each. By inputting the augend signal pair A and the augend signal pair B to the first circuit 11, the first X of the augend signal A and the augend signal B is input to the signal line 201.
The NOR signal appears on the signal line 202 as the first XOR signal of the augend signal A and the addend signal B. A level assurance circuit 13 that assures "1" level is connected to these signal lines. The relationship between (A,) and (B,) input to the first circuit 11 and (first XOR, first XNOR) output is shown in FIG.

Here, as is apparent from FIG. 1, the first and second circuits 11 and 12 have first, second, third and fourth MOS type transistors Q1.
To Q4, the first and second MOS type transistors Q1,
The sources of Q2 are both connected to its first input terminal (3), the sources of the third and fourth MOS transistors Q3, Q4 are both connected to its second input terminal (4), and The gates of the fourth MOS type transistors Q1 and Q4 are both connected to the third input terminal (1) thereof, and the second and third
The gates of the MOS transistors Q2 and Q3 are both connected to the fourth input terminal (2) thereof.

Further, the first XNOR signal from the signal line 201 and the first XOR signal from the signal line 202 are respectively included in the second circuit 12.
Second connected to the gates of OS type transistors Q5 to Q8
The carry input signal pair Cin, ▲ ▼ connected to the third and fourth input terminals of the circuit 12 of FIG.
The second XNOR, XOR circuit 12 connected to the sources of the MOS transistors Q5 to Q8 included in the circuit 12 of FIG.

The level assurance circuits 13 to 15 are composed of two PMOS type transistors, both sources are connected to the power supply potential V _CC , both gates are connected to the other drain, and both drains are connected to the connection terminal.

Explaining the operation of the level assurance circuits 13 to 15, when one of the connection terminals becomes the ground potential GND, the PMOS transistor whose gate is connected to the connection terminal is turned on,
The power supply potential V _CC appears at the other connection terminal. At this time, the gate connected to the connection terminal where the power supply potential V _CC appears P
The MOS transistor is turned off. That is, if one of the two connection terminals has the logic "0", the other has the logic "1" without fail, and the logic "1" becomes the power supply potential V _CC . if,
When the level assurance circuits 13 to 15 are not added, the first circuit 11
And since the second circuit 12 is an NMOS type transistor,
If V _TH is the threshold potential of the NMOS transistor, the level of logic “1” output to the drain is only V−V _TH <V _CC (the source input voltage of the NMOS transistor is V).

Logic "1" less than the power supply potential V _CC, they can be used to increase the power consumption by the power source potential V _CC direct current flows to the ground potential GND in a device receiving this signal, or decrease the margin for noise. Therefore, it is necessary to guarantee the level of logic "1" to the power supply potential V _CC by providing the level guarantee circuits 13 to 15.

Next, the first XNOR signal from signal line 201 and signal line 202
The first XOR signal from C and the carry input signal Cin as a pair of complementary carry input signals input to terminals 5 and 6, respectively.
By inputting and its negative signal () to the second circuit 12, the second XOR signal appears on the signal line 203 and the second XNOR signal appears on the signal line 204. The relationship between (Cin, ▲ ▼), (first XNOR, first XOR) and output (second XOR, second XNOR) is shown in FIG. A level guarantee circuit 14 for guaranteeing the "1" level is connected to this. Second XOR signal from signal line 203 and signal line
The second XNOR signal from 204 is the inverting amplifier circuit 16, 17 respectively.
And the outputs of the inverting amplifier circuits 16 and 17 are
The sum signal S, which is a pair of sum signals complementary to 7 and 8, and its negation signal are output.

The carry input signal Cin and its negation signal ▲ ▼ input to the terminals 5 and 6 are simultaneously opened and closed by the first XNOR signal of the signal line 201 and the first XOR signal of the signal line 202. Is also entered. Then, the carry input signal Cin and its negation signal ▲ ▼ appear or are cut off as they are on the signal lines 205 and 206 according to the opening and closing of the transmission gate circuits 20 and 21. When the carry input signal Cin and its negation signal ▲ ▼ are cut off by the transmission gate circuits 20 and 21, in the carry signal erasing circuit 22 or the carry signal generating circuit 23, the augend signal pair A, and the addend signal. Pair B,
Due to this, a carry generation signal and a carry cancellation signal are generated and appear on the signal line 205 or the signal line 206. Here, FIG. 4 shows how the signal lines 205 and 206 are changed by the augend signal A and the addend signal B.

The signal lines 205 and 206 are connected with a level assurance circuit 15 and inverting amplifier circuits 18 and 19 for guaranteeing a “1” level, respectively, and outputs of the inverting amplifier circuits 18 and 19 are complementary carry to terminals 9 and 10, respectively. The carry output signal CO, which is a pair of output signals, and its negation signal ▲ ▼ are output.

Next, paying attention to the signal propagation operation of the full adder circuit of the present invention, a propagation path when a signal is transmitted from the input signal pair B to the sum output pair S will be described as an example.

B, the gate at the previous stage for driving the signal pair has a gate capacitance of one MOS transistor in the carry signal erasing circuit 22 or the carry signal generating circuit 23 and a second transistor through the MOS transistor in the first circuit 11. Two gate capacitances of the MOS transistor in the circuit 12 (and the gate capacitances of the first and second gate circuits 20 and 21 are also added by the B signal) and stored in the parasitic capacitance of the wiring up to that point. Driving the electric charge and the direct current for inverting the level assurance circuit 13,
The signal is transmitted to the third and fourth input terminals of the circuit 12 of FIG.

Then, the conduction / non-conduction of each MOS transistor in the second circuit 12 is changed by that, and the negation circuit is passed through the MOS transistor in the second circuit 12 in which the previous circuit driving the Cin signal pair is conductive. Input end capacitance of 16 and 17, electric charge stored in the parasitic capacitance of the wiring up to that, and level assurance circuit
DC circuit for inverting 14 and drive
And propagate the signal to the 17 input terminals.

Then, the negation circuits 16 and 17 convert the input signal into S,
Propagation to the signal and propagation from B, signal to S, signal is achieved.

The input signal pair B, carry output signal pair CO, ▲ ▼
First and second gate circuits for signal propagation to the
The paths to 20, 21 are similar to the sum output signal pair S, and the propagated signal brings the first and second gate circuits into the conductive state.

Next, when the circuit at the previous stage that drives the Cin signal pair becomes conductive,
The charge accumulated in the input terminal capacitances of the NOT circuits 18 and 19 and the parasitic capacitance of the wiring up to that point and the DC current for inverting the level assurance circuit 15 are driven through the first and second gate circuits 20 and 21. , The signal is transmitted to the input terminals of the negation circuits 18 and 19. The negating circuits 18 and 19 send this signal to their output terminals 9 and 1, respectively.
By transmitting to 0, signal propagation from the input signal pair B, to the carry output signal pair CO, ▲ ▼ is achieved.

For the signal propagation from the input signal pair A, the preceding circuit driving it is equivalent to the gate capacitance of two MOS transistors in the first circuit and the carry signal erasing circuit 22 or the carry signal generating circuit 23. Driving the gate capacitance of one of the MOS transistors in the first circuit and the parasitic capacitance of the wiring up to that, and transmitting the signal to the gate input terminal of the MOS transistor in the first circuit,
As a result, after determining the conduction / non-conduction of each transistor in the first circuit, in the same sequence as the signal propagation path from the input signal pair B, the input signal pair A, each output signal pair S,
Achieve the propagation of signals to CO, ▲ ▼.

Further, the signal propagation from Cin, ▲ ▼ is also the signal propagation from B, the second circuit 12 and the first and second gate circuits.
The sequence is the same after the conduction state of the MOS transistors in 20, 21 is determined.

As described above, in the circuit of the present invention, it is not necessary to internally generate the negative signal, so that the signal propagation delay is reduced. Also, a second circuit consisting of four MOS transistors is provided between the Cin signal pair and the output signal S pair, the Cin signal pair passes through the source and drain paths of the second circuit, and the gate thereof receives the signal from the input signal A, B pair. Since it is controlled by, the Cin signal pair is
In addition to being input to the gates of the second gate circuits 20 and 21,
Since it is necessary to determine the logic of the circuit 12 of, the load of the circuit in the previous stage that drives the Cin signal pair is heavy, while the input signal pair, B, and A determines the logic of the first circuit 11 except Only the signals are input to the gates of the carry signal generating circuit 22 and the carry signal erasing circuit 23, and the load on the circuit at the previous stage for driving the input signal pair B, A is reduced. Therefore Ci
Compared with the signal propagation delay from n signal pairs, the signal propagation delay from the input signal pairs A, and B, which was slow, can be made faster, and as a result, the signal propagation delay between each input signal pair and each output signal pair. Can be made uniform. Therefore, high-speed operation can be achieved and the parallel multiplier can be speeded up.

In the above embodiment, the first and second gate circuits are constructed by using N-type MOS transistors.
An OS transistor or both N and P type transistors may be used at the same time, and the same effect as described above can be obtained.

〔The invention's effect〕

As described above, according to the full adder circuit of the present invention, the first exclusive OR signal and the first negative exclusive signal are input with the complementary addend signal pair and the complementary addend signal pair. A first circuit for outputting a logical sum signal, and a complementary sum signal pair with a carry input signal pair complementary to the first exclusive logical sum signal and the first negative exclusive logical sum signal as inputs A second circuit for outputting a second exclusive OR signal and a second negative exclusive OR signal, and the complementary carry input signal pair respectively for the first exclusive OR signal and the second exclusive OR signal. First and second gate circuits for passing and blocking using at least one of the first negative exclusive-OR signals, and the addend when the first and second gate circuits are in a blocking state. A carry output signal line pair depending on the signal pair and the augend signal pair. A carry signal generating circuit and a carry signal erasing circuit that generate a carry generating signal and a carry erasing signal by setting one of them to a predetermined potential, and the first and second circuits, 1st, 2nd, 3rd,
It is composed of a fourth MOS transistor, and has a first and a second M
The sources of the OS type transistors are both connected to the first input terminal thereof, the sources of the third and fourth MOS type transistors are both connected to the second input terminal thereof, and the sources of the first and fourth MOS type transistors are connected together. The gate is the third together
, The gates of the second and third MOS type transistors are both connected to the fourth input terminal thereof, and the drains of the first and third MOS type transistors are connected to the output terminal of the exclusive NOR operation. And the second and fourth MO
The drain of the S-type transistor is used as an exclusive OR output terminal, and the first and second input terminals of the second circuit form a pair, and the complementary carry input signal pair is input to the input terminal pair. The third and fourth input terminals of the second circuit form a pair, and the first exclusive OR signal complementary to the first circuit and the first negative exclusive signal are coupled to the input terminal pair. Since a pair of logical sum signals is input, it is not necessary to make a negative signal inside, and the carry input signal pair Cin, which can operate at high speed, has a heavy load on the preceding stage for driving Cin, ▲ ▼. The input signal pair B with a large number of signal propagation stages is configured to reduce the load on the circuit at the previous stage that drives, so compared to the signal propagation delay from the carry input signal, the slower input signal pair A ,, The signal propagation delay from B, can be increased, resulting in each input signal pair and each output signal. To achieve high-speed operation is possible equalize the signal propagation delay of pairs, there is an effect of obtaining a full adder circuit which can achieve high-speed parallel multiplier.

[Brief description of drawings]

FIG. 1 is a diagram showing a full adder circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing in FIG. 1 that (A,) and (B,) are input to the level assurance circuit and output (first XOR, first
3 is a diagram showing the relationship of (XNOR), FIG. 3 is input to the second circuit in FIG. 1 (Cin, ▲ ▼), (first XNOR,
FIG. 4 shows the relationship between the first XOR) and the output (second XOR, second XOR). FIG. 4 shows what kind of signal line the augend signal and the augend signal in FIG. FIG. 5 is a diagram showing a conventional full adder circuit, FIG. 6 is a diagram showing a 4-bit × 4-bit parallel multiplication circuit by a carry save adder method, and FIG. 7 is a diagram showing FIG. Inside AND addition circuit 50
It is a circuit diagram of. In the figure, 11 and 12 are first and second circuits, 13 to 15 are level assurance circuits, 16 to 19 are inverting amplifier circuits, 20 and 21 are transmission gate circuits, 22 is a carry signal erasing circuit, and 23 is a digit. It is a raising signal generation circuit. The same reference numerals in the drawings indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Shuichi Kato 4-1-1 Mizuhara, Itami-shi, Hyogo Prefecture LS Electric Co., Ltd. LSE Research Institute (72) Inventor Takashi Oya 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Co., Ltd. LSI Research Laboratory (72) Inventor Norihiko Shimazu 4-1-1 Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Co., Ltd. LSI Research Laboratory (56) Reference JP-A-63-124133 (JP, A) JP-A-61-183738 (JP, A)

Claims (1)

[Claims] 1. A first circuit which inputs a complementary addend signal pair and a complementary augend signal pair and outputs a first exclusive OR signal and a first negative exclusive OR signal. A carry input signal pair complementary to the first exclusive OR signal and the first negative exclusive OR signal is used as an input, and a second exclusive OR signal is used as a complementary OR signal pair. Two
A second circuit for outputting a negative exclusive-OR signal of at least one of the first exclusive-OR signal and the first negative-exclusive-OR signal, respectively. A first and a second gate circuit for passing and blocking using one of the two, and a pair of the addend signal and the augend signal pair when the first and second gate circuits are in the blocking state. A carry signal generating circuit and a carry signal erasing circuit for generating a carry generating signal and a carry erasing signal by setting one of the carry output signal line pairs to a predetermined potential. And the second circuit is the first, second, third and fourth MOS
Type transistor, the sources of the first and second MOS type transistors are both connected to the first input terminal thereof, and the sources of the third and fourth MOS type transistors are both connected to the second input terminal thereof. , First and fourth
The gates of the MOS type transistors are both connected to the third input terminal thereof, the gates of the second and third MOS type transistors are both connected to the fourth input terminal thereof, and the gates of the first and third MOS type transistors are connected together. The drain serves as a negative exclusive OR output terminal, the drains of the second and fourth MOS type transistors serve as exclusive OR output terminals, and the first and second input terminals of the second circuit form a pair. Then, the complementary carry input signal pair is inputted to the input terminal pair, and the third and fourth input terminals of the second circuit form a pair, and the input terminal pair of the first circuit of the first circuit becomes Complementary first
A full adder circuit, to which a pair of the exclusive OR signal and the first negative exclusive OR signal is input.