JPH07334117A - Multilevel display device and method thereof - Google Patents

Abstract

PURPOSE:To provide multilevel display without generating flicker and damaging display quality by providing selection control means selecting/outputting one voltage level having a prescribed voltage level based on either of outputs of gradation pattern generating circuits. CONSTITUTION:When six bit gradation display data corresponds to the gradation having the intermediate voltage level of gradation voltages previously prepared in a gradation voltage generating circuit 501, the data are arithmetically processed in an arithmetic processing circuit 351 based on gradation compensating data of gradation pattern generating circuits 321a-321d selected by a selecting circuit 341. Four bit gradation display data subjected to the arithmetic processing are outputted to a X driver 101 through a liquid crystal controller 251. Consequently, since one displaying gradation is controlled based on at least two and more different gradation patterns, multilevel display is realized without generating flicker and damaging display quality at the time of multilevel display.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device such as a liquid crystal display device and an electroluminescence (EL) display device, and more particularly to a multi-gradation display device and a multi-gradation display method capable of multi-gradation display. .

[0002]

2. Description of the Related Art In recent years, in display devices typified by liquid crystal display devices, not only high definition but also multi-gradation display have been demanded. For each display pixel, a thin film transistor (hereinafter,
It is abbreviated as TFT. ) And the like are taken as an example of an active matrix type liquid crystal display device, each pixel electrode, a counter electrode facing the pixel electrode, and a liquid crystal held between the pixel electrode and the counter electrode. An image display is performed by holding a predetermined potential between the electrodes that are composed of the composition and that form one display pixel for one frame (F) period.

In such a liquid crystal display device, in order to prevent the deterioration of the liquid crystal composition, the voltage applied to the pixel electrode in order to realize the above-described multi-gradation display, for example, 64 (2 ⁶ ) gradation Since it is necessary to perform AC driving, the voltage level of 64 × 2 is required.

However, preparing 64 × 2 voltage levels increases the power consumption of the IC that constitutes the drive circuit,
Alternatively, it is not a preferable method in terms of cost. Therefore, as another method for realizing multi-gradation display, the voltage level of the gradation voltage applied to each pixel electrode is not made different according to the display gradation, but the voltage application period, that is, There is known a so-called pulse width modulation method in which the pulse width is changed to realize display corresponding to each gradation. However, such a method also has a problem that the display circuit is complicated and the control is difficult in multi-gradation display such as 64 (2 ⁶ ) gradation.

[0005]

As another method for solving the above-mentioned problems, one display period is formed by setting a plurality of consecutive frame (F) periods as one cycle, and a frame is turned on within one display period. (F) A so-called frame rate control (FRC) method is known, which realizes multi-gradation display by controlling the period. Also, for example, Japanese Patent Laid-Open No.
In addition to the above-mentioned FRC method, there are no.
There is also known a method in which a plurality of adjacent display pixels are used as one control unit and the frame (F) periods that are turned on between the adjacent display pixels are made different to prevent the occurrence of flicker.

According to such an FRC system, it is possible to eliminate the need for a plurality of gray scale voltages, and it is also possible to eliminate the disadvantages of the pulse width modulation system described above. However, it is necessary to further increase the number of frame (F) periods constituting one display period in order to realize further multi-gradation display by such an FRC method. For example, 64 (2 ⁶ )
If an attempt is made to realize multi-gradation display such as gradation, problems such as the multi-gradation display being visually unrecognized and flicker occurring due to an increase in the number of frame (F) periods occur. .

The present invention has been made in response to the above technical problems, and is capable of realizing multi-gradation display in which flicker does not occur and display quality is not impaired. It is an object of the present invention to provide a gradation display device and a multi-gradation display method.

[0008]

According to a first aspect of the present invention, there is provided a multi-gradation display device for displaying an image by selecting a predetermined voltage level according to input multi-gradation display data. And a display panel having display pixels of
Is a positive integer greater than or equal to 2) and a first gradation pattern generating circuit having a first gradation pattern for obtaining one display gradation in a frame period, and the first gradation pattern generating circuit for obtaining one display gradation in an m frame period. A second gradation pattern generation circuit having a second gradation pattern different from the gradation pattern; and the multi-gradation display data to be one display gradation based on the first gradation pattern or the second gradation pattern. When corresponding, a selection control means for selecting and outputting one of the predetermined voltage levels based on the output of either the first gradation pattern generating circuit or the second gradation pattern generating circuit. It is characterized by having and.

According to a second aspect of the invention, the multi-gradation display data according to the first aspect is k (k is a positive integer greater than 2).
It is characterized by being a bit digital signal.
The invention according to claim 3 is characterized in that the multi-gradation display device according to claim 2 is provided with a gradation voltage generating circuit for supplying a voltage level lower than 2 ^{k + 1} .

According to a fourth aspect of the invention, a display panel having a plurality of display pixels for displaying an image by selecting one of the voltage level groups based on the multi-gradation display data, and m (m Is a positive integer greater than or equal to 2) a first gradation pattern generating circuit for generating a first gradation pattern for obtaining one display gradation in a frame period, and the first gradation pattern generating circuit for obtaining one display gradation in an m frame period. A second gradation pattern generation circuit for generating a second gradation pattern different from the gradation pattern, and input k (k is a positive integer larger than j) bit multi-gradation display data for j-bit multi-gradation display Display data converting means for converting into data, and if the k-bit multi-gradation display data corresponds to one display gradation based on the first or second gradation pattern, the j-bit multi-gradation display data is converted into the first Or in the second gradation pattern It is characterized in that an arithmetic processing circuit for outputting performs arithmetic processing Zui.

According to a fifth aspect of the present invention, the first and second grayscale pattern generating circuits according to the fourth aspect include a plurality of display pixels as one control unit so that one display grayscale can be obtained in consecutive m frame periods. It is characterized by controlling as.

The invention according to claim 6 is characterized in that the first and second gradation pattern generating circuits according to claim 5 control m × m display pixels as one control unit. According to a seventh aspect of the present invention, the first grayscale pattern generation circuit according to the sixth aspect includes a first grayscale pattern in which a table composed of m × m grayscale compensation data is configured by m sheets, and a second grayscale pattern is provided. The gradation pattern generating circuit is characterized in that it has a second gradation pattern in which a table consisting of m × m gradation compensation data is composed of m sheets.

The invention according to claim 8 is characterized in that one control unit according to claim 5 is arranged in a substantially square arrangement. The invention according to claim 9 is characterized in that the first gradation pattern and the second gradation pattern according to claim 6 are configured based on a magic circle.

According to a tenth aspect of the present invention, in the multi-grayscale display device according to the fifth aspect, the first grayscale pattern or the second grayscale pattern generates a random number every m frame periods. It is characterized by being selected by the output from.

The invention described in claim 11 is a multi-gradation display method for displaying an image in accordance with input k (k is a positive integer greater than 2) bits multi-gradation display data. When the k-bit multi-gradation display data corresponds to one voltage level prepared in advance, the k-bit multi-gradation display data corresponds to i (i is a positive integer smaller than k) bits corresponding to the one voltage level. If the k-bit multi-gradation display data does not correspond to any of the voltage levels prepared in advance, the k-bit multi-gradation display data is converted to multi-gradation display data and output.
Bit multi-gradation display data is m (m is a positive integer of 2 or more)
A first gradation pattern generating circuit for generating a first gradation pattern for obtaining one display gradation in a frame period, and a second floor different from the first gradation pattern for obtaining the one display gradation in m frame periods It is characterized in that it is provided with conversion to i-bit multi-grayscale display data based on the output of either one of the second grayscale pattern generating circuits for generating a grayscale pattern and outputting.

[0016]

According to the multi-gradation display device and method of the present invention, as described above, the first gradation pattern for generating one display gradation in the m (m is a positive integer of 2 or more) frame period is generated. And a second gradation pattern generating circuit which is different from the first gradation pattern which produces one display gradation in m frame periods.
A second gradation pattern generating circuit for generating a gradation pattern.

Then, the input multi-gradation display data is
When the display gradations of the first gradation pattern and the second gradation pattern are supported, a predetermined value prepared in advance according to the output of either the first gradation pattern generating circuit or the second gradation pattern generating circuit. Converted to correspond to the voltage level. Therefore, gradation display corresponding to a voltage level that is not prepared in advance is possible.

Further, since one display gradation is controlled on the basis of at least two or more different gradation patterns, flicker does not occur even when multi-gradation display is realized, and the display quality is impaired. It is possible to realize multi-gradation display without any need.

[0019]

EXAMPLE As an example of the present invention, 64 (2
⁶ ) An active matrix type liquid crystal display device for displaying gradation will be described as an example with reference to the drawings. As shown in FIG. 1, this liquid crystal display device (1) has (640 × 3) rows ×
Liquid crystal panel (11) capable of color display having display pixels arranged in a matrix of 480 columns, and this liquid crystal panel
An X driver (101) and a Y driver (201) electrically connected to (11), a liquid crystal controller (251) for controlling the X driver (101) and the Y driver (201), and an external input. A gradation signal conversion circuit (300) for converting 6-bit gradation display data to 4-bit gradation data and outputting it to the liquid crystal controller (251), and a reference voltage for each frame (F) period as shown in FIG. Grayscale voltages (V0, V1, V2 ... V) composed of 16 square wave voltages whose polarities are inverted with respect to
15) is output to the X driver (101) gradation voltage generation circuit (5
01) and are configured. In this example,
Although the frame inversion drive is taken as an example, when the frame inversion drive is combined with the line inversion drive in order to further prevent the occurrence of flicker, the polarity is inverted with respect to the reference voltage every one frame (F) period. At the same time, a square wave voltage whose polarity is inverted with respect to the reference voltage every predetermined horizontal scanning period may be used as the gradation voltage (V0, V1, V2 ...

This liquid crystal panel (11) is of a so-called active matrix type and has a TF for each display pixel electrode (21).
T (31) is provided. The scanning line (13) connected to the TFT (31) has a Y driver (2
01) supplies the scan pulse (VG) for a predetermined period of time T
The FT (31) becomes conductive. This allows the X driver (1
The gradation voltage from the signal line (15) connected to (01) is applied to the TFT (3
1) is written to the display pixel electrode (21) via the liquid crystal capacitor (Clc) and the auxiliary capacitor (Cs) provided in parallel with the liquid crystal capacitor (Clc) by the auxiliary capacitor line (51) for one frame (F ) It is a mechanism that the image is displayed for a period of time.

The X driver (101) shifts the 4-bit gradation display data input as shown in FIG.
K) and the start pulse (ST), the shift register (111) that transfers sequentially, the decoder (113) that converts the output from the shift register (111), and the 16 levels according to the output of the decoder (113). A selection circuit (115) for selecting and outputting one of the adjusted voltages (V0, V1, ... V15) and a latch circuit (117) for holding this output for a predetermined period.

Next, the gradation signal conversion circuit (300) of the liquid crystal display device (1) will be described. This gradation signal conversion circuit
(300) corresponds to 6-bit gradation display data input from the outside with any of 16 gradation voltages (V0, V1, ... V15) prepared in the gradation voltage generating circuit (501). A gradation control circuit (303) for converting into 4-bit gradation display data is provided.

In the gradation signal conversion circuit (300), the input 6-bit gradation display data is supplied to the gradation voltage generation circuit (5
01) corresponds to the grayscale voltage prepared in advance, the converted 4-bit grayscale display data is output without arithmetic processing, and the input 6-bit grayscale display data is input to the grayscale voltage generation circuit ( (501) corresponds to the gray scale corresponding to the intermediate voltage level of the gray scale voltage prepared in advance, the arithmetic processing circuit (351) which outputs after performing the arithmetic processing for expressing the intermediate gray scale Is equipped with.

The arithmetic processing circuit (351) includes a first gradation pattern generating circuit (321a) and a second gradation pattern generating circuit (321).
b), connected to the third gradation pattern generation circuit (321c) and the fourth gradation pattern generation circuit (321d) via the selection circuit (341).

In the selection circuit (341), the 6-bit gray scale display data input from the outside is previously stored in the gray scale voltage generation circuit (5
01) corresponding to the intermediate display gray scale between the gray scale voltages, the first to the first of the first to the second are output according to the output of the random number generation circuit (313) which generates a random number every 6 frame (F) periods. Any one of the four gradation pattern generation circuits (321a), (321b), (321c), (321d) is selected. According to this embodiment, when the output of the random number generation circuit (313) is {0}, the first gradation pattern generation circuit (321a) is used, and when the output of the random number generation circuit (313) is {1}, the first gradation pattern generation circuit (321a) is output. 2 gradation pattern generation circuit (321b) is a random number generation circuit
When the output of (313) is {2}, the third gradation pattern generating circuit (321c) is, and when the output of the random number generating circuit (313) is {3}, the fourth gradation pattern generating circuit (321d) is. Each is configured to be selected.

First to fourth gradation pattern generation circuits (321a),
As shown in FIG. 4, (321b), (321c), and (321d) represent the display pixel area of the liquid crystal panel (11) in a quadrangular shape with six rows and six columns adjacent to each other. Pixels (6 × 6 matrix) are used as one control unit, and one display screen is divided into blocks of 80 rows × 240 columns for control. And each gradation pattern generation circuit (321a), (321b), (321c), (321d)
Is for controlling each control unit with a continuous 6 frame (F) period as one display period. Therefore, each gradation pattern is configured to realize one display gradation with six tables each including 36 gradation compensation data for realizing one display gradation, and each gradation pattern generating circuit (321a) ,
Such gradation patterns for 5 gradations are stored in (321b), (321c), and (321d), respectively.

Further, each gradation pattern generating circuit (321a), (32
1b), (321c), and (321d) are 6-frame counters for selecting one of the first to sixth tables of each gradation pattern, and 6 for obtaining gradation compensation data corresponding to display pixels from one table. It is connected to a designated circuit (311) consisting of a line counter and a 6-column counter.

According to the gradation signal conversion circuit (300) thus constructed, the 6-bit gradation display data inputted from the outside is converted into the 4-bit gradation display data by the gradation control circuit (303). At the same time, when the 6-bit gradation display data corresponds to the gradation voltage prepared in advance in the gradation voltage generating circuit (501), the converted 4-bit gradation display data is arithmetically processed by the arithmetic processing circuit (351). LCD controller (2
51) to the X driver (101), and the 6-bit gradation display data corresponds to the gradation of the intermediate voltage level of the gradation voltage prepared in advance in the gradation voltage generation circuit (501). , The gradation pattern generation circuit (321a), (321b), (321c), (321d) selected by the selection circuit (341) performs the arithmetic processing in the arithmetic processing circuit (351) based on the gradation compensation data, The arithmetically processed 4-bit gradation display data is output to the X driver (101) via the liquid crystal controller (251).

The method for realizing the intermediate display gradation used in the liquid crystal display device (1) of this embodiment will be described in detail below. In a liquid crystal display device in which gray scale voltages (V0, V1, ... V15) composed of 16 square wave voltages are prepared, it is possible to select 16 gray scale voltages (V0, V1, ... V15) by selecting one of the gray scale voltages. It is possible to display gradation images. Therefore, in this liquid crystal display device (1), a gray scale voltage (V0, V1, ... V15) composed of 16 square wave voltages is used, and
The following display operation is performed in order to realize the image display of four gradations.

One gradation voltage (Vi) (i = 0,1,2, ..., 14)
And in order to realize an intermediate ⅙ gradation with another gradation voltage (Vi + 1) adjacent thereto, gradation is performed for 5 frame (F) periods during continuous 6 frame (F) periods. Voltage (Vi
) For the remaining 1 frame (F) period, the gradation voltage (Vi + 1
) Control to select. One gradation voltage (Vi),
In order to realize 2/6 gray scale between the gray scale voltages (Vi + 1) adjacent to this, 4 during 4 consecutive frame periods (F)
The gray scale voltage (Vi) is selected in the frame (F) period, and the gray scale voltage (Vi + 1) is selected in the remaining two frame (F) periods. In order to realize 3/6 gradation between one gradation voltage (Vi) and the gradation voltage (Vi + 1) adjacent thereto, 3 frames ( The gray scale voltage (Vi) is selected during the F) period, and the gray scale voltage (Vi + 1) is selected during the remaining three frame (F) periods. Further, in order to realize an intermediate 4/6 gray scale between one gray scale voltage (Vi) and a gray scale voltage (Vi + 1) adjacent thereto, two frames are provided during a continuous 6 frame (F) period. The gray scale voltage (Vi) is selected in the (F) period, and the gray scale voltage (Vi + 1) is selected in the remaining four frame (F) periods. Further, in order to realize a 5/6 gray scale which is an intermediate between one gray scale voltage (Vi) and the gray scale voltage (Vi + 1) adjacent thereto, one frame is produced during a continuous 6 frame (F) period. The gray scale voltage (Vi) is selected during the (F) period, and the gray scale voltage (Vi + 1) is selected during the remaining 5 frame (F) periods.

As described above, the combination of the control of the frame (F) period and the 16 gradation voltages (V0, V1, ... V15) theoretically realizes 91 gradations as shown in FIG. can do. In this embodiment, 6 gray scales are selected from among 91 gray scales by selecting 64 gray scales with a particularly preferable display state.
A four-gradation image display is realized. For example, in this embodiment, the gray scale voltage (V0) and the gray scale voltage (V
1) and 1/6 gradation (theoretical gradation 2 in FIG. 5) and 5 /
6 gradations (theoretical gradation 6 in FIG. 5) and 1/6 gradation between the gradation voltage (V1) and the gradation voltage (V2) (theoretical gradation 8 in FIG. 5) are used for display. , 1/6 gradation and 5/6 gradation between the other gradation voltage (Vi) and the gradation voltage (Vi + 1) are not used for display. The 1/6 gradation or the 5/6 gradation is used only in the area where the gradation is difficult to recognize because flicker may be visually recognized depending on the display image.

Next, each gradation pattern used in this embodiment will be described. The selection of each gradation pattern in this embodiment is considered based on the concept of the magic circle. The magic circle is configured, for example, by assigning numbers 1 to N ² to each matrix of an N × N matrix of N rows and N columns so that the sum of the numbers in each row and each column is equal. It is something. In addition, the complete magic circle is configured by being assigned so that the total numbers are equal in each diagonal.

The gradation pattern of this embodiment is composed of a 6 × 6 matrix and has no perfect magic circle [(4r + 2) × (4r + 2) matrix: r is a positive number of 1 or more]. Therefore, it is constructed based on the magic circle.

In FIG. 6, in the magic circle of 6 × 6 matrix, 1 is assigned to the matrix to which the numbers 1 to 6 are assigned,
2 is assigned to the matrix assigned the numbers 7 to 12.
1 is assigned to the matrix assigned the numbers 3 to 18.
Assign 4 to 2 in the matrix assigned the numbers 9 to 24
3 is assigned to the matrix assigned the numbers 5 to 31.
6 shows auxiliary magic circles each having 6 assigned to a matrix to which numbers 1 to 36 are assigned.

The gradation patterns are selected in the following manner by using the auxiliary magic circle thus constructed. If one display pixel realizes 1/6 gray scale between the gray scale voltage (Vi) and the gray scale voltage (Vi + 1) adjacent to the gray scale voltage (Vi), 1 in 6 consecutive frame (F) periods. The gradation voltage (Vi + 1) may be selected only during the frame (F) period, and the gradation voltage (Vi) may be selected during the other five frame (F) periods. Therefore, as shown in FIG. 7A, the gradation compensation data {1} is allocated to the matrix to which the numeral 1 in FIG. 6 is allocated, and the gradation compensation data {0} is allocated to the other matrixes. The first table of the six tables for realizing 1/6 gradation of the tonal pattern is configured. Further, as shown in FIG. 7B, the gradation compensation data {1} is allocated to the matrix to which the numeral 2 in FIG. 6 is allocated, and the other gradation compensation data {0} is allocated to the first gradation. 6 to realize 1/6 gradation of pattern
In the second table in the table, gradation compensation data {1} is allocated to the matrix to which the numeral 3 is allocated, and gradation compensation data {0} is allocated to the other ones, and 1/6 gradation of the first gradation pattern The third table of the six tables for realizing the above is assigned the gradation compensation data {1} to the matrix to which the number of 4 is assigned, and the other is assigned the gradation compensation data {0} and the first gradation pattern is assigned. The fourth table out of the six tables for realizing the 1/6 gradation is assigned the gradation compensation data {1} to the matrix to which the numeral 5 is assigned, and the other is assigned the gradation compensation data {0}. The 5th table out of the 6 tables for realizing 1/6 gradation of the 1st gradation pattern, the gradation compensation data {1} is further allocated to the matrix to which the numeral of 6 is allocated, and the others are gradation. Assign compensation data {0} Sixth table in the 6 tables for implementing the 1/6 gradation of the first gradation pattern Te the constituting respectively.

By sequentially repeating the first to sixth tables configured as described above with 6 frame (F) periods as one display period, the gray scale voltage (Vi) and the adjacent voltage to the gray scale voltage (Vi) in the 6 frame (F) periods. It is possible to realize 1/6 gradation between the gradation voltage (Vi + 1) and the gradation voltage.

When one display pixel realizes 2/6 gray scale between the gray scale voltage (Vi) and the gray scale voltage (Vi + 1) adjacent to the gray scale voltage (Vi), 6 consecutive frames (F). 2 during the period
Select the gradation voltage (Vi + 1) only during the frame (F) period,
In the other four frame (F) periods, the gray scale voltage (Vi) may be controlled to be selected. Therefore, the gradation compensation data {1} is added to the matrix to which the numbers 1 and 2 shown in FIG. 6 are assigned.
, And gradation compensation data {0} for the others,
The first table of the six tables for realizing 2/6 gradation of the first gradation pattern is configured. Further, the gradation compensation data {1} is assigned to the matrix to which the numbers 3 and 4 shown in FIG. 6 are assigned, and the gradation compensation data {0} is assigned to the other matrixes, and the 2 / 6th floor of the first tone pattern is assigned. A second table among the six tables for realizing the key is constructed. Similarly, the third to sixth tables out of the six tables for realizing 2/6 gradation of the first gradation pattern are configured.

Similarly, one display pixel has a gradation voltage (Vi
) And the gradation voltage (Vi + 1) adjacent to
First to sixth tables (see FIG. 8) for realizing 6 gradations, one display pixel is on the 3 / 6th floor between the gradation voltage (Vi) and the gradation voltage (Vi + 1) adjacent thereto. First to sixth tables (see FIG. 9) for realizing the gradation, one display pixel displays 4/6 gradations between the gradation voltage (Vi) and the gradation voltage (Vi + 1) adjacent thereto. 1st to 6th tables (Fig.
0), one display pixel realizes 5/6 gradation between the gradation voltage (Vi) and the gradation voltage (Vi + 1) adjacent thereto (see FIG. 11). ) Respectively.

The gradation patterns shown in FIGS. 7 to 11 configured as described above are the first gradation pattern generation circuit (321a).
Remembered in. In addition, the gradation pattern configured based on other magic circles is used for the second to fourth gradation pattern generation circuits (3
21b), (321c), and (321d).

FIG. 12 shows the second gradation pattern generation circuit (321b).
The gray scale pattern for expressing the 2/6 gray scale stored in FIG. 13 and the gray scale pattern for expressing the 2/6 gray scale stored in the third gray scale pattern generating circuit (321c) are shown in FIG. , Figure 1
4/2 / stored in the third gradation pattern generation circuit (321c)
The gradation patterns for expressing 6 gradations are shown respectively.

Then, each such gradation pattern is R
Each gradation pattern generation circuit (321a) composed of AM (321a), (321
b), (321c), (321d) are stored in advance. Next, FIG.
The specific operation of this embodiment will be described with reference to one display state of the liquid crystal panel shown in FIG.

First, when displaying the first gradation on the display pixel (1, 1), 6-bit gradation display data {000000} corresponding to the first gradation is inputted. This 6-bit gradation display data {000000} is converted to the gradation control circuit (303).
Is converted into a 4-bit gradation signal {0000} corresponding to 16 gradation voltages (V0, V1, ... V15). The 6-bit gradation display data {000000} for displaying the first gradation corresponds to the gradation voltage (V0) of the prepared 16 gradation voltages (V0, V1, ... V15). Therefore, the 4-bit grayscale data {0000} is output to the X driver (101) via the liquid crystal controller (251) without being processed by the arithmetic processing circuit (351). Then, the X driver (101) selects and outputs the gradation voltage (V0) based on the 4-bit gradation data {0000}, and the first gradation is displayed on the display pixel (1, 1). Is displayed.

When displaying the fourth gradation on the display pixel (1, 2), 6-bit gradation display data {000011} corresponding to the fourth gradation is input. The 6-bit gradation display data {000011} is converted into a 4-bit gradation signal {0000} corresponding to 16 gradation voltages (V0, V1, ... V15) by the gradation control circuit (303). And
The 6-bit gradation display data {000011} for displaying the fourth gradation is provided with 16 prepared gradation voltages (V
0, V1, ... V15) corresponding to an intermediate gradation, that is, 3/6 gradation which is between the gradation voltage (V0) and the gradation voltage (V1).

Therefore, the random number generation circuit (313) generates random numbers from {0} to {3} by the output from the gradation control circuit (303), and in response to this, the gradation pattern generation circuit (321).
One corresponding to 3/6 gradation of a), (321b), (321c), and (321d) is selected.

Here, it is assumed that the random number generation circuit (313) generates {0} and the first gradation pattern generation circuit (321a) is selected. Based on the display pixels (1, 2), the gradation pattern generation circuit (321a) causes the designation circuit (311) to output data of 1 line and 2 columns of the first frame, that is, FIG.
The gradation compensation data {1} in the table of (a) is output. Therefore, the 4-bit gradation signal {0000} is added to the gradation compensation data {1} from the gradation pattern generating circuit (321a) by the arithmetic processing circuit (351), and the arithmetic processing circuit (351) outputs the gradation compensation data {1}. 4-bit gradation data {0001} is output to the X driver (101) via the liquid crystal controller (251). Then, the X driver (101) produces a gradation voltage (V1) based on the 4-bit gradation data {0001}.
Is selected and output. If the second frame also displays the fourth gradation similarly to the first frame, the gradation compensation data {0} shown in FIG. The gradation voltage (V0) is selected and output based on the gradation data {0000}.

Further, if the third frame also displays the fourth gradation similarly to the first and second frames, the gradation compensation data {1} shown in FIG. The addition processing is performed, and the gradation voltage (V1) is selected and output based on the 4-bit gradation data {0001}.
Further, if the fourth gradation is similarly displayed in the fourth to sixth frames, the gradation voltage (V0) or the gradation is calculated based on the gradation compensation data shown in FIGS. Voltage (V1
) Is selectively output.

When the 6-bit gray scale display data {000011} for displaying the fourth gray scale is input in this way, the continuous 6 frames are set as one display period and the fourth gray scale is displayed.
A gradation display is realized.

By the way, in the above-mentioned case, the 6-bit gradation display data input to the display pixel (2, 1) is a 6-bit gradation for displaying the fourth gradation in any period of 6 frames (F). Although the case of the gradation display data {000011} is shown, the 6-bit gradation display data to be input may be different in the period of 2 frames (F) in, for example, a moving image.

Therefore, 6-bit gray scale display data {corresponding to the fifth gray scale in the period of 2 frames (F), that is, 4/6 gray scale which is between the gray scale voltage (V0) and the gray scale voltage (V1) { 0
A case where "00100} is input will be described. This 6-bit gradation display data {000100} is the 4-bit gradation signal {0000} corresponding to 16 gradation voltages (V0, V1, ... V15) by the gradation control circuit (303) as described above. Is converted to. Then, 6-bit gradation display data {00010 for displaying the fifth gradation
0} are 16 prepared gradation voltages (V0, V1, ... V)
15) is a halftone that does not correspond to 15) and is similarly controlled by the first gradation pattern generation circuit (321a). That is, in the 4-bit gradation signal {0000}, the gradation compensation data {1} of 1 line and 2 columns of the second frame shown in FIG. The gradation data {0001} is output to the X driver (101) via the liquid crystal controller (251). Then, the X driver (101) selects and outputs the gradation voltage (V1) based on the 4-bit gradation data {0001}.

As described above, the 6-bit gradation display data input in a moving image or the like is a frame (1F) in one display pixel.
In the case of different gray scales, the display may be performed for each frame (1F) based on the input 6-bit gray scale display data. Actually, 16 gray scale voltages (V0, V1, ...).
Even if there are gradations that cannot be expressed by V15), it is difficult to visually distinguish the gradations in a moving image, so there is almost no problem.

As described above, after the display for 6 frame (F) period which is one display period in this embodiment, the random number generation circuit (313) is output again from the gradation control circuit (303). Random numbers {0} to {3} are generated, and the gradation pattern generation circuits (321a), (321b), (321) are generated according to the random numbers.
One of c) and (321d) is selected, and an intermediate display gradation is realized based on the gradation pattern of any one of the gradation pattern generation circuits (321a), (321b), (321c), and (321d). To do.

As described above in detail, in this embodiment, 1
It is possible to realize 64-gradation display with only 6 gradation voltages (V0, V1, ... V15). In this embodiment, the grayscale pattern generation circuits (321a), (321b), (321c) are used even though halftone display is realized with a continuous 6-frame (F) period as one display period. Since each gradation pattern stored in (, 321d) is constructed based on the concept of the magic circle, it is possible to prevent flicker.

Further, in this embodiment, the random number generation circuit (31
3) a gradation pattern generation circuit (321) having different gradation patterns according to the random numbers {0} to {3} generated by
One of a), (321b), (321c), and (321d) is selected. As a result, even when displaying a still image or the like, it is possible to further prevent the change cycle of the gradation pattern from being visually confirmed and causing flicker.

By the way, in this embodiment, the display of the halftone is set to one continuous 6-frame (F) period,
The case where it is realized by the gradation pattern composed of 36 gradation compensation data composed of 6 × 6 matrix has been described, but it is 7 × when the continuous 7 frame (F) period is one cycle.
A gradation pattern composed of 49 gradation compensation data composed of 7 matrices may be used, or realized by 16 gradation patterns composed of 4 × 4 matrix with one continuous 4 frame (F) period as one display period. You may combine with the case. When used in combination as described above, for example, 1/4 gray scale, 2/4 gray scale, and 3/4 gray scale realized with 4 frame (F) periods as one display period,
2 realized with 6 frame (F) periods as one display period
It is preferable to use / 6 gradation and 4/6 gradation, respectively.

By the way, in the above-mentioned embodiment, 16 gradation voltages (V0, V1, ... V15) are prepared, but the present invention is not limited to this and can be combined with various gradation voltages. It works effectively.

In this embodiment, one control unit has 36 display pixels arranged in a square, but it does not have to be a square arrangement. Further, in this embodiment, as a method for realizing a display gray level corresponding to an intermediate voltage level of gray scale voltages (V0, V1, ... V15) prepared in advance, adjacent gray scale voltages are adjacent in a plurality of frame (F) periods. Although one of the grayscale voltages is selectively output, it is not always necessary to select adjacent grayscale voltages, and a grayscale intermediate between the grayscale voltage (V1) and the grayscale voltage (V2) is required. When displaying, gradation voltage (V0) and gradation voltage (V2) or gradation voltage (V0)
And the gradation voltage (V3) may be selected, or two or more kinds of gradation voltages may be selected in a plurality of frame (F) periods. With such control,
It is possible to realize a higher number of gradations with a smaller gradation voltage. In this embodiment, the active matrix type liquid crystal display device has been described as an example, but it can be applied to various display devices other than this and effectively acts.

[0057]

According to the present invention, when the input multi-gradation display data corresponds to an intermediate voltage level of the voltage levels prepared in advance, a plurality of types based on the multi-gradation display data are provided. One grayscale pattern is randomly selected from the grayscale patterns, and the selection control means controls to select and output a predetermined voltage level in accordance with this output, so that a large number of levels can be obtained with a small number of voltage levels. Not only is it possible to display the tones, but it is also possible to suppress the occurrence of flicker and display a high-quality display image.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of an X driver in FIG.

3 is a diagram showing a gradation voltage waveform generated by the gradation voltage generating circuit in FIG.

FIG. 4 is a diagram for explaining a control unit in the liquid crystal display device of this embodiment.

FIG. 5 is a diagram for explaining the concept of multi-gradation display in the liquid crystal display device of this embodiment.

FIG. 6 is a diagram showing an auxiliary magic circle formed on the basis of one magic circle in the liquid crystal display device of this embodiment.

7 is a diagram showing a gradation pattern for realizing 1/6 gradation stored in the first gradation pattern generating circuit in FIG. 1;

8 is a diagram showing a gradation pattern for realizing 2/6 gradation stored in the first gradation pattern generating circuit in FIG. 1;

9 is a diagram showing a gradation pattern for realizing 3/6 gradation stored in the first gradation pattern generating circuit in FIG. 1;

10 is a diagram showing a gradation pattern for realizing 4/6 gradation stored in the first gradation pattern generating circuit in FIG. 1;

11 is a diagram showing a gradation pattern for realizing 5/6 gradation stored in the first gradation pattern generation circuit in FIG. 1;

12 is a diagram showing a gradation pattern for realizing 2/6 gradation stored in a second gradation pattern generation circuit in FIG. 1;

13 is a diagram showing a gradation pattern for realizing 2/6 gradation stored in a third gradation pattern generating circuit in FIG.

FIG. 14 is a diagram showing a gradation pattern for realizing 2/6 gradation stored in a fourth gradation pattern generation circuit in FIG. 1;

FIG. 15 is a diagram showing one display example of the liquid crystal display device of this embodiment.

[Explanation of symbols]

 (1) ... liquid crystal display device (11) ... liquid crystal panel (101) ... X driver (201) ... Y driver (251) ... liquid crystal controller (300) ... gradation signal conversion circuits (311a), (311b), (311c) ), (311d)… Gradation pattern generation circuit (311)… Designation circuit (313)… Random number generation circuit (341)… Selection control circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuyoshi Yamamoto 50 Kamimabe, Yobu, Himeji City, Hyogo Prefecture, Ltd. Inside the Himeji Plant, Toshiba Corp. ) Inventor Hiroyoshi Murata 50, Kamimabe, Yobu, Himeji, Hyogo Pref., Inside the Himeji Plant, Toshiba Corporation (72) Inventor, Hiroyuki Hamabe, 50, Kamiburo, Himeji, Himeji

Claims (11)

[Claims] 1. A multi-gradation display device for displaying an image by selecting a predetermined voltage level according to input multi-gradation display data, comprising: a display panel having a plurality of display pixels; (A positive integer of 2 or more) A first grayscale pattern generation circuit having a first grayscale pattern for obtaining one display grayscale in a frame period, and the first floor for obtaining the one display grayscale in m frame periods A second gradation pattern generating circuit having a second gradation pattern different from the gradation pattern; and the multi-gradation display data corresponding to the one display gradation based on the first gradation pattern or the second gradation pattern. And a selection control means for selecting and outputting one of the predetermined voltage levels based on the output of either the first gradation pattern generating circuit or the second gradation pattern generating circuit. Having Multi-gradation display device comprising. 2. The multi-gradation display data according to claim 1 is k
A multi-gradation display device, which is a digital signal of (k is a positive integer greater than 2) bits. 3. The multi-gradation display device according to claim 2, wherein
A multi-gradation display device comprising a gradation voltage generation circuit for supplying a voltage level lower than ^{k + 1} . 4. A display panel having a plurality of display pixels for displaying an image by selecting one voltage level of a voltage level group based on multi-gradation display data, and m (m is a positive value of 2 or more). An integer) a first gradation pattern generating circuit for generating a first gradation pattern for obtaining one display gradation, and a first gradation pattern different from the first gradation pattern for obtaining one display gradation for m frame periods. A second gradation pattern generation circuit for generating a 2-gradation pattern, and display data for converting input k (k is a positive integer larger than j) bit multi-gradation display data to j-bit multi-gradation display data Conversion means, and if the k-bit multi-gradation display data corresponds to one display gradation based on the first or second gradation pattern, the j-bit multi-gradation display data is converted to the first or second gradation pattern. Based on Multi-gradation display apparatus which is characterized in that an arithmetic processing circuit for and output. 5. The first and second gradation pattern generating circuits according to claim 4, wherein a plurality of display pixels are controlled as one control unit so that one display gradation can be obtained in consecutive m frame periods. Multi-gradation display device. 6. The multi-gradation display device according to claim 5, wherein the first and second gradation pattern generation circuits control m × m display pixels as one control unit. 7. The first gradation pattern generating circuit according to claim 6, comprising a first gradation pattern in which m tables each consisting of m × m gradation compensation data are composed of m sheets, and a second gradation pattern is provided. The multi-gradation display device, wherein the generation circuit is provided with a second gradation pattern in which a table composed of m × m gradation compensation data is composed of m sheets. 8. A multi-gradation display device according to claim 5, wherein one control unit is arranged in a substantially square arrangement. 9. The multi-gradation display device according to claim 6, wherein the first gradation pattern and the second gradation pattern are formed based on a magic circle. 10. The multi-gradation display device according to claim 5, wherein the first gradation pattern or the second gradation pattern is selected by an output from a random number generation circuit that generates a random number every m frame periods. A multi-gradation display device characterized by the above. 11. A multi-gradation display method for displaying an image in accordance with input k (k is a positive integer greater than 2) bit multi-gradation display data, wherein the k-bit multi-gradation display data is previously stored. When the prepared one voltage level is supported, the k-bit multi-gradation display data is converted into i (i is a positive integer smaller than k) -bit multi-gradation display data corresponding to the one voltage level and output. However, if the k-bit multi-gradation display data does not correspond to any of the voltage levels prepared in advance, the k-bit multi-gradation display data is set in one m (m is a positive integer of 2 or more) frame period. A first gradation pattern generating circuit for generating a first gradation pattern for obtaining a display gradation, and a second gradation pattern different from the first gradation pattern for obtaining the one display gradation in m frame periods.
A multi-gradation display method comprising converting to i-bit multi-gradation display data and outputting the i-bit multi-gradation display data based on an output of either one of a second gradation pattern generation circuit for generating a gradation pattern.