JPH07326762A - Thin film transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the off-state current of a thin film transistor of the same structure as an LDD structure, wherein processes are shortened and a reduction in cost is realized. CONSTITUTION:In a thin film transistor of a constitution, wherein a channel part 3 and source and drain regions 4 and 5 are formed in a polycrystalline semiconductor film formed on a substrate 1 and a gate electrode 7 is provided on the channel part 3 via an insulating film 6, the polycrystalline semiconductor film of the source and drain regions 4 and 5 consists of a polycrystalline semiconductor film having a crystal grain diameter smaller than that of the channel part 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly, it suppresses off current of a thin film transistor using a polycrystalline thin film semiconductor formed on a substrate having an insulating layer formed on an insulating substrate or a conductive substrate. It is a thing.

[0002]

2. Description of the Related Art With the personalization of information and the miniaturization and higher performance of computers, the present age is said to be the age of information. For downsizing of information devices for the past several years, researches on displays as man-machine interfaces, particularly liquid crystal displays (LCDs) using transistors (thin film transistors) using thin film semiconductors as switching elements have been actively conducted.

As a semiconductor film of a thin film transistor, an amorphous thin film semiconductor has been conventionally used. However, for example, since amorphous silicon has a low mobility of several cm ² / Vs or less, it has a slow response speed and is used only in the pixel portion. The drive portion is formed separately from an IC chip and then connected by wire bonding or the like. There were various problems such as having to do it.

Due to such problems, polycrystalline thin film semiconductors have been vigorously studied as a material to replace amorphous thin film semiconductors. Taking polycrystalline thin-film silicon as an example, its mobility is more than two orders of magnitude that of amorphous thin-film silicon, and it is possible to realize a high-speed response and pixel / drive unit integrated display, which is of good quality for making a lightweight and compact display. It is considered a material.

A problem with a polycrystalline thin film transistor having such advantages is that the off-current value is several orders of magnitude higher than that of an amorphous thin film transistor. It is considered that this is because a high electric field strength is applied to the interface between the semiconductor layer on the drain side and the active layer during transistor operation. As a countermeasure against this, the conventional LDD (Lightly Doped Drai) is used.
n) A structure is proposed.

A method of manufacturing a polycrystalline thin film transistor having a typical LDD structure is shown in FIGS.

A gate insulating layer 32 and a gate electrode 33 are formed on the polycrystalline semiconductor layer 31 formed on the insulating substrate 30, and then patterned (see FIG. 15).

Then, using the gate electrode 33 as a mask,
Ion implantation 34 of P (phosphorus) having a large diffusion coefficient is performed to form n ⁻ regions 35a and 35b (see FIG. 16).

Next, an insulating film 36 is deposited by the chemical vapor deposition (CVD) method (see FIG. 17), and the insulating film 36 is anisotropically etched to form sidewalls 37a and 37b on both sides of the gate electrode 33. (See FIG. 18).

Subsequently, As (arsenic) is ion-implanted 38 using the gate electrode 33 and the sidewalls 37a and 37b as a mask to form n ⁺ regions 39a and 39b (see FIG. 19).

Thereafter, annealing is performed at a high temperature of about 1000 ° C. (see FIG. 20) to activate the n ⁻ regions 35a, 35b, n ⁺ regions 39a, 39b and the gate electrode 33. Here, the n ⁻ regions 35a and 35b are referred to as LDD regions, which serve as a sloped portion of resistance between the channel portion and the drain region during transistor operation, thereby forming a structure for relaxing an electric field.

[0012]

In the method of forming the LDD structure transistor as described above, there are problems that the ion implantation is required twice and the process is complicated such as forming walls on both sides of the gate electrode. there were.

Another problem is that the types of substrates that can be used for activation at high temperatures are limited and the cost is high.

Further, it is known that the characteristic of this structure itself is that the LDD optimum condition range is narrow and that a deterioration mode peculiar to the n ⁻ region is exhibited.

By the way, when a polycrystalline thin film semiconductor is used in a transistor element, it has been clarified that there is a correlation between the polycrystalline size (crystal grain size) and element characteristics. For example, as shown in Japanese Patent Application No. 5-154128, when polycrystalline Si is manufactured by implanting impurity ions into amorphous silicon (Si) and then recrystallizing the amorphous silicon (Si) with a laser, the sheet resistance increases as the crystal grain size increases. It shows a tendency to decrease. It can be considered that this is because electron scattering at the grain boundary per unit length is reduced, and it is possible to control the electric field by using the grain boundary.

The present invention has been made to solve the above-mentioned problems, and has a structure for reducing the off current similar to the LDD structure by controlling the crystal grain sizes of the channel portion, the source and drain regions. The purpose is to manufacture and realize the reduction of the process and the cost reduction.

[0017]

According to the present invention, a channel portion and a source / drain region are formed in a polycrystalline semiconductor film formed on a substrate, and a gate electrode is provided on the channel portion via an insulating film. The polycrystalline semiconductor film in the source and drain regions is made of a polycrystalline semiconductor film having a crystal grain size smaller than that of the channel portion.

As the above-mentioned polycrystalline semiconductor film, it is possible to use a film obtained by recrystallizing an amorphous semiconductor laminated on a substrate in which irregularities are formed at the positions located in the source and drain regions.

Ions that deteriorate the crystallinity may be selectively introduced into the drain region.

It is preferable that the gate electrode extends to part of the source and drain regions.

Further, the method of manufacturing a thin film transistor according to the present invention comprises the steps of forming irregularities on the substrate surface at the portions located in the source and drain regions, forming an amorphous semiconductor film on the formed substrate, and A step of heat-treating the crystalline semiconductor to form a polycrystalline semiconductor film by recrystallization, a gate electrode is provided over the channel portion with an insulating film interposed therebetween, and the gate electrode is used as a mask to form a source into the polycrystalline semiconductor film.
And a step of forming a drain region.

The height of the concavo-convex portion may be controlled to be equal to or more than 2/3 of the thickness of the polycrystalline semiconductor film to be formed.

[0023]

According to the present invention, a high resistance region is provided between the source / drain region and the channel portion by controlling the crystal grain size of the source / drain region to be smaller than that of the channel portion. As a result, electrolytic relaxation between the channel and the drain can be achieved.

Further, by introducing ions having a higher resistance than the source region into the drain region, the electrolysis between the drain region and the channel portion is relaxed, and the off current of the transistor is further relaxed.

By extending the gate electrode to a part of the source and drain regions, a structure similar to the n ⁻ region of the LDD structure can be adopted.

Further, according to the manufacturing method of the present invention, the source,
A concavo-convex portion is selectively formed in advance on the surface of the substrate to be the drain region, and the amorphous semiconductor is recrystallized by laser or low temperature heating. At this time, the grain size in the uneven portion is smaller than that in other portions, and a part of the grain size is different from that of the conventional LDD
The role of the n ^- region in the structure will be fulfilled by the different structure. Therefore, the deterioration peculiar to the LDD structure is solved, and the ion implantation step for forming the n ⁻ region and the step for forming the side wall of the gate electrode are unnecessary. Further, by activating the n ⁺ region and the gate electrode by laser or low temperature heating, it is possible to lower the temperature and increase the throughput of the entire process, which contributes to cost reduction.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of the present invention.

Quartz glass, low-melting glass having an insulating film of SiO ₂ , SiN _x or the like deposited to a thickness of 100 nm to 1 μm, or a conductive substrate is formed on the surface of the substrate 1, where source and drain regions 4 and 5 are formed. The uneven portion 2 is formed in advance. The height (depth) of the uneven portion 2 is such that the average crystal grain size of the source and drain regions 4 and 5 after recrystallization is 1/10 or less of the average crystal grain size of the channel part 3. It is controlled according to the film thickness of the polycrystalline semiconductor film provided on the substrate 1.

FIG. 11 shows the relationship between the depth of the unevenness and the average crystal grain size of the polycrystalline semiconductor film formed thereon. In this figure, the height of the uneven portion is standardized with respect to the film thickness of the polycrystalline semiconductor film to be formed, and the case where no unevenness is provided is set to 1,
The ratio is shown. From this figure, the height (depth) of the concavo-convex portion is 2/3 or more and the average particle size is 1/1 when there is no concavity and convexity.
It is below 0 and saturated.

FIG. 12 shows the relationship between the average grain size of crystals and the resistance value. In general, LDD source and drain and LD
The resistance value of the source and the drain having no D structure is different by one digit or more. That is, the LDD structure has a resistance value larger by one digit or more. As shown in FIG. 12, when the average particle size is 1/6, the resistance value is about 5 times. Therefore, by forming the source / drain regions 4 and 5 having a grain size 1/10 or less of that of the channel portion 3, the same effect as the LDD structure can be obtained.

As described above, the predetermined uneven portion 2 is formed on the substrate 1.
Is formed, and amorphous Si (hereinafter abbreviated as a-Si) having a predetermined thickness formed by plasma CVD or the like is recrystallized by laser irradiation or the like to form a polycrystalline semiconductor film. . In this polycrystalline semiconductor film, the average crystal grain size of the source and drain regions 4 and 5 is 1/10 or less of the average crystal grain size of the channel portion 3. Then, a gate electrode 7 is provided on the channel portion 3 via the gate insulating film 6, and with the gate electrode 7 as a mask, impurities such as P (phosphorus) are ion-implanted or the like to form the source / drain regions 4 and 5. Has been introduced to. The gate electrode 7 overlaps the source and drain regions 4 and 5 by about 1/10 of the channel length, respectively.

Further, the drain region 5 may be selectively doped with ions of O (oxygen), Al (aluminum), C (carbon), etc. to have a higher resistance than the source region 4.

A protective insulating film 8 such as SiO ₂ is provided on the substrate 1 including the gate electrode 7, and the source / drain regions 4, 5 are formed through the contact holes provided in the protective insulating film 8.
And the metal electrodes 8 made of Al or the like.

Next, a method of manufacturing a thin film transistor according to the present invention will be described with reference to FIGS.

As shown in FIG. 2, quartz glass or Si
A resist 11 is applied on the insulating layer on the low melting point glass or the conductive substrate 1 on which an insulating film of O ₂ , SiN _x or the like is formed to a thickness of 100 nm to 1 μm, and the window 11a is formed by photolithography on the portions to be the source and drain regions. To form.

Next, as shown in FIG. 3, wet etching using an aqueous solution of diluted HF, buffered HF, etc.,
Alternatively, the irregularities 2 are formed by dry etching using a gas such as CH ₄ , SF ₆ , CCl ₂ F _6, or the like. At this time, as described above, the average grain size of the source and drain regions 4 and 5 after recrystallization is 1/1 of the average grain size of the channel portion 3.
Conditions are set for each film thickness so as to be 0 or less.

Then, as shown in FIG.
Is removed, and then an a-Si film is deposited in a thickness of 20 to 100 nm by using plasma CVD, low pressure CVD, a sputtering method, or the like,
An island 12 made of a-Si is formed by patterning. Further, if the a-Si film contains a large amount of hydrogen, bumping occurs during recrystallization and film roughness occurs.
Dehydrogenation is performed by a method such as low-temperature annealing at ℃ or less.

Then, as shown in FIG. 5, laser irradiation 1
3, the a-Si film is recrystallized to form a polycrystalline semiconductor film 14 having different crystal grain sizes in the source / drain regions and the channel portion. At this time, as a laser, a high energy density short pulse laser (F ₂ , ArF, KrF, XeC) is used.
1, excimer laser) can be used to shorten the processing time. In addition, the laser energy at this time is 100 mJ / cm ^{2 to} 500 mJ / cm ² , and the number of times of irradiation to one place is 1 to 100 times.

Next, the gate insulating film 6 having a film thickness of 20 to 200 nm is formed by the atmospheric pressure CVD method, the sputtering method or the like, and the a-Si film 7a for the gate electrode is formed thereon as in the method shown in FIG. The film is formed to a thickness of 50 to 150 nm by the above method.

Then, as shown in FIG. 7, patterning is performed so that the resist 15 remains on the gate portion.
The film 7a and the insulating film 6 are etched. At this time, the mask is designed so that the overlap with the gate electrode, the source, and the drain region is about 1/10 of the channel length.

Then, as shown in FIG. 8, after removing the resist, the Group 5 elements (P, A) are used with the gate electrode 7 as a mask.
s, Sb, etc.), a group III element (B, etc.) or a compound containing these is implanted as impurity ions 16 to form n- or p-type impurity ion layers 4a, 5b. Furthermore, the drain region 5 may be further selectively doped with ions of O, Al, C or the like to have a higher resistance than the source region 4.

Thereafter, as shown in FIG. 9, these elements are activated by a laser 17, and a source region 4 and a drain region 5 are activated.
And the gate electrode 7 is formed.

Next, as shown in FIG.
A protective insulating film 8 made of SiO ₂ having a thickness of 500 nm is deposited, and passivation 18 is performed with hydrogen atoms or molecules in order to suppress the leak current at the polycrystalline Si grain boundaries. Then, after forming a contact hole in the protective insulating film 8, A
By providing the metal electrode made of l, the thin film transistor of the invention shown in FIG. 1 can be obtained.

All of the above steps can be performed in a low temperature process of 600 ° C. or lower. Therefore, since a glass substrate or the like can be used as the substrate, the cost can be reduced.

Next, a second embodiment of the present invention will be described with reference to FIG.
It will be described with reference to FIGS. In the second embodiment, the film thickness of the region to be the channel portion 23 is small,
The polycrystalline semiconductor film 20 is used in which the film thickness of the portions to be the source and drain regions 24 and 25 is increased. This second embodiment, as shown in Japanese Patent Application No. 5-154128,
When a thin polycrystalline or amorphous silicon film is recrystallized using a laser, a thick polycrystalline or amorphous silicon film is recrystallized using a laser.
It utilizes the fact that the crystal grain size becomes large.

The second embodiment will be described below with reference to FIGS. 13 and 14. As shown in FIG. 13, on the insulating transparent substrate 21 made of glass, a region of the a-Si film 20 serving as a channel portion has a film thickness of 50 nm, and regions on both sides thereof serving as source / drain regions have a film thickness of 100 nm. To be formed. Then, in the vacuum atmosphere, the laser 26 is irradiated from the substrate surface side. An ArF excimer laser was used as the laser, and the substrate temperature at this time was 400 ° C. By this laser irradiation, a region having a film thickness of 50 nm, that is, a region to be the channel portion 23 becomes a polycrystalline semiconductor film having a large crystal grain size, and a region having a film thickness of 100 nm to be the source 24 region and the drain region 25 has a crystal grain size. Becomes a small polycrystalline semiconductor film.

Subsequently, as shown in FIG. 14, a gate insulating film 27 and a gate electrode 28 are formed. At this time, the gate electrode is formed in the source and drain regions so as to overlap with about 1/10 of the channel length as in the above-described embodiment. Using the gate electrode 28 as a mask, a Group 5 element (P, As, Sb, etc.), a Group 3 element (B, etc.) or a compound containing these is implanted as impurity ions 19 to form an n-type or p-type impurity ion layer. To do. Further, the drain region 25 may be further selectively doped with ions of O, Al, C or the like to have a higher resistance than the source region 24. Then, these elements are activated by laser to form a source region 24, a drain region 25 and a gate electrode 28.

Next, although not shown, as in the previous embodiment, a protective insulating film made of SiO ₂ having a film thickness of 300 to 500 nm is covered, and hydrogen atoms or hydrogen atoms are used to suppress the leak current at the polycrystalline Si grain boundaries. After performing passivation by molecules, after forming a contact hole in the protective insulating film, A
The thin film transistor of the present invention can be obtained by providing the metal electrode made of l.

[0049]

As described above, according to the present invention, the grain size of the polycrystalline semiconductor is controlled by the uneven portion of the substrate, and the electric field is relaxed at the interface between the gate portion and the source / drain by using this. LDD in a shorter time and at lower cost than conventional methods
A transistor similar to one having a structure can be manufactured.

Further, the present invention does not structurally change with time the resistance value in the n ⁻ region, which has been a problem peculiar to the LDD structure, so that high reliability can be obtained.

Further, the cost of the mortar substrate can be reduced because all the steps can be performed by a low temperature process of 600 ° C. or lower.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a process example of manufacturing the thin film transistor according to the first embodiment of the invention.

FIG. 3 is a cross-sectional view showing a process example of manufacturing the thin film transistor of the first embodiment of the invention.

FIG. 4 is a sectional view showing an example of manufacturing steps of the thin film transistor according to the first embodiment of the present invention in steps.

FIG. 5 is a cross-sectional view showing a manufacturing example of the thin film transistor according to the first embodiment of the present invention in steps.

FIG. 6 is a sectional view showing an example of manufacturing steps of the thin film transistor according to the first embodiment of the present invention in steps.

FIG. 7 is a cross-sectional view showing a manufacturing example of the thin film transistor of the first embodiment of the present invention step by step.

FIG. 8 is a cross-sectional view showing a process example of manufacturing the thin film transistor of the first embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a manufacturing example of the thin film transistor of the first embodiment of the present invention in steps.

FIG. 10 is a cross-sectional view showing a process example of manufacturing the thin film transistor according to the first embodiment of the present invention.

FIG. 11 is a diagram showing the relationship between the depth of irregularities on the substrate surface and the average crystal grain size of the polycrystalline semiconductor film formed on the surface.

FIG. 12 is a diagram showing the relationship between the average grain size of crystals and the resistance value.

FIG. 13 is a cross-sectional view showing a process example of manufacturing the thin film transistor of the second embodiment of the present invention.

FIG. 14 is a sectional view showing an example of manufacturing steps of a thin film transistor according to a second embodiment of the present invention in steps.

FIG. 15 is a cross-sectional view showing a process example of manufacturing a conventional thin film transistor having an LDD structure in process steps.

FIG. 16 is a cross-sectional view showing a process example of manufacturing a conventional LDD-structured thin film transistor.

FIG. 17 is a cross-sectional view showing a process example of manufacturing a conventional LDD-structured thin film transistor.

FIG. 18 is a cross-sectional view showing a process example of manufacturing a conventional thin film transistor having an LDD structure.

FIG. 19 is a cross-sectional view showing a process example of manufacturing a conventional thin film transistor having an LDD structure.

FIG. 20 is a cross-sectional view showing an example of manufacturing a conventional thin film transistor having an LDD structure in each step.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Concavo-convex part 3 Channel part 4 Source region 5 Drain region 6 Gate oxide film 7 Gate electrode 8 Protective insulating film

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[Procedure amendment]

[Submission date] September 7, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Title of invention

[Correction method] Change

[Correction content]

Title: Thin film transistor and method of manufacturing the same

Claims (6)

[Claims] 1. A thin film transistor having a channel portion, a source and a drain region formed in a polycrystalline semiconductor film formed on a substrate, and a gate electrode provided on the channel portion with an insulating film interposed therebetween. A thin film transistor, wherein the polycrystalline semiconductor film in the source and drain regions is made of a polycrystalline semiconductor film having a crystal grain size smaller than that of the channel region. 2. The polycrystalline semiconductor film is obtained by recrystallizing an amorphous semiconductor laminated on a substrate having concavities and convexities formed at locations located in the source and drain regions. Item 3. The thin film transistor according to Item 1. 3. The thin film transistor according to claim 1, wherein ions that deteriorate the crystallinity are selectively introduced into the drain region. 4. The thin film transistor according to claim 1, wherein the gate electrode extends to part of the source and drain regions. 5. A step of forming irregularities on the substrate surface at the portions located in the source and drain regions, a step of forming an amorphous semiconductor film on the formed substrate, a heat treatment of the amorphous semiconductor, A step of crystallizing and forming a polycrystalline semiconductor film; a step of providing a gate electrode on the channel portion with an insulating film interposed therebetween, and forming a source / drain region in the polycrystalline semiconductor film using the gate electrode as a mask. A method of manufacturing a thin film transistor comprising: 6. The method of manufacturing a thin film transistor according to claim 6, wherein the height of the irregularities is equal to or greater than 2/3 of the thickness of the polycrystalline semiconductor film to be formed.