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JPH07326750A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH07326750A
JPH07326750A JP12086594A JP12086594A JPH07326750A JP H07326750 A JPH07326750 A JP H07326750A JP 12086594 A JP12086594 A JP 12086594A JP 12086594 A JP12086594 A JP 12086594A JP H07326750 A JPH07326750 A JP H07326750A
Authority
JP
Japan
Prior art keywords
film
insulating film
region
semiconductor substrate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12086594A
Other languages
Japanese (ja)
Inventor
Mikio Wakamiya
幹夫 若宮
Yuichi Mikata
裕一 見方
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP12086594A priority Critical patent/JPH07326750A/en
Publication of JPH07326750A publication Critical patent/JPH07326750A/en
Pending legal-status Critical Current

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  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To make it possible to control the threshold voltage of a transistor without inflicting an adverse effect on the characteristics of the transistor by a method wherein an insulating film containing carbon is formed between a gate insulating film, which is formed on a substrate, and a gate electrode, the film-forming condition at the time of formation of the insulating film is changed and the concentration of the carbon being contained in the insulating film is controlled. CONSTITUTION:An oxide film 12 is formed on the surface of a semiconductor substrate 11 and a BPSG film 13 is formed on the surface of the film 12. Then, a polycrystalline silicon film 14 is formed on the surface of the film 13. A resist mask 15 is formed on the surface of the film 14 and the film 14 and the film 13 are etched in order using this mask 15 as a mask to form a gate electrode. The film-forming condition of the film 13 within this gate electrode is changed and the concentration of carbon being contained in the film 13 is controlled. Thereby, the threshold voltage of a transistor 4 can be controlled without inflicing an adverse effect on the characteristics of the transistor 4.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置とその製造方
法、特に電界効果型トランジスタとその製造方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a field effect transistor and its manufacturing method.

【0002】[0002]

【従来の技術】電界効果型トランジスタのしきい値電圧
は、素子の特性においては重要であり、このしきい値電
圧を所望の値に制御することが行われている。しきい値
電圧を決定する要因としては、ゲート絶縁膜の膜厚、ゲ
ート絶縁膜内の電荷量、半導体基板内に形成される不純
物領域の不純物の種類と濃度等があるが、ゲート酸化膜
内の電荷量は、半導体装置の製造工程中に所望の値に制
御することは困難である。また半導体基板内の不純物濃
度やゲート絶縁膜の膜厚についても、しきい値電圧以外
の特性に影響を与えるため、ある程度の値に限定されて
しまう。
2. Description of the Related Art The threshold voltage of a field effect transistor is important in the characteristics of the device, and it has been practiced to control this threshold voltage to a desired value. Factors that determine the threshold voltage include the thickness of the gate insulating film, the amount of charge in the gate insulating film, and the type and concentration of impurities in the impurity region formed in the semiconductor substrate. It is difficult to control the amount of electric charge in the desired value during the manufacturing process of the semiconductor device. Further, the impurity concentration in the semiconductor substrate and the film thickness of the gate insulating film also affect characteristics other than the threshold voltage, and are therefore limited to a certain value.

【0003】電界効果型トランジスタのしきい値電圧を
制御する方法としては、主にチャネルドープ法が用いら
れている。このチャネルドープ法は半導体基板表面のチ
ャネル領域にBやP等の不純物をイオン注入し、半導体
基板表面の不純物濃度を変化させる方法である。
As a method of controlling the threshold voltage of a field effect transistor, a channel doping method is mainly used. This channel doping method is a method in which impurities such as B and P are ion-implanted into the channel region on the surface of the semiconductor substrate to change the impurity concentration on the surface of the semiconductor substrate.

【0004】このチャネルドープ法を用い、P型シリコ
ン基板にNチャネル電界効果型トランジスタを製造する
場合における、主としてゲート電極の製造方法につい
て、以下図面を参照して説明する。まず図5(a)に示
すように半導体基板111表面上に酸化膜112を形成
する。次にチャネル形成予定領域上以外の酸化膜112
表面上にレジストマスク113を形成し、これをマスク
として半導体基板111内にBを所定の加速エネルギー
とドーズ量によりイオン注入114し、チャネル領域1
15の不純物濃度を制御する。この工程において電界効
果型トランジスタのしきい値電圧は決定される。
A method of manufacturing a gate electrode in the case of manufacturing an N-channel field effect transistor on a P-type silicon substrate using this channel doping method will be described below with reference to the drawings. First, as shown in FIG. 5A, an oxide film 112 is formed on the surface of the semiconductor substrate 111. Next, the oxide film 112 other than on the channel formation planned region
A resist mask 113 is formed on the surface, and using this as a mask, B is ion-implanted 114 into the semiconductor substrate 111 with a predetermined acceleration energy and a predetermined dose amount, and the channel region 1 is formed.
The impurity concentration of 15 is controlled. In this step, the threshold voltage of the field effect transistor is determined.

【0005】続いて図5(b)に示すように、酸化膜1
12表面上に多結晶シリコン膜を形成し、これをパター
ニングしゲート電極116を形成する。このゲート電極
116をマスクとして半導体基板111内にPをイオン
注入し、N型拡散領域を形成し、一方をソース領域11
7、他方をドレイン領域118とする。以上の工程によ
り、チャネルドープ法を用いた電界効果型トランジスタ
のゲート電極の製造工程は終了する。
Subsequently, as shown in FIG. 5B, the oxide film 1
A polycrystalline silicon film is formed on the surface 12 and patterned to form a gate electrode 116. Using this gate electrode 116 as a mask, P ions are implanted into the semiconductor substrate 111 to form an N-type diffusion region, one of which is the source region 11
7 and the other is the drain region 118. Through the above steps, the manufacturing process of the gate electrode of the field effect transistor using the channel doping method is completed.

【0006】[0006]

【発明が解決しようとする課題】上記に示した電界効果
型トランジスタのチャネルドープ法においては、以下に
示す問題点がある。まず第一の問題点として、BやP等
の不純物原子をイオンとして高エネルギーで加速し、こ
れを直接半導体基板内に打ち込むため、この打ち込まれ
たイオンによって半導体基板を構成するSiの配列が乱
され、結晶欠陥が発生する。この結晶欠陥はリーク電流
を生じさせる原因となる。
The channel doping method for the field effect transistor described above has the following problems. The first problem is that impurity atoms such as B and P are accelerated as ions with high energy and are directly implanted into the semiconductor substrate, so that the implanted ions disturb the arrangement of Si constituting the semiconductor substrate. Then, a crystal defect is generated. This crystal defect causes a leak current.

【0007】また第二の問題点として、イオン注入によ
り注入した不純物イオンを半導体基板内で活性化させる
ために、摂氏1000度以上の熱処理を行うが、素子の
微細化と高集積化に伴って例えばソース、ドレイン間の
間隔が狭まり、またこれら不純物領域が形成される領域
も半導体基板の浅い領域であり、高温の熱処理が行われ
ると不純物の再拡散が発生し、素子内或いは半導体基板
上に形成されている他の素子内や素子間においても、接
合リーク電流を発生させる原因となる。
A second problem is that heat treatment at 1000 ° C. or higher is performed in order to activate the impurity ions implanted by ion implantation in the semiconductor substrate, but with the miniaturization and high integration of the device. For example, the distance between the source and drain is narrowed, and the region where these impurity regions are formed is also a shallow region of the semiconductor substrate. When high-temperature heat treatment is performed, re-diffusion of impurities occurs, and This may cause a junction leak current in other formed elements or between elements.

【0008】上記のようにしきい値電圧を制御するため
に行われる、チャネルドープ法による従来の半導体装置
の製造方法では、結晶欠陥や不純物の再拡散等が生じ、
最終的には製品として素子に求められる特性が、得られ
なくなる場合があるという問題点がある。よって本発明
においては、トランジスタの特性に悪影響を与えること
なく、しきい値電圧を制御することが可能な半導体装置
とその製造方法を提供することを目的とする。
In the conventional method of manufacturing a semiconductor device by the channel doping method, which is performed to control the threshold voltage as described above, crystal defects, re-diffusion of impurities, etc. occur,
Finally, there is a problem in that the characteristics required for the device as a product may not be obtained in some cases. Therefore, it is an object of the present invention to provide a semiconductor device capable of controlling the threshold voltage without adversely affecting the characteristics of the transistor and a manufacturing method thereof.

【0009】[0009]

【課題を解決するための手段】本発明においては、電界
効果型トランジスタのしきい値電圧の制御を行うため
に、半導体基板上に形成するゲート絶縁膜とゲート電極
との間に、炭素(以下Cと記す。)を含有する絶縁膜を
成膜する。絶縁膜成膜時の成膜条件を変化させ、膜内に
含有されるCの濃度を制御する。このCは電荷として機
能させることができ、絶縁膜内に含有されるCの濃度を
制御することにより、絶縁膜が有する電荷量を変化させ
る。この電荷の働きにより、電界効果型トランジスタの
しきい値電圧を所望の値に制御する。
According to the present invention, in order to control the threshold voltage of a field effect transistor, carbon (hereinafter referred to as a “gate”) is formed between a gate insulating film formed on a semiconductor substrate and a gate electrode. An insulating film containing C) is formed. The concentration of C contained in the film is controlled by changing the film forming conditions when forming the insulating film. This C can function as an electric charge, and the amount of electric charge of the insulating film is changed by controlling the concentration of C contained in the insulating film. The action of this charge controls the threshold voltage of the field effect transistor to a desired value.

【0010】[0010]

【作用】本発明によれば、半導体基板内に結晶欠陥や不
純物の再拡散を生じさせず、素子の特性に悪影響を与え
ることなく、電界効果型トランジスタのしきい値電圧を
制御することが可能となる。
According to the present invention, it is possible to control the threshold voltage of a field effect transistor without causing crystal defects or re-diffusion of impurities in the semiconductor substrate and adversely affecting the characteristics of the device. Becomes

【0011】[0011]

【実施例】本発明の実施例について以下図面を参照して
説明する。本実施例においては、その代表的な例とし
て、大規模集積回路を構成する電界効果型トランジスタ
の製造方法について説明する。
Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, as a typical example thereof, a method of manufacturing a field effect transistor which constitutes a large scale integrated circuit will be described.

【0012】図1(a)に示すように、メモリセル部
(図示せず)が既に形成されている半導体基板11表面
上に、熱酸化により膜厚100オングストロームの酸化
膜12を形成する。次に酸化膜表面上に膜厚100オン
グストロームのBPSG(Boron doped Phospho Silica
te Glass)膜13を形成する。次にBPSG膜13表面
上に、LPCVD法により膜厚4000オングストロー
ムの多結晶シリコン膜14を形成する。
As shown in FIG. 1A, an oxide film 12 having a thickness of 100 angstrom is formed by thermal oxidation on the surface of the semiconductor substrate 11 on which the memory cell portion (not shown) is already formed. Next, BPSG (Boron doped Phospho Silica) having a film thickness of 100 angstrom is formed on the surface of the oxide film.
te Glass) film 13 is formed. Next, a polycrystalline silicon film 14 having a film thickness of 4000 angstrom is formed on the surface of the BPSG film 13 by the LPCVD method.

【0013】BPSG膜13はLPCVD(Low Pressu
re Chemical Vapour Deposition )法により成膜し、摂
氏600度程度、約1torrの減圧状態にある装置内
に、TEOS(テトラエトキシシラン)、PH3 (ホス
フィン)、TMB(トリメチルボレート)、酸素を導入
することにより行う。導入ガスの流量比等の条件を変え
ることにより、BPSG膜内に導入するB、Pのドーピ
ング量を所望の値に制御することができる。
The BPSG film 13 is formed by LPCVD (Low Pressu
A film is formed by a re chemical vapor deposition (deposition) method, and TEOS (tetraethoxysilane), PH3 (phosphine), TMB (trimethylborate), and oxygen are introduced into an apparatus under a reduced pressure of about 1 degree to 600 degrees Celsius. By. The doping amount of B and P introduced into the BPSG film can be controlled to a desired value by changing the conditions such as the flow rate ratio of the introduced gas.

【0014】但しPの導入量を大きくしすぎると、BP
SG膜に吸湿の問題が生じるためB、Pのドーパントの
量は導入ガスの総重量に対し、Pが7%、Bが4%程度
が望ましい。
However, if the amount of P introduced is too large, BP
Since there is a problem of moisture absorption in the SG film, it is desirable that the amounts of B and P dopants are about 7% for P and 4% for B with respect to the total weight of the introduced gas.

【0015】形成されたBPSG膜13の膜内には、T
EOSの成分である有機物が含まれており、BPSG膜
13中にはCが含有される。Cは一定の電荷として機能
するため、このCによる電荷はNチャネルの電界効果型
トランジスタにおいては、しきい値電圧を低下させる効
果があり、BPSG膜内に含有するCの濃度を制御する
ことにより、電界効果型トランジスタのしきい値電圧を
制御することが可能となる。
In the film of the formed BPSG film 13, T
An organic substance, which is a component of EOS, is contained, and C is contained in the BPSG film 13. Since C functions as a constant electric charge, the electric charge by the C has an effect of lowering the threshold voltage in the N-channel field effect transistor. By controlling the concentration of C contained in the BPSG film, It is possible to control the threshold voltage of the field effect transistor.

【0016】ここで図2にBPSG膜の成膜温度と、B
PSG膜13内に含有されるCの濃度の関係を示す。こ
の際の酸素分圧は0.17torrで一定であり、導入
ガスのそれぞれの流量は、TEOS100cc/se
c、PH3 180cc/sec、TMB12cc/se
c、酸素100cc/secとした。
FIG. 2 shows the deposition temperature of the BPSG film and B
The relationship between the concentrations of C contained in the PSG film 13 is shown. The oxygen partial pressure at this time was constant at 0.17 torr, and the flow rate of each introduced gas was TEOS 100 cc / se.
c, PH3 180cc / sec, TMB12cc / se
c and oxygen were 100 cc / sec.

【0017】また図3にはBPSG膜の成膜時の酸素分
圧と、BPSG膜13内に含有されるCの濃度の関係を
示す。酸素分圧は導入ガスに対する値であり、この際の
TEOS等酸素を除く導入ガスの流量は、図2の場合と
同様である。また成膜温度は摂氏600度で一定であ
る。
FIG. 3 shows the relationship between the oxygen partial pressure during the formation of the BPSG film and the concentration of C contained in the BPSG film 13. The oxygen partial pressure is a value for the introduced gas, and the flow rate of the introduced gas excluding oxygen such as TEOS at this time is the same as that in the case of FIG. The film forming temperature is constant at 600 degrees Celsius.

【0018】これらによれば成膜温度を高くするに従っ
て、BPSG膜内に含有されるCの濃度は減少してゆ
き、酸素の流量を多くすることにより、BPSG膜内に
含有されるCの濃度は減少してゆくことが分かる。よっ
てBPSG膜内に含有されるCの濃度はBPSG膜の成
膜条件、例えば成膜温度や導入する酸素の分圧比により
制御することができる。
According to these, the concentration of C contained in the BPSG film decreases as the film forming temperature increases, and the concentration of C contained in the BPSG film increases by increasing the flow rate of oxygen. It can be seen that is decreasing. Therefore, the concentration of C contained in the BPSG film can be controlled by the film forming conditions of the BPSG film, for example, the film forming temperature and the partial pressure ratio of oxygen to be introduced.

【0019】図4にBPSG膜内に含有するCの濃度と
しきい値電圧の関係を示す。これによればCの濃度を高
くすることにより、しきい値電圧が低下することが分か
る。よって図2、図3をもとにBPSG膜の成膜条件を
変化させ、BPSG膜内に含有されるCの濃度を制御す
ることにより、しきい値電圧を所望の値に制御すること
が可能となる。
FIG. 4 shows the relationship between the concentration of C contained in the BPSG film and the threshold voltage. According to this, it is understood that the threshold voltage is lowered by increasing the concentration of C. Therefore, the threshold voltage can be controlled to a desired value by changing the film forming conditions of the BPSG film based on FIGS. 2 and 3 and controlling the concentration of C contained in the BPSG film. Becomes

【0020】続いて図1(b)に示すように、多結晶シ
リコン膜14表面上にレジストマスク15を形成し、こ
れをマスクとして多結晶シリコン膜14、BPSG膜1
3を順にエッチングすることによりゲート電極を形成す
る。
Subsequently, as shown in FIG. 1B, a resist mask 15 is formed on the surface of the polycrystalline silicon film 14, and the polycrystalline silicon film 14 and the BPSG film 1 are used as a mask.
A gate electrode is formed by etching 3 sequentially.

【0021】続いて図1(c)に示すように、ゲート電
極をマスクとして半導体基板11内の所定の領域にPを
イオン注入し、熱処理を行うことによりソース領域16
及びドレイン領域17を形成する。以上の工程により大
規模集積回路内に電界効果型トランジスタが製造され
る。この後、先の工程において形成されているメモリセ
ル部との接続等が行われ、大規模集積回路の製造が完了
する。以上の工程により、従来チャネルドープ法を行う
ことにより生じていた結晶欠陥や不純物の再拡散を生じ
させることなく、電界効果型トランジスタのしきい値電
圧を、所望の値に制御することが可能となる。
Subsequently, as shown in FIG. 1C, P is ion-implanted into a predetermined region in the semiconductor substrate 11 by using the gate electrode as a mask, and a heat treatment is performed to perform the heat treatment.
And the drain region 17 is formed. Through the above steps, a field effect transistor is manufactured in a large scale integrated circuit. After that, connection with the memory cell portion formed in the previous step is performed, and the manufacturing of the large-scale integrated circuit is completed. Through the above steps, the threshold voltage of the field-effect transistor can be controlled to a desired value without causing the crystal defects and the re-diffusion of impurities, which have been caused by the conventional channel doping method. Become.

【0022】上記実施例においてはBPSG膜をLPC
VD法により形成したが、これは常圧のCVD法により
形成することもできる。その際成膜される膜の均一性は
LPCVD法によるものと比べ劣るが、膜の成長速度を
高めることができる。また形成する膜はPSG(Phosph
o Silicate Glass)膜によっても、上記同様の効果が期
待できる。よってBPSG膜とPSG膜を積層に形成す
ることもできる。
In the above embodiment, the BPSG film was used as the LPC.
Although it is formed by the VD method, it can also be formed by the atmospheric pressure CVD method. At that time, the uniformity of the film formed is inferior to that obtained by the LPCVD method, but the growth rate of the film can be increased. The formed film is PSG (Phosph
The same effect as above can be expected with a Silicate Glass) film. Therefore, the BPSG film and the PSG film can be formed in a stack.

【0023】また上記実施例においては大規模集積回路
における電界効果型トランジスタの製造方法について示
したが、本発明は電界効果型トランジスタ全般に関して
適用できるものであり、例えばパワーMOS−FET
(Metal Oxide Semiconductor-FET )等のしきい値電圧
の制御についても用いることができる。
Further, although the method of manufacturing the field effect transistor in the large scale integrated circuit is shown in the above embodiment, the present invention can be applied to all field effect transistors, for example, a power MOS-FET.
(Metal Oxide Semiconductor-FET) and the like can also be used for controlling the threshold voltage.

【0024】[0024]

【発明の効果】本発明によれば、半導体基板内に結晶欠
陥や不純物の再拡散を生じさせず、素子の特性に悪影響
を与えることなく、電界効果型トランジスタのしきい値
電圧を制御することが可能となる。
According to the present invention, it is possible to control the threshold voltage of a field effect transistor without causing crystal defects or re-diffusion of impurities in the semiconductor substrate and adversely affecting the characteristics of the device. Is possible.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例の製造工程を説明する断面図。FIG. 1 is a sectional view illustrating a manufacturing process according to an embodiment of the present invention.

【図2】BPSG膜の成膜条件とCの濃度の関係図。FIG. 2 is a diagram showing the relationship between the film formation conditions for a BPSG film and the C concentration.

【図3】BPSG膜の成膜条件とCの濃度の関係図。FIG. 3 is a diagram showing the relationship between the film forming conditions for the BPSG film and the C concentration.

【図4】Cの濃度としきい値電圧の関係図。FIG. 4 is a relationship diagram between the concentration of C and the threshold voltage.

【図5】従来の製造工程を説明する断面図。FIG. 5 is a cross-sectional view illustrating a conventional manufacturing process.

【符号の説明】[Explanation of symbols]

11、111 半導体基板 12、112 酸化膜 13 BPSG膜 14 多結晶シリコン膜 15、113 レジストマスク 16、117 ソース領域 17、118 ドレイン領域 114 Bのイオン注入 115 チャネル領域 116 ゲート電極 11, 111 Semiconductor substrate 12, 112 Oxide film 13 BPSG film 14 Polycrystalline silicon film 15, 113 Resist mask 16, 117 Source region 17, 118 Drain region 114 B ion implantation 115 Channel region 116 Gate electrode

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板表面上に形成された第一絶縁
膜と、 この絶縁膜表面上の所定の領域に形成された有機物を含
有する第二絶縁膜と、 この第二絶縁膜表面上に形成された導電膜と、 前記第二絶縁膜直下の領域に隣接する前記半導体基板内
に対向して形成されたソース領域及びドレイン領域とを
有することを特徴とする半導体装置。
1. A first insulating film formed on the surface of a semiconductor substrate, a second insulating film containing an organic substance formed in a predetermined region on the surface of the insulating film, and a second insulating film on the surface of the second insulating film. A semiconductor device comprising: a formed conductive film; and a source region and a drain region formed in the semiconductor substrate adjacent to a region immediately below the second insulating film so as to face each other.
【請求項2】 半導体基板内の第一領域と、 前記第一領域を介して前記半導体基板内に離間して形成
された第二領域及び第三領域と、 少なくとも前記第一領域上の前記半導体基板表面上に形
成された第一絶縁膜と、 この第一絶縁膜上に形成され
所定の電荷量を備えた第二絶縁膜と、 この第二絶縁膜表面上に形成された導電膜とを有するこ
とを特徴とする半導体装置。
2. A first region in a semiconductor substrate, a second region and a third region which are formed in the semiconductor substrate with the first region separated from each other, and at least the semiconductor on the first region. A first insulating film formed on the surface of the substrate, a second insulating film having a predetermined charge amount formed on the first insulating film, and a conductive film formed on the surface of the second insulating film. A semiconductor device having.
【請求項3】 請求項1または2記載の半導体装置にお
いて、 前記第二絶縁膜はBPSG(Boron doped Phospho Sili
cate Glass)膜またはPSG(Phospho Silicate Glas
s)膜または前記BPSG膜と前記PSG膜により形成
されていることを特徴とする半導体装置。
3. The semiconductor device according to claim 1, wherein the second insulating film is BPSG (Boron doped Phospho Sili).
cate glass) film or PSG (Phospho Silicate Glas)
s) A semiconductor device comprising a film or the BPSG film and the PSG film.
【請求項4】 半導体基板表面上に第一絶縁膜を形成す
る工程と、 前記絶縁膜表面上に有機物を含有する第二絶縁膜を形成
する工程と、 前記第二絶縁膜表面上に導電膜を形成する工程と、 前記第二絶縁膜と前記導電膜を所定の電極形状に加工す
る工程と、 電極形状に加工された前記第二絶縁膜と前記導電膜をマ
スクとしてイオン注入により前記半導体基板内に不純物
領域を形成する工程とを具備することを特徴とする半導
体装置の製造方法。
4. A step of forming a first insulating film on the surface of a semiconductor substrate, a step of forming a second insulating film containing an organic substance on the surface of the insulating film, and a conductive film on the surface of the second insulating film. And a step of processing the second insulating film and the conductive film into a predetermined electrode shape, and the semiconductor substrate by ion implantation using the second insulating film and the conductive film processed into the electrode shape as a mask. And a step of forming an impurity region therein.
【請求項5】 請求項4記載の半導体装置の製造方法に
おいて、 前記第二絶縁膜はBPSG(Boron doped Phospho Sili
cate Glass)膜またはPSG(Phospho Silicate Glas
s)膜または前記BPSG膜と前記PSG膜であること
を特徴とする半導体装置の製造方法。
5. The method of manufacturing a semiconductor device according to claim 4, wherein the second insulating film is BPSG (Boron doped Phospho Sili).
cate glass) film or PSG (Phospho Silicate Glas)
s) A film or a method of manufacturing a semiconductor device, which is the BPSG film and the PSG film.
【請求項6】 半導体基板内のチャネル領域と、 前記チャネル領域を介して前記半導体基板内に離間して
形成されたソース領域及びドレイン領域と、 前記チャネル領域上の前記半導体基板表面上に形成され
たゲート絶縁膜とを有する電界効果型トランジスタを具
備した半導体装置において、 前記ゲート絶縁膜上に、含有する炭素の濃度により前記
電界効果型トランジスタのしきい値電圧を制御する膜を
具備することを特徴とする半導体装置。
6. A channel region in a semiconductor substrate, a source region and a drain region spaced apart in the semiconductor substrate via the channel region, and a channel region formed on the surface of the semiconductor substrate. In a semiconductor device having a field effect transistor having a gate insulating film, a film for controlling a threshold voltage of the field effect transistor is provided on the gate insulating film according to a concentration of carbon contained therein. Characteristic semiconductor device.
JP12086594A 1994-06-02 1994-06-02 Semiconductor device and manufacture thereof Pending JPH07326750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12086594A JPH07326750A (en) 1994-06-02 1994-06-02 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12086594A JPH07326750A (en) 1994-06-02 1994-06-02 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH07326750A true JPH07326750A (en) 1995-12-12

Family

ID=14796873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12086594A Pending JPH07326750A (en) 1994-06-02 1994-06-02 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH07326750A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6864561B2 (en) 1996-02-02 2005-03-08 Micron Technology, Inc. Method and apparatus for reducing fixed charge in semiconductor device layers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6864561B2 (en) 1996-02-02 2005-03-08 Micron Technology, Inc. Method and apparatus for reducing fixed charge in semiconductor device layers

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