JPH0732396B2 - Data transfer system and timing control device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a data transfer system suitable for use in processing a digital audio signal.

“Prior Art” Conventionally, as a data transfer method between digital devices, there has been a data transfer method using a serial data bus group and a matrix switch. This method, as shown in FIG.
Serial data bus group A _{0 to} An and serial data bus group
A matrix switch 60 is provided between B _{0 and} Bn to appropriately set the connection relationship between both buses.

In addition, a data transfer method using a so-called VME bus is adopted in general-purpose computers and the like. This is an asynchronous bus that directly connects the boards together and is configured to wait until the sender acknowledges that the receiver has received the data,
This makes it possible to transfer data having various data lengths.

[Problems to be Solved by the Invention] By the way, each of the above-mentioned methods has a problem to be solved.

First, in the data transfer method using the serial data bus group and the matrix switch, there is a drawback that high-speed transmission is difficult due to serial data transmission. Further, if the number of data buses is increased, the matrix switch There is also a drawback that the structure of 60 becomes complicated and expensive.

On the other hand, in the data transfer method using the VME bus, the timing of the data transfer is uncertain, so if it is used to transfer a real-time signal such as a digital audio signal, the transferred data will always be transferred in real time. It was inconvenient because it needed to be corrected.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a data transfer system and a timing control device that are both inexpensive and that enable both serial and high-speed data transmission.

"Means for Solving the Problems" In order to solve the above problems, in the invention described in the first aspect of the invention, as shown in FIG.
Of the address information, a transmitting device 103 for transmitting the data, a receiving device 104 for receiving the data when the second address information is supplied, and two receiving sets of the address information. A main control device 101 that generates an address information sequence including the first and second address information, and that forms the address information sequence when the main control device 101 supplies the address information sequence. The timing control device 102 supplies the address information to the transmission device 103 and the reception device 104 in a predetermined order and at a predetermined timing in units of one set.

Further, in the invention described in claim 2, as illustrated in FIG. 1B, the address information generating means 203 for generating address information circulating in a predetermined cycle, and the address information are When supplied, the first storage device 201 which outputs the contents of the address specified by the address information
When the address information is supplied, the second storage device 202 that outputs the content of the address specified by the address information, and the address information supplied from the address information inventing means are supplied to the second storage device for each cycle. Switching means 204 for alternately supplying to the first and second storage devices 201 and 202, and data updating means for updating the contents of the first or second storage devices 201 and 202 on the side to which the address information is not supplied. 205
And are provided.

[Operation] In the invention according to the first aspect of the invention, the set of address information supplied from the main control device 101 is output from the timing control device 102 in a predetermined order and at a predetermined timing. Therefore, when the set of the first and second address information is included in the address information sequence, the data transfer from the transmitting device 103 to the receiving device 104 is executed at the timing when this set of address information is output.

Therefore, if the address information sequence is configured such that the set of the first and second address information is repeatedly output from the timing control device 102 at a constant cycle, the transmission device
Data transfer from 103 to the receiving device 104 is periodically executed.

Further, if the address information sequence is configured so that the set of the first and second address information is frequently output, a large amount of data can be transferred from the transmitting device 103 to the receiving device 104 in a short time.

As described above, according to the present invention, the data transfer timing and the data transmission amount can be arbitrarily set by appropriately configuring the address information sequence generated by the main control device 101.

In the invention according to claim 2, the address information generated by the address information generating means 203 is transferred to the first and second storage devices 201 and 202 via the switching means 204.
Are supplied alternately. Then, the storage device on the side to which the address information is supplied outputs data according to the address information. On the other hand, the content of the other storage device is updated by the data updating means 205.

Thus, in the present invention, the address information generating means
203 controls the timing of data output from each of the storage devices 201 and 202, and the data updating means 205 sets the data content. Then, since both of them control different storage devices in an instant, there is no conflict of control between them.

[Examples] Next, examples of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing the electrical configuration of the musical sound synthesis system of the first embodiment of the present invention.

In the figure, 5, 6, 8 and 9 are A / D modules,
A waveform storage module, a D / A module, and a DSP module, which are connected to the control bus 1, the data bus 2, and the address bus 3. A predetermined address number is assigned to each of these modules. When the address number appears on the address bus 3, the corresponding module inputs / outputs a digital signal to / from the data bus 2. Reference numeral 11 denotes a main control unit, which is provided with a central processing unit, a storage unit and the like (not shown), and gives various instructions to the above-mentioned modules. Also, the main controller
The reference numeral 11 supplies an address signal to the address bus 3 via the bus controller 10, thereby designating a module for transmitting data and a module for receiving the data. Reference numeral 12 is a keyboard for inputting performance information to the main controller 11. An operation panel 13 inputs various control signals to the main controller 11. The bus controller 10 generates a timing signal for the input / output operation of each module, and supplies the address signal supplied from the main controller 11 to the address bus 3 in synchronization with the timing signal.

Next, the function of each module will be described. A / D module 5
When an audio signal is input from the microphone 4, the audio signal is converted into a digital signal and output to the data bus 2. Further, the waveform storage module 6 stores musical instrument waveforms of various musical instruments (for example, piano, harpsichord, etc.) and outputs a musical tone signal based on the performance information supplied from the main controller 11.
The D / A module 8 also converts a digital audio signal input via the data bus 2 into an analog audio signal,
This is output to the sound system 7. The acoustic system 7
The supplied analog audio signal is amplified and sounded from the speaker 7a. Further, the DSP module 9 functions as a mixer, an equalizer, or an effector by performing waveform synthesis and waveform processing by digital calculation.

Next, details of the bus controller 10 will be described with reference to FIG. In the figure, reference numerals 21 and 22 denote RAMs (read / write storage devices), which have address terminals ADD and data terminals D, respectively.
ATA, select terminal ▲ ▼, write terminal ▲ ▼
And. These RAMs have their select terminals ▲
When the "0" level signal is supplied to ▼ and the "1" level signal is supplied to the write terminal ▲ ▼, the content of the adrel designated by the address signal is output to the data terminal DATA. Also, when a "0" level signal is supplied to both the select terminal ▲ ▼ and the write terminal ▲ ▼,
The data content supplied to the data terminal DATA is written at the address designated by the address signal. If the signals supplied to the select terminal ▲ ▼ and the write terminal ▲ ▼ are in states other than the above, the data terminal DATA is in a high impedance state, and data cannot be input / output.

Reference numerals 23 and 24 denote switching devices, which control the switches provided therein based on the control signal S ₁ from the RAM switching control circuit 25 to set the connection destinations of the terminals of the RAMs 21 and 22. For example, in the illustrated state, each terminal of the RAM 21 is connected to the main control device 11 via each switch. This allows
Main controller 11 can freely read from and write to RAM 21. On the other hand, since the select terminal ▲ ▼ of the RAM22 is always supplied with the signal of "0" level and the write terminal ▲ ▼ is always supplied with the signal of "1" level, the operation of the RAM22 is limited to the read operation. . Also RAM
The address terminal ADD of 22 is connected to the output terminal of the counter 26, and the data terminal DATA is connected to the address bus 3 of the tone synthesis system (see FIG. 2) via the tristate buffer 30. As a result, the output signal S ₂ of the counter 26
The content of the address designated by is read from the RAM 22 and this content is supplied to the address bus 3.

On the other hand, when the switches inside the switches 23 and 24 are switched to the opposite side to the one shown in the figure, the state opposite to that described above is obtained.
That is, the RAM 22 becomes readable and writable by the main controller 11, and the contents of the RAM 21 are stored in the counter 26.
Is supplied to the address 3 in accordance with the output signal of.

Reference numeral 27 is a timing generation circuit, which generates a control signal S _C for each time slot from the clock signal and supplies this to the control bus 1 via the buffer 28. Here, the time slot is a unit of time for data transmission in the musical sound synthesis system of FIG. 2, and each mondule 5, 6, 8, 9 inputs / outputs each time slot according to the control signal S _C. (Details will be described later). Further, the timing generation circuit 27 outputs a clock signal S _{3 in} units of time slots, which is a counter.
Supplied to 26.

The counter 26 repeatedly counts the clock signal S ₃ within a range of “0” to a predetermined number “N”, and outputs the counting result as a signal S ₂ . The output signal S ₂ is supplied to the address terminal ADD of the RAM 21 or RAM 22 as described above. When the count result of the counter 26 changes from "N" to "0",
The sample timing signal S ₄ is output. Here, the sample is a unit of time for data transmission, and one sample is equal to “N + 1” time slots. One sample is also equal to the sampling period of each digital audio signal (details will be described later). Then, the sample timing signal S ₄ becomes a signal indicating the delimiter of each sample. The sample timing signal S ₄ is supplied to the control bus 1 via the buffer circuit 29 and also to the RAM switching control circuit 25.

When the sample timing signal S ₄ is supplied, the RAM switching control circuit 25 outputs a control signal S ₁ that reverses the connection state of the switching devices 23 and 24. Therefore, RAM21,22 is 1
Each sample is alternately connected to the main controller 11 and the data content thereof is updated. Further, the RAM on the side not connected to the main controller 11 is, in accordance with the output signal S ₂ of the counter 26,
The contents are sequentially supplied to the address bus 3. RAM
The switching control circuit 25 monitors the input / output operation of the main controller 11 and the RAMs 21 and 22, and during the input / output operation, the control signal S ₁
Is configured not to output.

Next, the overall operation of this embodiment will be described.

First, in FIG. 3, the main controller 11 stores in the RAM 21 the data corresponding to the first sample (that is, the data corresponding to the 0th to Nth time slots in the first sample).
Write in. This data specifies the module that transmits the data and the module that receives the data in each time slot. Meanwhile, the counter 26
Counts the clock signal S ₃ , and outputs the sample timing signal S ₄ when the count result changes from “N” to “0”. As a result, the RAM switching control circuit 25 causes the switching unit 2
Switch the connection status of 3 and 24 in the opposite direction to the figure.

Next, the contents of the RAM 21 are sequentially read according to the counting result of the counter 26 and supplied to the address bus 3 via the tristate buffer 30. On the other hand, in the RAM 22, the main controller 11
From, the data corresponding to the second sample is written. Then, when the reading of the data from the RAM 21 is completed, the connection state of the switches 23 and 24 is switched in the direction shown in the figure.

After that, similarly, according to the output signal S ₂ of the counter 26, RA
The content of one of M21 and M22 is read out, and the address bus 3
Is supplied to. Data corresponding to the next sample is written to the other RAM by the main control unit 11, and this data is switched by the switching devices 23 and 24 and the adrel bus 3 is sent.
Is supplied to.

The signals supplied to the address bus 3 are constantly monitored by the modules 5, 6, 8 and 9 in FIG. Then, each of the modules 5, 6, 8 and 9 performs the corresponding operation when the module is designated as the input side or the output side. The details will be described with reference to FIG. Note that FIG. 5 is an operation explanatory diagram of the present embodiment.

In FIG. 5, S _A is a signal supplied to the address bus 3 and includes a transmission address signal S _AS and a reception address signal S _AR . S _D is a signal supplied to the data bus 2. These signals are updated every time slot.
A module designated in a time slot having a sample of the transmission address signal S _AS is a transmission module 41. In the example of FIG. 2, the transmission module 41 is A /
It is either the D module 5, the waveform storage module 6, or the DSP module 9. Further, a module designated by the reception address signal S _AR in the same time slot is set as a reception module 42. The receiving module 42 is the second
In the example shown, it is either the D / A module 8, the waveform storage module 6, or the DSP module 9.

The receiving module 41 receives the my address (the address assigned to the transmitting module 41) and the sending address signal S.
_When a match with _AS is detected, digitized tone data is supplied to the data bus 2. Meanwhile, the receiving module 42
Detects the match between the my address and the received address signal S _AR , the data is read from the data bus 2. In this way, the transmission module and the reception module are set for each time slot, and data is transferred between these modules. That is, it is possible to perform a large number of data transmissions in which various transmission and reception modules are designated within one sample period.

Here, if the time slot number for transferring the data from the transmitting module 41 to the receiving module 42 is fixed (in the example of FIG. 5, the fourth time slot in each sample), the interval at which the data is transferred Is equal to 1 sample. Therefore, when the data bus to be transferred is a digital audio signal, if the sampling period of the digital audio signal is set to the same time as one sample, data can be transmitted in synchronization with the sampling period. The receiving module 42 does not need to perform time correction or the like, for example.

On the other hand, when transmitting a large amount of data from the transmitting module 41 to the receiving module 42 in a short time, a plurality of time slots in one sample may be used for transmission. Needless to say, such a change of the transmission timing or the transmission capacity can be easily realized by rewriting the contents of the RAMs 21 and 22 by the main controller 11.

As described above, in this embodiment, the transmitting module, the receiving module, the transmission timing and the transmission capacity can be freely set even during the operation of the musical sound synthesizing system.

The present invention is not limited to the above embodiment,
It goes without saying that various applications are possible. For example, the present invention can be applied to the audio system shown in FIG. In the figure, reference numeral 46 denotes a disk control module, through which data can be input / output to / from the hard disk 45. Further, with respect to the digital audio device 48 having an input / output interface different from that of the present audio system, input / output is enabled by inserting the digital I / O module 47. Further, the present system is provided with constituent elements (corresponding to the same reference numerals as those in FIG. 2) corresponding to the respective portions in FIG. Then, these components enable recording, processing, reproduction and the like of audio signals.

[Advantages of the Invention] As described above, according to the present invention, it is possible to provide a data transfer system and a timing control device that are inexpensive and that enable both serial and high-speed data transmission.

[Brief description of drawings]

1 (a) and 1 (b) are block diagrams illustrating the configuration of the present invention, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is a block diagram of the main part of FIG. FIG. 4 is a block diagram of a modified example of the embodiment, FIG. 5 is an operation explanatory view of the embodiment, and FIG. 6 is an operation explanatory view of a matrix circuit according to a conventional technique. 5 ... A / D module (transmission device), 8 ... D / A module (reception device), 10 ... Bus controller (timing control device), 11 ... Main control device (data updating means), 21
... Read / write storage device (first storage device), 22 ...
... Read / write storage device (second storage device), 23, 24
...... Switcher (switching means), 25 ...... RAM switching control circuit (switching means), 26 ...... Counter (address information generating means),
27 …… Timing generator (address information generator),
101 ... Main control device, 102 ... Timing control device, 103
...... Sending device, 104 ...... Reception device, 201 ...... First storage device, 202 ...... Second storage device, 203 ...... Address information generating means, 204 ...... Switching means, 205 ...... Data updating means

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Junichi Fujimori 10-1 Nakazawa-cho, Hamamatsu-shi, Shizuoka Yamaha stock company (72) Inventor Takeshi Funada 10-1 Nakazawa-cho, Hamamatsu-shi, Shizuoka Yamaha stock company

Claims (2)

[Claims] 1. A transmission device that transmits data when first address information is supplied, a reception device that receives the data when second address information is supplied, and two address information as a set. A main control unit which is formed by connecting a plurality of sets of this address information and generates an address information sequence including the first and second address information; and when the main control unit supplies the address information sequence, A data transfer system comprising: a timing control device that supplies each piece of address information constituting the above to the transmitting device and the receiving device in a predetermined order and at a predetermined timing in a set unit. 2. An address information generating means for generating address information which circulates in a predetermined cycle, and a first storage device which, when supplied with the address information, outputs the contents of an address designated by the address information. When the address information is supplied, a second storage device that outputs the contents of the address specified by the address information, and the address information supplied from the address information generating means are supplied to the first and Switching means for alternately supplying to the second storage device, and data updating means for updating the contents of the first or second storage device on the side to which the address information is not supplied. Timing control device.