JPH0732223B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0732223B2 JPH0732223B2 JP60003876A JP387685A JPH0732223B2 JP H0732223 B2 JPH0732223 B2 JP H0732223B2 JP 60003876 A JP60003876 A JP 60003876A JP 387685 A JP387685 A JP 387685A JP H0732223 B2 JPH0732223 B2 JP H0732223B2
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- lead
- center
- leads
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 230000000694 effects Effects 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、パツケージの中心にリードを有するDIL（デ
ユアル・インライン）形樹脂封止型パツケージ構造の半
導体装置，特にメモリIC用リードフレーム部のパターン
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a semiconductor device having a DIL (dual in-line) type resin-sealed package structure having a lead in the center of the package, and particularly to a lead frame portion for a memory IC. It is about patterns.
メモリICは高集積度化が進み、年々チツプサイズが大き
くなつてきているが、パツケージサイズに制限がある場
合のチツプサイズはパツケージの短手方向より長手方向
に対して大きくなり、現在、パツケージ長手方向のチツ
プサイズが10mmを超えるものがでてきている。As memory ICs are becoming more highly integrated and the chip size is increasing year by year, the chip size when the package size is limited becomes larger in the longitudinal direction than in the lateral direction of the package. Chip sizes exceeding 10 mm are coming out.
また、メモリIC素子の中央部分はメモリセルで占められ
ているため、外部リード接続用の内部電極（ボンテイン
グパツド）はチツプ長手方向の両サイドに設けられてい
る。Further, since the central portion of the memory IC element is occupied by the memory cells, internal electrodes (bonding pads) for connecting external leads are provided on both sides in the chip longitudinal direction.
このようにチツプの長さが10mmを超えるようなメモリIC
をパツケージの中央にリードを有するDIL形樹脂封止型
パツケージ（18ピン,22ピンのようにパツケージ片側の
リード総数が奇数となるもの）に適用した場合、組立工
程で次のような問題が生じる。第２図に示すパツケージ
サイズが300ミルで18ピンDIL形樹脂封止型パツケージを
例にあげて説明する。In this way, memory ICs whose chip length exceeds 10 mm
When applied to a DIL type resin-sealed package that has a lead in the center of the package (the number of leads on one side of the package is odd such as 18-pin and 22-pin), the following problems occur during the assembly process. . The 18-pin DIL type resin-sealed package having a package size of 300 mils shown in FIG. 2 will be described as an example.
第２図はリードフレームに10mmのチツプを搭載しワイヤ
リングしたものである。ここで、リードフレーム１は、
チツプを搭載するためのダイスパッド２と、このダイス
パッド２の両側から引き出された支持枠３と、ダイスパ
ッド２の両側を挾むように多数設けられたリード４-1〜
４-18から構成され、この各リード４-1〜４-18が図示し
ないダムバーで互に連結されると共に、このダムバーが
図示しない枠状のフレームで連結されている。このよう
なリードフレーム１に対し、ダイスパツド２上にメモリ
IC用の上記チツプ５を搭載したのち、このチツプ５上の
中央部分にあるメモリセル６を除く長手方向の両サイド
に設けられた内部電極７とその周囲にある各リード４-1
〜４-18との間でワイヤ８を介してワイヤリングして接
続がなされている。なお、リードフレーム１上の破線で
示す符号９はモールドラインであり、このモールドライ
ン９が上記チツプ５を樹脂封止するためのパツケージサ
イズに相当し、そのパツケージ・ダイスパツドセンター
を符号Ａ−Ａ′で示している。Figure 2 shows a 10mm chip mounted on a lead frame and wired. Here, the lead frame 1 is
A die pad 2 for mounting a chip, a support frame 3 pulled out from both sides of the die pad 2, and a large number of leads 4 -1 provided so as to sandwich both sides of the die pad 2.
4 -18 . The leads 4 -1 to 4 -18 are connected to each other by a dam bar (not shown), and the dam bars are connected by a frame-shaped frame (not shown). For such a lead frame 1, memory is placed on the die pad 2.
After mounting the chip 5 for the IC, the internal electrodes 7 provided on both sides in the longitudinal direction except the memory cell 6 in the central portion on the chip 5 and the leads 4 -1 around the internal electrodes 7 are provided.
4 to 18 are connected by wiring via a wire 8. A reference numeral 9 indicated by a broken line on the lead frame 1 is a mold line, and this mold line 9 corresponds to a package size for resin-sealing the chip 5, and the package / dies pad center is designated by reference numeral A-. It is indicated by A '.
ところで、上記構成のDIL形パツケージにおいて、パツ
ケージの中央に位置するリード４-5およびリード４-14
のリード先端は隣り合うリード４-4およびリード４-13
を越えて先に伸ばすことはできない。それというのもフ
レーム製作上リードとリードの間隔はフレームの板厚以
上必要であり、リード４-5および４-14のリード先端が
リード４-4および４-13を超えるにはパツケージ短手方
向のチツプサイズを極めて小さくしなければならないた
め、現実的には困難である。By the way, in the DIL type package having the above structure, the lead 4 -5 and the lead 4 -14 located at the center of the package.
Of the lead is adjacent to lead 4 -4 and lead 4 -13.
You cannot extend beyond the point. This is because the distance between the leads must be equal to or greater than the plate thickness of the frame in order to manufacture the frame. If the lead tips of the leads 4 -5 and 4 -14 exceed the leads 4 -4 and 4 -13 , they are in the lateral direction of the package. This is practically difficult because the chip size of must be extremely small.
この結果、リード４-5および４-14に配線されるワイヤ
長さは極めて長くなるため、ワイヤ８がリード４-4,4
-13やダイスパツド２に接触し易いという問題が生じ、
ワイヤリング作業が不安定なものとなり、また信頼性上
大きな問題となる。As a result, the length of the wire wired to the leads 4 -5 and 4 -14 becomes extremely long, so that the wire 8 is connected to the leads 4 -4 ,
-13 or die pad 2 has a problem of being easy to contact,
Wiring work becomes unstable and becomes a big problem in reliability.
本発明は、上記の問題点を解決するためになされたもの
であり、ワイヤリングを容易にして信頼性を高めた半導
体装置を提供するものである。The present invention has been made to solve the above problems, and provides a semiconductor device in which wiring is facilitated and reliability is improved.
〔問題点を解決するための手段〕 本発明に係る半導体装置は、中央部に長方形のダイスパ
ッドを有し、このダイスパッドの長辺の両側にそれぞれ
奇数本のリードを所定ピッチ間隔で並設して成るリード
フレームと、このリードフレームのダイスパッドに搭載
され、ダイスパッドの短辺側に極在化して複数個の電極
が設けられた半導体チップと、このチップの上記電極と
リードの対向端とを接続するワイヤとを有する半導体装
置において、上記ダイスパッドの長手方向の中心位置を
リードフレームの中心より、リードの所定間隔の約1/2
だけリードのピッチ方向に移して形成し、上記ダイスパ
ッドの長手方向の中心位置に対してダイスパッドの長辺
に隣接して並設されたリードを対称に形成するととも
に、上記ダイスパッドの長手方向の中心位置側に位置す
る各リードに隣合う外側の各リードの一部に切欠きを設
け、上記ダイスパッドの長辺の両側にそれぞれ並設され
た奇数本のリードの内のそれぞれ中央の各１本のリード
とワイヤによって接続される半導体チップの各電極を、
リードフレーム中心に近い方の半導体チップ短辺部側に
それぞれ設けたものである。[Means for Solving the Problems] A semiconductor device according to the present invention has a rectangular die pad in the center, and odd-numbered leads are arranged in parallel on both sides of the long side of the die pad at predetermined pitch intervals. A lead frame, a semiconductor chip mounted on a die pad of the lead frame and having a plurality of electrodes localized on the shorter side of the die pad, and the opposite ends of the electrodes and leads of the chip. In a semiconductor device having a wire connecting with the center of the die pad in the longitudinal direction from the center of the lead frame, about 1/2 of the predetermined interval of the lead is provided.
Formed by moving in the lead pitch direction only, and symmetrically forming the leads juxtaposed adjacent to the long side of the die pad with respect to the center position of the die pad in the longitudinal direction, and in the longitudinal direction of the die pad. A notch is provided in a part of each outer lead adjacent to each lead located on the center position side of each of the odd-numbered leads juxtaposed on both sides of the long side of the die pad. Each electrode of the semiconductor chip connected by one lead and wire,
They are provided on the shorter side of the semiconductor chip closer to the center of the lead frame.
［作用］ 本発明においては、リードフレームのダイスパッドにチ
ップを搭載した場合、パッケージ中央に位置するリード
に接続するワイヤ長さをダイスパッドセンターとパッケ
ージセンターのズレ量だけ短くすることができ、しかも
ダイスパッドの長手方向の中心位置に対してダイスパッ
ドの長辺に隣接して並設されたリードを対称にし、か
つ、長手方向の中心位置側に位置する各リードに隣合う
外側の各リードの一部に切欠きを設けたので、中心位置
側のリードに接続されるワイヤが隣接するリードへ接触
するのを防ぐことができる。[Operation] In the present invention, when the chip is mounted on the die pad of the lead frame, the length of the wire connected to the lead located in the center of the package can be shortened by the amount of deviation between the die pad center and the package center. The leads arranged side by side adjacent to the long side of the die pad are symmetrical with respect to the center position in the longitudinal direction of the die pad, and the outer leads adjacent to the leads located on the center position side in the longitudinal direction are adjacent to each other. Since the notch is provided in part, it is possible to prevent the wire connected to the lead on the center position side from coming into contact with the adjacent lead.
［実施例］ 以下、本発明を図面に示す実施例に基いて説明する。[Examples] The present invention will be described below based on Examples shown in the drawings.
第１図は本発明の一実施例によるリードフレームにチツ
プをワイヤリングした18ピンDIL形パツケージ構造のメ
モリICを示す主要平面図である。この実施例では、チツ
プを搭載するためのダイスパツド２と、このダイスパツ
ド２の両側から引き出された支持枠３と、ダイスパツド
２の両側を挾むように多数設けられたリード４-1〜４
-18と、この各リード４-1〜４-18を互に連結するダムバ
ーおよびフレームからリードフレーム１が構成されてい
る点は上記した従来の第２図に示すものと同様である
が、このリードフレーム１のダイスパツド２のセンター
（チツプセンター）Ｃ−Ｃ′がパツケージセンターＢ−
Ｂ′から1.27mm離れている。そして、パツケージセンタ
ーＢ−Ｂ′に位置するリード４-5および４-14にワイヤ
８を介してそれぞれ接続されるチツプ５上の２個の内部
電極７が同一端面に配置されている。さらに、ダイスパ
ッドセンターＣ−Ｃ′に対してリード４-4と４-5、４-3
と４-6、４-14と４-15及び４-13と４-16がそれぞれ図示
されるように対称に配列して形成されている。なお、図
中，第２図と同一符号は同一また相当部分を示す。FIG. 1 is a main plan view showing a memory IC having an 18-pin DIL type package structure in which a chip is wired to a lead frame according to an embodiment of the present invention. In this embodiment, a die pad 2 for mounting a chip, a support frame 3 pulled out from both sides of the die pad 2, and a large number of leads 4 -1 to 4 provided so as to sandwich both sides of the die pad 2.
-18 and, although that it is configured that the lead frame 1 from the dam bar and the frame to each other connecting the respective leads 4 -1 to 4 -18 is the same as that shown in FIG. 2 of the prior art described above, this The center (chip center) C-C 'of the die pad 2 of the lead frame 1 is the package center B-.
1.27 mm away from B '. Then, two internal electrodes 7 on the chip 5 are connected through the wire 8 to the lead 4 -5 and 4-14 located Patsu cage center B-B 'is positioned on the same end face. Further, the leads 4 -4 and 4 -5 , 4 -3 with respect to the die pad center C-C '.
And 4 -6 , 4 -14 and 4 -15 and 4 -13 and 4 -16 are symmetrically arranged as shown in the drawing. In the figure, the same reference numerals as those in FIG. 2 indicate the same or corresponding parts.
このように、パツケージの長手方向に対するダイスパツ
ドセンターＣ−Ｃ′をパツケージラインＢ−Ｂ′より1.
27mm離し、パツケージ中央に位置するリード４-5および
４-14にワイヤ８を介して接続される２個の内部電極７
を同一端面に配置することにより、リードフレーム１の
ダイスパツド２に上記サイズのチツプ５を搭載しワイヤ
リングした場合、前記各リード４-5および４-14に接続
されるワイヤ８の長さは、ダイスパツドセンターＣ−
Ｃ′とパツケージセンターＢ−Ｂ′のズレ量だけ短かく
なる。これによつて、ワイヤリング作業が容易に行な
え、ワイヤ８のダイスパツド２などへの接触もなく、信
頼性向上がはかれる。Thus, the die pad center C-C 'with respect to the longitudinal direction of the package is 1. from the package line BB'.
Apart 27 mm, 2 pieces of the internal electrodes 7 are connected via the wire 8 to the lead 4 -5 and 4-14 located in the bobbin center
When the chips 5 of the above size are mounted on the die pad 2 of the lead frame 1 and wired, the length of the wire 8 connected to each of the leads 4 -5 and 4 -14 is Pad Center C-
It becomes shorter by the amount of deviation between C'and the package center BB '. As a result, the wiring operation can be easily performed, the wire 8 does not come into contact with the die pad 2, and the reliability is improved.
なお、ダイスパツド２のズレ量としてはリードピツチの
1/2,即ち1.27mmが最もワイヤ長を短かくできる。上述の
実施例では、パッケージの長手方向に対するダイスパッ
ドセンターＣ−Ｃ′をパッケージラインＢ−Ｂ′よりリ
ードピッチの約1/2ずらして、このダイスパッド２の周
辺に配列されるリードのうち４-4と４-5、４-3と４-6、
４-14と４-15及び４-13と４-16それぞれをダイスパッド
センターＣ−Ｃ′に対して対称に配列する場合について
示したが、本発明はこれに限らず、ダイスパッド２の長
辺の両側にそれぞれ並設される奇数本のリードの内のそ
れぞれ中央の各１本のリードに隣合うリード４-3,4-6及
び４-13及び４-16の一部に切欠き10を設けることもでき
る。この構造によると、中央の各１本のリード４-4,
4-5,4-14,4-15とそれに対応してリードフレーム中心に
近い方のチップ短辺部にそれぞれ設けられた内部電極７
が接続されるワイヤ８が、隣合う各リード４-3,4-6及び
４-13,4-16へ接触するのを効果的に防ぐことができる。The amount of displacement of the die pad 2 depends on the lead pitch.
1/2, or 1.27 mm, can be the shortest wire length. In the above-described embodiment, the die pad center C-C 'with respect to the longitudinal direction of the package is shifted from the package line B-B' by about 1/2 of the lead pitch, and four of the leads arranged around the die pad 2 are arranged. -4 and 4 -5 , 4 -3 and 4 -6 ,
The case where 4 -14 and 4 -15 and 4 -13 and 4 -16 are arranged symmetrically with respect to the die pad center C-C 'is shown, but the present invention is not limited to this, and the length of the die pad 2 is not limited to this. A notch 10 is formed in a part of leads 4 -3 , 4 -6 and 4 -13 and 4 -16 that are adjacent to each one lead in the center of each of the odd number leads arranged side by side. Can be provided. According to this structure, one lead at the center 4 -4 ,
4 -5 , 4 -14 , 4 -15 and corresponding internal electrodes 7 provided on the short side of the chip closer to the center of the lead frame
It is possible to effectively prevent the wire 8 to be connected to each other from coming into contact with the adjacent leads 4 -3 , 4 -6 and 4 -13 , 4 -16 .
以上説明したように本発明によれば、リードフレームの
ダイスパッドにチップを搭載した場合、パッケージ中央
に位置するリードに接続するワイヤ長さをダイスパッド
センターとパッケージセンターのズレ量だけ短くするこ
とができ、しかもダイスパッドの長手方向の中心位置に
対してダイスパッドの長辺に隣接して並設されたリード
を対称にし、かつ、長手方向の中心位置側に位置する各
リードに隣合う外側の各リードの一部に切欠きを設けた
ので、中心位置側のリードに接続されるワイヤが隣接す
るリードへ接触するのを防ぐことができるという効果が
ある。As described above, according to the present invention, when the chip is mounted on the die pad of the lead frame, the wire length connected to the lead located in the center of the package can be shortened by the amount of deviation between the die pad center and the package center. In addition, the leads arranged side by side adjacent to the long side of the die pad can be made symmetrical with respect to the center position in the longitudinal direction of the die pad, and the outer side adjacent to each lead located on the center position side in the longitudinal direction. Since the notch is provided in a part of each lead, there is an effect that the wire connected to the lead on the central position side can be prevented from coming into contact with the adjacent lead.
第１図は本発明の一実施例によるリードフレームにチツ
プをワイヤリングしたDIL形パツケージ構造のメモリIC
の主要平面図、第２図は従来例によるリードフレームに
チツプをワイヤリングしたDIL形パツケージ構造のメモ
リICの主要平面図である。 １……リードフレーム、２……ダイスパツド、３……支
持枠、４-1〜４-18……リード、５……半導体素子（チ
ツプ）、６……メモリセル、７……内部電極、８……ワ
イヤ、９……モールドライン、Ａ−Ａ′……パツケージ
・ダイスパツドセンタ、Ｂ−Ｂ′……パツケージセンタ
ー、Ｃ−Ｃ′……ダイスパツドセンター、10……切欠
き。FIG. 1 is a memory IC having a DIL type package structure in which a chip is wired to a lead frame according to an embodiment of the present invention.
2 is a main plan view of a memory IC having a DIL type package structure in which a chip is wired to a lead frame according to a conventional example. 1 ...... lead frame, 2 ...... Daisupatsudo, 3 ...... support frame 4 -1 to 4 -18 ...... lead, 5 ...... semiconductor element (chip), 6 ...... memory cell, 7 ...... internal electrodes, 8 ...... Wire, 9 ...... Mold line, A-A '... Package / dies pad center, BB' ... Package center, CC '... Dies pad center, 10 ... notch.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭60−10651（ＪＰ，Ａ) 特開 昭55−93243（ＪＰ，Ａ) 特開 昭59−125644（ＪＰ，Ａ) 実開 昭58−195453（ＪＰ，Ｕ) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-60-10651 (JP, A) JP-A-55-93243 (JP, A) JP-A-59-125644 (JP, A) Actual development Sho-58- 195453 (JP, U)
Claims (1)
のダイスパッドの長辺の両側にそれぞれ奇数本のリード
を所定ピッチ間隔で並設して成るリードフレームと、こ
のリードフレームのダイスパッドに搭載され、ダイスパ
ッドの短辺側に極在化して複数個の電極が設けられた半
導体チップと、このチップの上記電極とリードの対向端
とを接続するワイヤとを有する半導体装置において、上
記ダイスパッドの長手方向の中心位置をリードフレーム
の中心より、リードの所定間隔の約1/2だけリードのピ
ッチ方向に移して形成し、上記ダイスパッドの長手方向
の中心位置に対してダイスパッドの長辺に隣接して並設
されたリードを対称に形成するとともに、上記ダイスパ
ッドの長手方向の中心位置側に位置する各リードに隣合
う外側の各リードの一部に切欠きを設け、上記ダイスパ
ッドの長辺の両側にそれぞれ並設された奇数本のリード
の内のそれぞれ中央の各１本のリードとワイヤによって
接続される半導体チップの各電極を、リードフレーム中
心に近い方の半導体チップ短辺部側にそれぞれ設けたこ
とを特徴とする半導体装置。1. A lead frame having a rectangular die pad in the center, and odd-numbered leads arranged side by side at predetermined pitch intervals on both sides of the long side of the die pad, and the die pad of the lead frame. A semiconductor chip having a plurality of electrodes that are mounted on the short side of the die pad and are polarized, and a wire that connects the electrode of the chip and the opposite end of the lead. The center position of the die pad in the longitudinal direction is moved from the center of the lead frame in the pitch direction of the lead by about 1/2 of the predetermined interval of the lead to form the die pad with respect to the center position in the longitudinal direction of the die pad. The leads arranged side by side adjacent to the long sides are formed symmetrically, and the outer leads adjacent to the leads located on the center position side in the longitudinal direction of the die pad are A notch is provided in each portion, and each electrode of the semiconductor chip connected to each lead by a wire is connected to one lead at the center of each of the odd leads arranged on both sides of the long side of the die pad. A semiconductor device characterized in that it is provided on each of the shorter side portions of the semiconductor chip closer to the center of the frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60003876A JPH0732223B2 (en) | 1985-01-11 | 1985-01-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60003876A JPH0732223B2 (en) | 1985-01-11 | 1985-01-11 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61163654A JPS61163654A (en) | 1986-07-24 |
| JPH0732223B2 true JPH0732223B2 (en) | 1995-04-10 |
Family
ID=11569385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60003876A Expired - Lifetime JPH0732223B2 (en) | 1985-01-11 | 1985-01-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0732223B2 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5593243A (en) * | 1979-01-04 | 1980-07-15 | Nec Corp | Semiconductor device |
| JPS58195453U (en) * | 1982-06-22 | 1983-12-26 | 富士通株式会社 | lead frame |
| JPS59125644A (en) * | 1982-12-29 | 1984-07-20 | Fujitsu Ltd | Semiconductor device |
| JPS6010651A (en) * | 1983-06-30 | 1985-01-19 | Toshiba Corp | Semiconductor device |
-
1985
- 1985-01-11 JP JP60003876A patent/JPH0732223B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61163654A (en) | 1986-07-24 |
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