JPH07322118A - Head separation type ccd camera and its synchronizing phase control method - Google Patents

Abstract

PURPOSE:To provide a head separation type CCD camera with which the length of a camera cable is never limited by correcting automatically the shift of phases due to the delay caused by the camera cable between a video data signal and a signal processing pulse. CONSTITUTION:A signal processing part 20 includes a video signal processing means 25, a reference signal generator means 23 which outputs a signal processing pulse and a synchronizing reference signal, a control signal generator means 27 which outputs a head synchronizing signal and a timing detection signal based on the synchronizing reference signal, a phase control means 31 which delays and controls the phase of the head synchronizing signal and sends this controlled signal to a camera head part 11, and a pixel control means 61 which outputs a delay decision signal to the means 27 to change and delay the output of the head synchronizing signal for each clock. Meanwhile the part 11 outputs a video timing signal to show the CCD output signal and its output timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a head separation type CCD camera in which a signal processing section and a camera head section are separated from each other to reduce the size of the camera head section.

[0002]

2. Description of the Related Art Nowadays, as an endoscope or a surveillance camera, a head-separated solid-state image pickup device camera (CCD camera) capable of inserting and arranging the camera head in a narrow space by miniaturizing the camera head. ) Is often used. In this head-separated CCD camera, a CCD, an image sensor drive pulse generator, a synchronous oscillation circuit, etc. are incorporated in the camera head section, and the output signal from the CCD is sent to the signal processing section through the camera cable. The camera head unit and the signal processing unit are synchronized by sending a clock signal to the camera head unit, and the CCD output signal sent from the camera head unit is detected by an integrated circuit as a video signal processing means, and further, A horizontal synchronizing signal and a vertical synchronizing signal are added and level adjustment is also performed to form a video signal of, for example, the NTSC standard.

In a head-separated CCD camera, a signal processing unit sends a head synchronization signal together with a reference clock signal to the camera head unit to control the timing of transfer pulses output from the image pickup device drive pulse generator to the CCD. In addition, there is a camera head that is further miniaturized by simplifying a circuit incorporated in the camera head.

In a television camera of the head separated type, when the camera cable becomes long, the signal delay time due to the camera cable affects the timing of detecting the CCD output signal in the signal processing unit and the timing of adding the synchronizing signal. Therefore, in many head-separated CCD cameras, the length of the camera cable is specified in advance.

[0005]

A surveillance camera using a head-separated CCD camera can freely set the installation location because the camera head is small, but when the camera cable becomes long, the camera head can be set freely. It is necessary to adjust the timing of the signal processing pulse such as sampling and holding and the CCD output signal depending on the time it takes for the CCD output signal to reach the signal processing unit.

That is, since it takes about 5 nanoseconds for a signal to travel 1 meter of the camera cable, when the head synchronization signal is output from the signal processing unit to control the CCD in the camera head unit, this head synchronization is required. When the video data signal output from the CCD based on the signal is input to the signal processing unit, a delay of about 100 nanoseconds occurs every time the length of the camera cable increases by about 10 meters, which is similar to that of a surveillance camera. If the cable length is as long as several tens of meters and the required camera cable length differs depending on the installation location, it may be difficult to adjust the timing between the head synchronization signal and the signal processing pulse. It was

When the CCD is composed of hundreds of thousands of pixels and many pixels like today, the cycle of the read clock is as short as several tens of nanoseconds to hundreds of nanoseconds, and the signal processing pulse is used in the signal processing. Not only the phase of
When the length of the camera cable becomes long, a pixel unit shift may occur during signal processing.Therefore, the signal processing unit that adjusts the phase using the phase locked loop circuit adjusts the timing of the video data of each pixel and the signal processing pulse. However, since the synchronization signal and pixel data are not combined properly, the range of camera cable length that can be used according to the timing of the processing pulse in the signal processing unit is limited, The timing of the signal processing pulse must be adjusted according to the length of the cable.
There was a drawback that the mass productivity of CD cameras could not be improved.

The present invention eliminates such drawbacks, and provides a head-separated CCD camera which can always perform signal processing with accurate timing in the signal processing unit even when using camera cables of various cable lengths. What you do is as follows.

[0009]

According to the present invention, there is provided a video signal processing means, a reference signal generating means for outputting a signal processing pulse to the video signal processing means and a sync reference signal, and the sync reference signal. Control signal generating means for outputting a head synchronizing signal and a timing detection signal based on the synchronizing reference signal, phase adjusting means for delay adjusting the phase of the head synchronizing signal and sending it to the camera head part, and output of the head synchronizing signal And a pixel adjusting means for outputting to the control signal generating means a delay determination signal for changing and delaying each of the clocks in units of clocks, and the camera head shows the output timing of the CCD output signal in addition to the CCD output signal. It is the camera head that outputs the video timing signal.

Further, the video signal processing means, the reference signal generating means for outputting the signal processing pulse to the video signal processing means and the sync reference signal, and the sync reference signal are inputted and based on the sync reference signal. Control signal generating means for outputting a head synchronizing signal and timing detection signal, phase adjusting means for delay adjusting the phase of the signal processing pulse and sending it to the video signal processing means, and the signal processing pulse for each clock in the video signal processing means. The signal processing unit may include a pixel adjustment unit that outputs a delay determination signal to be delayed.

Further, a video signal processing means and a reference signal generating means for outputting a signal processing pulse to the video signal processing means and a sync reference signal, and a head based on the sync reference signal to which the sync reference signal is input. Control signal generating means for outputting a synchronizing signal or timing detection signal, phase adjusting means for delay adjusting the phase of the head synchronizing signal and sending it to the camera head section, and video signal processing means for delaying the signal processing pulse in clock units. In the case of a signal processing section having a pixel adjusting means for outputting a delay decision signal, or a video signal processing means and a reference signal generating means for outputting a signal processing pulse to the video signal processing means and also outputting a synchronization reference signal. , This sync reference signal is input and the head sync signal and timing detection signal based on the sync reference signal are output. And control signal generating means for,
Phase adjustment means for delay-adjusting the phase of the signal processing pulse and sending it to the video signal processing means, and pixel adjustment means for outputting to the control signal generation means a delay determination signal that delays the output of the head synchronization signal by changing in clock units. The signal processing unit may be included in some cases.

Further, a large number of delay elements having the same delay time are arranged in series and a predetermined signal is allowed to pass therethrough to form a large number of phase delayed signals whose timings are shifted,
Each phase delay signal is compared with the video timing signal output from the camera head to detect the phase difference between the predetermined signal and the video timing signal, and one of the phase delay signals is selected based on the detection result. The synchronous phase adjustment method will be adopted.

[0013]

[Operation] According to the present invention, the video signal processing means can perform signal processing such as detection on the CCD output signal to obtain a video signal. Further, since it has the control signal generating means for outputting the head synchronizing signal based on the synchronizing reference signal, by sending the head synchronizing signal outputted by this control signal generating means to the camera head section through the phase adjusting means. The timing of outputting the video data signal from the CCD in the camera head unit can be controlled, and the output timing of the CCD output signal can be adjusted within a minute range by shifting the phase of the head synchronizing signal by the phase adjusting means.

Further, since the control signal generating means also has a pixel adjusting means for outputting a delay decision signal for changing the output timing in clock units when the head synchronizing signal is outputted, the output timing of the head synchronizing signal is clocked. Because the camera head unit is capable of making a large change in units and adjusting the timing when the signal transmission time caused by the length of the camera cable changes significantly, and outputting the video timing signal indicating the output timing of the CCD output signal. , From camera head to CC
It is possible to output the video timing signal together with the D output signal, and perform the phase adjustment between the CCD output signal and the signal processing pulse and the delay adjustment in clock units with reference to the video timing signal.

Further, by sending the head synchronizing signal output from the control signal generating means to the camera head section, the timing at which the CCD output signal is output from the camera head section is kept constant, and the phase of the signal processing pulse is adjusted by delaying the image. A signal processing section having a phase adjusting means for sending to the signal processing means and a pixel adjusting means for outputting a delay decision signal to the video signal processing means, adjusts the timing of the signal processing pulse by the phase adjusting means to adjust the signal processing pulse and the video data signal. Since it is possible to adjust the timing of the signal in a minute range for proper detection, and the video signal processing means is also provided with a pixel adjusting means for outputting a delay determination signal for delaying the processing pulse in clock units, clock unit To change the timing of the signal processing pulse drastically, and depending on the length of the camera cable Even after changing the timing to be input to the CCD output signal and the video timing signal is a signal processing unit including a data signal, a signal processing pulse to match the length of the camera cable may be greatly changed in clock units.

Then, the signal processing section having the phase adjustment means for delay-adjusting the phase of the head synchronization signal and sending it to the camera head section and the pixel adjustment means for outputting the delay decision signal for deciding the delay of the processing pulse in clock units The timing of the signal processing pulse and the video data signal can be adjusted in a minute range by adjusting the timing of the head synchronizing signal signal by the phase adjusting means, and the video signal processing means determines the delay of the processing pulse in clock units. Since it also has the pixel adjusting means for outputting the delay decision signal, the timing of the signal processing pulse and the video data signal can be largely changed according to the length of the camera cable.

The signal processing section having the phase adjusting means for delay-adjusting the phase of the signal processing pulse and sending it to the video signal processing means and the pixel adjusting means for outputting the delay decision signal to the control signal generating means is the phase adjusting means. The timing of the signal processing pulse can be adjusted by adjusting the timing of the signal processing pulse and the video data signal in a minute range, and the delay determination signal for delaying the output of the head synchronization signal by the clock unit is delayed by the control signal generating means. Since it has the pixel adjusting means for outputting to, the timing of the signal processing pulse and the video data signal can be largely changed according to the length of the camera cable.

Furthermore, a method of forming a large number of phase delayed signals with different timings by arranging a large number of delay elements having the same delay time in series and passing a predetermined signal is output with the same waveform. It is possible to easily form a signal having different timings for a fixed time, and comparing each phase delay signal with the video timing signal to select one of the phase delay signals. By extracting the signal, it is extremely easy to convert the initial signal into a signal having a desired delay amount.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, an embodiment of a head-separated CCD camera according to the present invention comprises a CCD 15 as a two-dimensional solid-state image pickup device, a transfer gate pulse for driving the CCD 15 in accordance with the CCD 15, and a read clock. An image sensor drive pulse generator 13 that outputs an appropriate CCD drive pulse such as a pulse to the CCD 15, and also outputs a video timing signal E that has a predetermined timing in accordance with this CCD drive pulse, a phase comparator 18, and a voltage. Clock recovery means using a phase locked loop circuit formed by a controlled oscillator 19
And a camera head unit 11 having an image sensor driving pulse based on a head synchronizing signal J sent from the signal processing unit to the camera head unit 11 by the clock reproducing unit 17. By outputting a CCD drive pulse from the generator 13, a CCD output signal C including a video data signal is output from the camera head unit 11 and sent to the signal processing unit 20, and an image from the image sensor drive pulse generator 13 is output. The timing signal E is also sent to the signal processing section.

The head synchronization signal J input to the camera head section 11 is composed of at least a drive timing signal A and a clock reference signal B, and as shown in FIG. For example, 8 pulses corresponding to the horizontal blanking period are formed so as to be output 30 times per second as the drive timing signal A, and the horizontal blanking period is adjusted in accordance with the timing corresponding to the horizontal blanking period based on the drive timing signal A. For example, seven pulses that are synchronized with the read clock cycle are formed as the clock reference signal B for each.

Therefore, in the camera head section 11, the clock reproducing means 17 can form a clock pulse having a phase synchronized with the pulse forming the drive timing signal A and the pulse forming the clock reference signal B. On the basis of the above, the CCD drive pulse is outputted from the image pickup device drive pulse generator 13 to the CCD 15 so as to start the reading of the frame in accordance with the drive timing signal A, and the vertical blanking period and the horizontal blanking period are provided. A video data signal D formed by video data in pixel units from the CCD 15 is output from the CCD 15 as a CCD output signal C.

The video timing signal E output from the image pickup device drive pulse generator 13 is based on the drive timing signal A and is included in the first blanking period.
It is formed by outputting a large number of pulses synchronized with the read clock within the horizontal scanning period.
Then, a CCD output signal C including this video data signal D
As shown in FIG. 3, the signal processing unit that receives the video timing signal E and the video signal C performs detection processing such as correlated double sampling using the signal processing pulse H on the CCD output signal C, and further adds a synchronization signal to the video signal. Video signal processing means 25
And a reference signal generating means 23 which outputs a signal processing pulse H to the video signal processing means 25 with a built-in oscillator and also outputs a synchronization reference signal I, and the reference signal I output by the reference signal generating means 23. Based on the above, the head synchronization signal J is output, the first timing detection signal K and the phase correction signal L are output to the phase adjusting means 31, and the second timing detection signal M and the pixel correction signal N are output to the pixel adjusting means 61. The control signal generating means 27, the phase adjusting means 31 for slightly delaying the head synchronizing signal by the delay element and outputting the same to the camera cable, and the second timing detection signal M for detecting the timing of the video timing signal E for controlling the control signal. Pixel adjusting means for outputting the delay decision signal O to the generating means 27
61 and.

The reference signal generating means 23 in the signal processing unit 20 produces an image such as a clamp pulse or a sample hold pulse necessary for detection processing as a signal processing pulse H and a blanking pulse for performing blanking processing in a blanking period. It outputs various pulses necessary for signal processing, and also outputs a frame start reference signal and a clock signal as the synchronization reference signal I.

The clock signal has the same frequency as the clamp pulse and the sampling and holding pulse in accordance with the processing speed of the CCD 15, and the frame start reference signal is output every 1/30 second and the blanking pulse is The output timing is set to output several clocks to ten and several clocks earlier. Then, based on the clock signal included in the synchronization reference signal I, the control signal generating means 27, as shown in FIG. 4, as the head synchronization signal J, uses eight clock pulses as the drive timing signal A and the synchronization reference signal I. And outputs a single pulse signal as the phase detection pulse F within the first horizontal scanning period such as a delay of several tens of microseconds from the drive timing signal A. , 7 clock pulses are output as a clock reference signal B every 63.5 microseconds which is one horizontal scanning period with the drive timing signal A as a reference, and the first timing detection signal K is a phase detection pulse. A slight delay from F, and a single-shot pulse signal is output within one horizontal scanning period from the drive timing signal A.
A single pulse signal within one horizontal scanning period is output as the phase correction signal L from the drive timing signal A at a timing delayed from the timing detection signal K.
As shown in (2) of FIG. 4, the timing detection signal M is output with a length of several tens of microseconds after the drive timing signal A, and after the output of the second timing detection signal M, the single pulse signal is pixel-corrected. It is output as a signal N.

It is sufficient that the first timing detection signal K, the second timing detection signal M, the phase correction signal L, and the pixel correction signal N are output at a predetermined cycle such as every few seconds. . Then, the phase adjusting means 31
5, as shown in FIG. 5, a phase delay unit 32 in which a large number of delay elements 35 having the same delay time are connected in series, and a timing storage unit 37 using one D-flip-flop more than the delay elements 35. And a shift register 39 that holds the data in the timing storage unit 37, and a rising edge detection circuit that detects a rising edge in the output from this shift register 39.
A determination unit 41 configured by 43 and a counter circuit 45, and a phase calculation unit 51 that calculates the amount of phase shift based on the output of the determination unit 41.
And a phase delay signal J which is an output signal of the phase delay unit 32.
The selector 46 which selects one of 0, J1, J2, ..., Jn and outputs it to the camera cable.

In the present embodiment, the phase delay signal J0 outputs the input signal directly from the phase delay section 32 with the delay time set to 0. The phase delay unit 32 is, for example, a series of dozens of delay elements 35 having a delay time of several nanoseconds, and is a phase delay unit 32 capable of forming a delay time of one clock time or more. The input terminal of the section 32 and the output terminal of each delay element 35 are connected to the input terminal of the selector 46, and the input terminal of the phase delay section 32 and each delay element are connected.
The output terminals of 35 are connected to the clock input terminals of the D-flip-flops, which are timing storage sections 37, respectively, and all D-
The data input terminal of the flip-flop is connected to the video timing signal line of the camera cable, and the head synchronizing signal J from the control signal generating means 27 is input to the input terminal of the phase delay unit 32.

Therefore, in addition to the head synchronization signal J including the synchronization timing signal A, the clock reference signal B, and the phase detection pulse F from the phase delay unit 32, the delay time of the delay element 35 from the head synchronization signal J is several nanoseconds. A large number of phase-delayed signals J0, J having the same waveform as the head synchronization signal J delayed one by one.
1, J2, ..., Jn can be output. The phase delay signals J0, J1, J2, ..., Jn are input to the selector and also to the clock terminals of the D-flip-flops used as the timing storage section 37. Each time each pulse of A or the clock reference signal B and the phase detection pulse F is input, each D-flip-flop latches the level of the video timing signal E, which is a data input, but as shown in FIG. The video timing signal E outputs a pulse signal only within the first horizontal scanning period with a delay of a predetermined pulse from the drive timing signal A. Therefore, depending on the pulse of the drive timing signal A or the clock reference signal B, the timing storage unit 37 may be stored. The outputs of the respective D-flip-flops that are configured are maintained at a constant level, and when the phase detection pulse F is output, the timing is changed by the video timing signal E. Constituting the ring storage portion 37 D-output of the flip-flop is changed.

When the data from the timing storage unit 37 is changed by the phase detection pulse F included in the head synchronizing signal J, as shown in (1) of FIG. Each phase delay signal J0, J1, J2, ..., Jn slightly delayed by the delay time is formed by the phase delay unit 32, and the head synchronization signal J
As a result, the first D-flip-flop in the timing storage unit 37 latches the level of the video timing signal,
Phase delay signal J delayed by one of the delay elements 35
By 1, the latch timing of the D-flip-flops in the timing storage unit 37 is sequentially shifted by the delay time of the delay element 35 so that the second D-flip-flop latches the level of the video timing signal E.
In the timing storage unit 37, the data in which the level of the video timing signal E is latched at minute timings and different timings is output from the timing storage unit 37.

Further, each D- which constitutes the timing storage unit 37
The output terminal of the flip-flop is connected to the input terminal of the parallel-in / serial-out shift register 39, the output terminal of the shift register 39 is connected to the rising edge detection circuit 43 of the determination unit 41, and the first timing in the control signal generation means 27 is set. The output terminal of the signal K is connected to the load terminal of the shift register 39 and the reset start terminal of the counter circuit 45 in the determination unit 41, and the rising detection circuit of the determination unit 41 is connected.
The output terminal of 43 is connected to the count stop terminal of the counter circuit 45.

Therefore, the data input to the Qn terminal from the Qo of the shift register 39 is as shown in (2) of FIG.
The data of the level of the video timing signal E is stored with a delay time of several nanoseconds, which is the delay time of the delay element 35, and becomes the shift register by the first timing detection signal K.
This data is read into 39, and the data of this shift register 39 is detected by the rising edge detection circuit of the judging section 41 by the clock signal.
If sequentially output to the counter 43, the counter circuit 45 of the determination unit 41
The number of outputs is counted in accordance with the start of output of the shift register 39 by the timing signal K. For example, as shown in (2) of FIG. 6, the video timing signal becomes H at the timing of Qm.
When the level changes, the counter circuit 45 outputs the count value m and stops.

The output terminal of the counter circuit 45 in the judging section 41 is connected to the phase calculating section 51, and the phase calculating section
51 is a first for calculating the difference between the constant T and the output value m of the determination unit 41.
Phase for determining the input terminal of the selector 46 by the outputs of the second adder 55 and the register 57, which calculates the difference between the outputs of the adder 53, the register 57 and the register 57 and the output of the first adder 53 and returns it to the register 57 It is assumed that it is composed of a decoder 59 which outputs the delay selection signal W.

The constant T input to the first adder 53
Is for setting the optimum timing of a signal processing pulse such as a clamp pulse output from the reference signal generating means 23 to the video signal processing means 25 and the video data signal D input to the video signal processing means 25. A constant T that determines the optimum timing by the adder 53 and the phase m of the video timing signal E that is currently input to the signal processing unit 20 via the camera cable.
A register 57 for determining the timing of the current head synchronization signal J that is being output from the camera head section 11 by calculating the error S between Is calculated by the second adder 55 to calculate the necessary correction amount for the current output value V of the register 57, and the output of the first adder 53 The correction amount is calculated by the second adder 55 according to the error S and the output of the second adder 55 is stored in the register 57 by the phase correction signal L input from the control signal generating means 27. The decoder 59 converts into a phase delay selection signal W for selecting the input terminal of the selector 46 according to the output value of the register 57 and outputs it to the selector 46.

Therefore, in the phase adjusting means 31, the judging section
The output of 41 is as shown in 2 of FIG.
, And the timing of the signal processing pulse H is different from the optimum value T, the phase calculator 51 calculates the difference between T and m as a correction value S, and changes the phase delay selection signal W by this correction value. Then, the input terminal of the selector 46 is switched, and the selector 46 uses the signal processing unit as a head synchronization signal.
By switching the phase delay signals J0, J1, J2, ..., Jn output from 20, the phase of the head synchronization signal J sent to the camera head section 11 via the camera cable is shifted, so that the head synchronization section in the camera head section 11 is synchronized. The phase of the clock signal based on the signal J is shifted, and by extension, the camera head unit 11
The phase of the CCD output signal C including the video timing signal E and the video data signal D output from the circuit is shifted so that the phase of the video data signal D and the phase of the signal processing pulse H are correctly aligned regardless of the length of the camera cable. It is possible to properly perform signal processing such as detection.

The phase adjusting means 31 is a phase delay unit.
A row of delay elements 35 is provided as 32, and a drive timing signal A and a clock reference signal B required for the operation of the camera head unit 11 as a head synchronization signal J include a phase detection pulse F that does not affect the operation of the camera head unit 11. However, as shown in FIG. 7, two sets of phase delay units in which the same delay element 35 is connected in series are provided, and the first phase delay unit 33 has the drive timing signal A and the clock reference signal as the head synchronization signal J. A signal of only B is input, and the output terminal of each delay element 35 that constitutes the first phase delay unit 33 is connected to the selector 46 so that one of the phase delay signals or the head synchronization signal without the delay element 35. J is selectively sent to the camera head unit 11, the phase detection pulse F is input to the second phase delay unit 34, and the input terminal of the second phase delay unit 34 and the second phase delay unit
The output terminal of each delay element 35 constituting the 34 may be connected to the clock terminal of each D-flip-flop in the timing storage section 37, and the determination section 41 and the phase calculation section 51 may perform the same processing as described above.

Further, as another circuit example of the phase adjusting means 31, as shown in FIG. 8, a phase delay section 32 to which a head synchronizing signal Jx including a phase detection pulse is inputted, and a phase delay section 32.
, Jn from the phase-delayed signals J0, J1, J2, ..., Jn from the control signal generating means 27 and select and output any one of the signals. A coincidence detection unit 38 that detects a level change of the video timing signal E as a clock input to the D-flip-flop, and an output of the coincidence detection unit 38 causes a deviation between the video timing signal E and the phase detection pulse F included in the head synchronization signal Jx. Determination unit 41 including a rising edge detection circuit 43 and a counter circuit 45, a phase calculation unit 51 that outputs a phase delay selection signal W that determines the input terminal of the selector 46 based on the output of the determination unit 41, and the determination unit 41. Depending on the output value of the
A decoder may be provided as the correction unit 47 for inputting to the.

When this circuit is used as the phase adjusting means 31, as shown in FIG. 9, as the head synchronizing signal Jx, the phase detecting signal F by a large number of pulses is generated within one horizontal scanning period after the drive timing signal A. The phase detection signal F is included in the timing subsequent to the first timing detection signal Kx, and the phase detection switching signal P is output according to the first timing detection signal Kx. By stopping the output of the detection switching signal P, the coincidence detection section 38 and the determination section 41 detect the shift between the video timing signal E and the phase detection pulse F in the head synchronization signal Jx by the phase detection pulse F, and the determination section 41. After the calculation processing in the phase calculation unit 51 is completed by the output of, the correction changeover switch 49 is returned and the phase delay selection signal W from the phase calculation unit 51 is input to the selector 46. Unishi to have.

It is preferable that the pulse forming the phase detection pulse signal F is synchronized with the pulse of the clock signal and used for phase adjustment when the clock signal is reproduced by the clock reproducing means 17 in the camera head section 11. . Also,
As shown in FIG. 10, the pixel adjusting means 61 is a pixel shift detecting section including a head pulse detecting circuit 64 and a counter circuit 65.
63 and a first adder 73 for calculating the difference between the output value signal Y of the counter circuit 65 and the constant R in the pixel shift detection unit 63.
And a second adder 75 for calculating the difference between the output value signal U of the first adder 73 and the output value signal O of the register 77 and inputting it to the register 77, and a delay calculation section 71 constituted by the register 77. It is supposed to be configured.

The video signal timing signal E via the camera cable is input to the head pulse detection circuit 64 in the pixel shift detection unit 63, and the counter circuit 65 in the pixel shift detection unit 63 inputs the clock signal φ to the clock terminal. In addition, the output terminal of the second timing detection signal M from the control signal generating means 27 is connected to the reset start terminal, and the output terminal of the head pulse detection circuit 64 is connected to the count stop terminal. The output terminal is connected to the input terminal of the first adder 73 in the delay calculation section 71.

The second timing detection signal M input to the counter circuit 45 in the pixel shift detection unit 63 is output at the timing following the end of the drive timing signal A in the head synchronization signal, as shown in FIG. The second timing detection signal M causes the counter circuit 45 to start counting clock pulses, and when the head pulse detection circuit 64 detects the head pulse of the video timing signal E, the counting is stopped, and the count value is output to the output signal Y. Is output to the delay calculation unit 71.

Then, in the delay calculating section 71, among the signal processing pulses H output from the reference signal generating means 23 to the video signal processing means 25, the output timing of the blanking pulse or the like forming the synchronization signal and the video data signal D The value R of the output signal Y of the counter circuit 45 is compared with the first adder 73 for the appropriate timing of the above, and when there is a difference between the constant R and the value of the output signal Y, the second adder 75 The value of the output signal O of the register 77 is corrected by the value of the output signal U of the first adder 73, and the output signal of the second adder 75 is adjusted by the pixel correction signal N from the control signal generating means 27.
A register based on this newly stored value stored in
The output of 77 is sent to the control signal generating means 27 as the delay decision signal O, and the control signal generating means 27
Then, when the head synchronization signal J is formed based on the synchronization reference signal I, the output timing of the drive timing signal A is changed in clock units based on the value of the delay determination signal O.

Therefore, the length of the camera cable changes by several tens of meters, and the drive timing signal A output from the signal processing section 20 is transmitted to the camera head section 11 for about 10 hours.
It changes by about 0 nanosecond, and this drive timing signal A
Based on the above, the time for sending the video data signal D of the first pixel of the CCD 15 to the signal processing unit 20 also changes by about 100 nanoseconds, so that the driving timing signal from the signal processing unit 20 is changed by the change in the camera cable length. Even when the time from the output to the input of the video data signal D of the first pixel to the signal processing unit 20 is several hundred nanoseconds, that is, the timing change of several pixels occurs, the reference signal generating means. When the sync reference signal I is output from 23, the output timing of the sync reference signal I is set earlier than the output timing of the signal processing pulse H such as a blanking pulse as described above, and the frame of this sync reference signal I is set. Output of the drive timing signal A in clock units when the drive timing signal A is formed by the control signal generating means 27 based on the start reference signal By adjusting the timing, regardless of the length of the camera cable, it is capable of adjusting the timing of the timing and signal processing pulse H of the video data signal D in the CCD output signal C.

As described above, in the present embodiment, the pixel adjusting means 61 adjusts the output timing of the head synchronizing signal J including the drive timing signal A in clock units, and the phase adjusting means 31.
Since the head synchronizing signal J can be phase-adjusted with the accuracy of about 1 to 1/100 of the clock signal to match the timing, the CCD output signal C is always used as the CCD output signal C regardless of the length of the camera cable. Signal processing with proper timing with the signal processing pulse H becomes possible.

The timing adjustment in clock units by the pixel adjusting means 61 does not usually need to be made if the length of the camera cable is constant. Therefore, the second timing detection signal M and the pixel correction signal N are It is sufficient to check the timing of the video data signal D and the signal processing pulse H by outputting at intervals of several tens of minutes after the power is turned on, and the first output to the phase adjusting means 31. The timing detection signal K and the phase correction signal L are controlled at intervals of several tens of seconds to several minutes because the delay time of the delay element 35 may change depending on temperature when a circuit element such as a buffer is used as the delay element 35. It is possible to output from the signal generating means 27 and perform timing adjustment and timing confirmation of the signal processing pulse H and the CCD output signal C at relatively short intervals. preferable.

In the above embodiment, the head synchronizing signal output from the control signal generating means 27 is adjusted in units of clocks or in the phase range, but in another embodiment, the signal processing pulse H is adjusted in units of clocks. It may be adjusted in the phase range. In the second embodiment, as shown in FIG. 11, the phase adjusting means 31 is provided between the reference signal generating means 23 and the video signal processing means 25, and the first phase delay section 33 forms the signal processing pulse H. It is assumed that one of the many delayed signals is selected by the selector 46 and sent to the video signal processing means 25, and the phase detection pulse F is input to the second phase delay section 34 to form many delayed signals. The timing storage unit 37 detects the phase difference between the delay signal from the second phase delay unit 34 and the video timing signal E from the camera cable, and the shift register 39, the determination unit 41, and the phase calculation unit 51 detect the video timing signal E. The proper timing is determined, and the first phase delay unit 33
, One of a large number of delay signals formed from the signal processing pulse H is selected by the selector 46 and sent to the video signal processing means 25, and the pixel adjusting means 61 is output from the control signal generating means 27 by the second timing signal M. The number of clocks from the time when the drive timing signal A is output until the leading pulse of the video timing signal E is input to the signal processing unit 20 via the camera cable is counted, and the video signal processing means 25 is counted according to the count value. The timing for outputting the blanking pulse is adjusted in clock units.

When adjusting the signal processing pulse in units of phase and clock, the register in the phase calculator 51 is used.
When the output value of 57 is less than or equal to the threshold value, an adjusting circuit 69 for adding 1 to the constant R set in the pixel adjusting means 61 is provided, and the phase calculating section 51 in the phase adjusting means 31 and the delay in the pixel adjusting means 61 are provided. The adjustment unit 69 is connected to the calculation unit 71 so that the adjustment amount in units of clocks can be corrected according to the phase adjustment amount of the signal processing pulse H.

In the second embodiment, the drive timing signal A is output from the control signal generating means 27 by the phase adjusting means 31 and the pixel adjusting means 61, and then the camera head section 11 operated by the drive timing signal A is operated. Phase shift and time delay until the video timing signal E is returned to the signal processing unit 20 are detected, the phase of the signal processing pulse H is shifted based on this shift and delay, and the processing timing is delayed. There is an advantage that the circuit setting of the signal processing unit 20 becomes easy.

In another embodiment, the head synchronizing signal J from the control signal generating means 27 is output to the camera cable through the phase adjusting means 31 as in the first embodiment, and the pixel adjusting means 61 outputs it. The delay decision signal O is input to the video signal processing means 25, and the timing adjustment in clock units may be performed by the video signal processing means 25 as in the second embodiment. Furthermore, the phase adjusting means 31 is different from the second embodiment. Similarly, it is provided between the reference signal generating means 23 and the video signal processing means 25, and adjusts the timing of the head synchronization signal output from the control signal generating means 27 in clock units by the delay decision signal O from the pixel adjusting means 61. There is also.

When adjusting the head synchronizing signal in clock units while adjusting the phase of the signal processing pulse,
Similar to the first embodiment, the phase calculating unit 51 and the delay calculating unit 71 are connected via the adjusting circuit 69, and when the output value of the register in the phase calculating unit 51 is less than or equal to the threshold value, the value of 1 is set to the pixel adjusting means 61.
In addition to the constant R set to, the adjustment amount in units of clocks can be modified in accordance with the phase adjustment amount of the signal processing pulse H.

As described above, in each of the embodiments, the image input from the camera head unit 11 using the phase detection pulse F or the like with the drive timing signal A included in the head synchronization signal J output from the signal processing unit 20 as a reference. The phase of the timing signal E is detected, and when it is different from the phase of the predetermined video timing signal E, the phase adjusting means 31 adjusts the phase of the head synchronizing signal J or the phase of the signal processing pulse H, and the camera cable. The head synchronizing signal J is changed in clock units in accordance with the time from the output of the drive timing signal A to the input of the video timing signal E to the signal processing unit 20 even if the length of the head changes significantly. , Even when the signal processing unit 20 and the camera head unit 11 are connected by the camera cables of various lengths, the signal processing unit 20 can change the length of the camera cable. In addition, the signal processing timing is corrected in clock units, and the phase is adjusted to the optimum timing to perform the signal processing, so that a head-separated CCD camera having an unlimited camera cable length can be obtained. .

The phase adjusting means 31 of the head-separated CCD camera can adjust the phase in units of 1 nanosecond to several nanoseconds using a large number of delay elements 35, and a buffer or the like is used for the delay element 35. Thus, the logic IC can be easily miniaturized, and the delay time can be easily selected by the number of the delay elements 35 by connecting the delay elements 35 having the same delay time in series. Further, since the phase adjusting means 31 does not need to form a synchronous loop, it has an advantage that noise due to jitter may not occur.

[0051]

According to the present invention, a large number of delay elements having the same delay time are arranged in series to form a large number of phase delay signals sequentially having a predetermined delay, and these phase delay signals and video timing signals are combined. This is a method of comparing and detecting the shift between the signal input to the delay element array and the video timing signal, and selecting one of the phase delay signals based on the detection result. Therefore, it is easily suitable for the video timing signal. A timing signal can be formed, and a signal having a phase suitable for the video timing signal can be easily obtained.

Further, it has a camera head section for outputting a CCD output signal and a video timing signal, and the signal processing section delay adjusts the phase of the head synchronizing signal and sends it to the camera head section. When the drive timing signal is outputted from the control signal generating means and the phase adjusting means for delay adjusting the phase of the signal processing pulse from the means and sending it to the video signal processing means, that is, the drive timing signal is outputted from the signal processing section. From time to time, the time at which the video timing signal based on this drive timing signal is input to the signal processing unit via the camera cable is measured in clock units, and the timing of the head synchronization signal output from the signal processing unit is adjusted in clock units. Or the timing of the signal processing pulse when the video data signal is processed by the signal processing unit. Since it is a head-separated CCD camera having a pixel adjusting means for outputting a delay determination signal for adjusting in units of clocks, the timing of the signal processing pulse formed in the signal processing unit and the video data signal input from the camera head unit. Can be adjusted in units of clocks and in the range of clock phase shifts, and can be adjusted to proper timing and phase even if the signal delay time exceeds the CCD clock cycle due to the length of the camera cable. It is a CCD camera, which is a head-separated CCD camera in which the length of the camera cable can be freely determined and the camera head can be arranged and used. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a camera head portion of a head-separated CCD camera according to the present invention.

FIG. 2 is a diagram showing an example of signals transmitted by a camera cable of a head separated CCD camera according to the present invention.

FIG. 3 is a block diagram showing an embodiment of a signal processing unit of a head separated CCD camera according to the present invention.

FIG. 4 is a time chart diagram showing a signal and a video timing signal outputted by a control signal generating means of the head separated CCD camera according to the present invention.

FIG. 5 is a block diagram showing an embodiment of phase adjusting means in a head-separated CCD camera according to the present invention.

FIG. 6 is a time chart showing the signal processing of the phase adjusting means in the head separated CCD camera according to the present invention.

FIG. 7 is a block diagram showing another embodiment of the phase adjusting means in the head separated CCD camera according to the present invention.

FIG. 8 is a block diagram showing a third embodiment of the phase adjusting means in the head separated CCD camera according to the present invention.

FIG. 9 is a time chart diagram showing another example of a head synchronization signal in the head separated CCD camera according to the present invention.

FIG. 10 is a block diagram showing an embodiment of pixel adjustment means in a head-separated CCD camera according to the present invention.

FIG. 11 is a block diagram showing another embodiment of the signal processing unit of the head separated CCD camera according to the present invention.

[Explanation of symbols]

11 camera head section 13 image pickup element drive pulse generator 15 CCD 17 clock reproducing means 18 phase comparator 19 oscillator 20 signal processing section 23 reference signal generating means 25 video signal processing means 27 control signal generating means 31 phase adjusting means 32, 33, 34
Phase delay unit 35 Delay element 37 Timing storage unit 38 Match detection unit 39 Shift register 41 Judgment unit 43 Rise detection circuit 45 Counter circuit 46 Selector 47 Correction unit 49 Correction changeover switch 51 Phase calculation unit 53, 55 Adder 57 register 59 Decoder 61 Pixel adjustment means 63 Pixel shift detection section 64 Leading pulse detection circuit 65 Counter circuit 69 Adjustment circuit 71 Delay calculation section 73, 75 Adder 77 Register

Claims (5)

[Claims] 1. A video signal processing means for forming a video signal by a CCD output signal, a reference signal generating means for outputting a signal processing pulse to the video signal processing means and a sync reference signal, and a sync reference signal. The control signal generating means for outputting the head synchronizing signal and the timing detection signal based on the synchronizing reference signal, the phase adjusting means for delay adjusting the phase of the head synchronizing signal and sending it to the camera head part, and the control signal generating means In addition to the CCD output signal, the output timing of the CCD output signal in addition to the CCD output signal And a camera head section for outputting a video timing signal indicating Separate CCD camera. 2. A video signal processing means for forming a video signal by a CCD output signal, a reference signal generating means for outputting a signal processing pulse to the video signal processing means and a sync reference signal, and a sync reference signal. Control signal generating means for inputting and outputting a head synchronizing signal and timing detection signal based on this synchronizing reference signal, phase adjusting means for delay adjusting the phase of the signal processing pulse and sending it to the video signal processing means, and signal processing pulse And a pixel adjusting means for outputting to the video signal processing means a delay determination signal for delaying the video signal processing means in clock units, and a signal processing for outputting the head synchronization signal from the control signal generating means to the camera head section. Section, CCD output signal,
A head-separated CCD camera, comprising: a camera head unit that outputs a video timing signal indicating the output timing of a CCD output signal. 3. A video signal processing means for forming a video signal by a CCD output signal, a reference signal generating means for outputting a signal processing pulse to the video signal processing means and a sync reference signal, and a sync reference signal are inputted. A control signal generating means for outputting a head synchronizing signal and a timing detection signal based on the synchronizing reference signal, a phase adjusting means for delay-adjusting the phase of the head synchronizing signal and sending it to the camera head, and a signal processing pulse In addition to the CCD output signal, a video timing signal indicating the output timing of the CCD output signal, in addition to the CCD output signal, a signal processing unit having a pixel adjustment unit that outputs a delay determination signal for delaying in clock units in the signal processing unit to the video signal processing unit. A head-separated CCD camera having a camera head section for outputting. 4. A video signal processing means for forming a video signal by a CCD output signal, a reference signal generating means for outputting a signal processing pulse to the video signal processing means and a sync reference signal, and a sync reference signal. Control signal generating means for inputting and outputting a head synchronizing signal and timing detection signal based on this synchronizing reference signal, phase adjusting means for delay adjusting the phase of the signal processing pulse and sending it to the video signal processing means, and control signal generating And a pixel adjusting means for outputting to the control signal generating means a delay determination signal for delay-changing the timing of the head synchronizing signal output from the means in clock units, and the head synchronizing signal from the control signal generating means to the camera head section. In addition to the output signal processing unit and the CCD output signal, the output timing of the CCD output signal is shown. A head-separated CCD camera, comprising: a camera head unit that outputs a video timing signal. 5. A plurality of delay elements having the same delay time are arranged in series and a predetermined signal is allowed to pass therethrough to form a large number of phase delay signals whose timings are shifted, and each phase delay signal and the camera head section are formed. Head separation type characterized by detecting a phase difference between a predetermined signal and a video timing signal by comparing with a video timing signal output from the device and selecting one of the phase delay signals based on the detection result. CCD camera synchronous phase adjustment method.