JPH07321852A - Method and device for generating correction signal for jitter meter - Google Patents

Abstract

PURPOSE:To generate a correction signal with stable jitter quantity or width. CONSTITUTION:An output signal in which the ratio of logic 1 to logic 0 is set in 50%:50% from a frequency divider 4 is inputted to the driving signal input terminals of two oscillators 1, 2. A first oscillator 2 is operated while the signal of logic 1 is being inputted from the frequency divider 4, and a second oscillator 2 is operated while the signal of logic 0 is being inputted from the frequency divider 4, and the phases when oscillation is started of both oscillators 1, 2 coincide with each other(i.e., the phase difference is zero). Therefore, signals with different periods A and B are generated at the period of 1/2 of the output signal of the frequency divider 4 alternately at the output terminal of an OR gate 5. The appearance frequency(occupied time) of the output signals of two periods A. B from the OR gate is provided with an occupancy ratio of 50%:50% on a time axis, therefore, the jitter quantity or width of the output of the OR gate 5 can be kept constant.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for generating a calibration signal for a jitter meter.

[0002]

2. Description of the Related Art For example, in a digital signal train such as digital data transmitted through a transmission line using a high-speed communication network or an optical fiber, a pickup signal of a CD (compact disc), etc., the time axis depends on external factors and internal factors. Fluctuation, that is, jitter occurs. A jitter meter quantitatively measures the jitter in such a digital signal train.

FIG. 2 shows a signal waveform without jitter. That is, the voltage of the signal is zero at a measurement point after a fixed time from the reference point where the voltage zero of the signal is located.

On the other hand, FIG. 3 shows a signal waveform having a plurality of jitters. That is, if the measurement point is fixed after a fixed time T from the reference point where the voltage zero of each signal waveform is located,
The voltage at the measurement point is not constant between signal waveforms, and
When the time until the voltage of each signal becomes zero is measured, it can be seen that the measurement time is not constant between the signals, for example, T ₁ and T ₂ .

In the jitter meter, the voltage value at the fixed measurement point or the time until the voltage becomes zero is measured, and the measured value or the frequency of occurrence is displayed. Note that, in general, the frequency of occurrence of jitter is normally distributed like the noise component, so that the jitter meter often displays the jitter with the standard deviation.

The calibration signal generator for a jitter meter generates and supplies a calibration signal having a reference jitter amount or width to the above-mentioned jitter meter. Conventionally, such a calibration signal is generated by, for example, mixing a noise signal whose occurrence frequency is normally distributed with a digital signal without jitter.

Therefore, the noise component itself in such a calibration signal can be regarded as the jitter amount or width, and the occurrence frequency thereof is normally distributed as shown in FIG. 4, the vertical axis represents the occurrence frequency, the horizontal axis represents the measured value (the time from the reference point until the voltage becomes zero as shown in FIG. 3), X represents the average value, and σ represents the standard deviation. .

[0008]

However, a calibration signal generator for a jitter meter that generates a calibration signal by mixing a noise signal with a digital signal without jitter as described above can only obtain a calibration signal with low traceability. That is, an absolute reference calibration signal cannot be obtained.

For example, the noise signal itself used for the above mixing is ambiguous, the frequency component of the noise cannot be specified, and it is difficult to quantitatively specify the jitter amount or width. That is, for example,
10k when mixed signal is 100Hz and 1kHz
Each jitter amount or width at Hz cannot be specified as an absolute value. Therefore, even if the same calibration signal from the same calibration signal generation device for a jitter meter is used, for example, when two jitter meters having different frequency characteristics (responses) are used, the displayed values may be greatly different from each other. Yes,
There is a problem that the calibration signal lacks reliability.

Therefore, an object of the present invention is to provide a calibration signal generating method and apparatus for a jitter meter, which solves the above problems.

[0011]

SUMMARY OF THE INVENTION The present invention is directed to generating a switching signal at a predetermined period and, in response to the switching signal, generating a calibration signal whose period alternates between two different values. Characterize.

Furthermore, in the present invention, it is preferable that the calibration signal has a continuous phase when the cycle is switched.

Further, in the present invention, it is preferable that the calibration signal is generated alternately from two fixed period oscillating means at the predetermined period.

Further, in the present invention, it is preferable that the calibration signal is generated from one voltage control type oscillation means for switching and inputting each of two different control voltages in response to the switching signal at the predetermined period. It is characterized by

Further, in the present invention, preferably, a signal of a predetermined pattern is generated in response to the calibration signal.

Further, according to the present invention, a switching signal generating means for generating a switching signal at a predetermined cycle, and a calibration signal for switching the cycle to each of two different values in response to the switching signal from the switching signal generating means. And a calibration signal generating means for generating the calibration signal.

Further, in the present invention, it is preferable that the calibration signal generating means generate a calibration signal having a continuous phase when the cycle is switched.

Further, in the present invention, it is preferable that the calibration signal generating means is responsive to the switching signal, and two oscillating means that oscillate signals of different cycles that alternately operate at the predetermined cycle. And a means for taking out the signals from the two oscillating means as a calibration signal.

Further, in the present invention, it is preferable that the calibration signal generating means includes two voltage sources having different voltage values, a voltage control type oscillation means, and the two voltage sources in response to the switching signal. Means for alternately applying a voltage to the control voltage input terminal of the voltage control type oscillation means.

Further, the present invention is preferably characterized by further comprising means for generating a signal of a predetermined pattern in response to the calibration signal.

Further, in the present invention, it is preferable that the predetermined pattern generating means stores a predetermined voltage pattern responsive to the calibration signal as digital data, and the digital data in the storage means as the calibration signal. In response to the output, and means for converting the output digital data into an analog voltage and outputting the analog voltage.

Further, in the present invention, it is preferable that the predetermined pattern generating means stores the predetermined digital pattern responsive to the calibration signal as digital data, and the digital data in the storage means as the calibration signal. And a means for outputting in response to.

Further, in the present invention, preferably, a filter is provided on the output side of the output means.

[0024]

According to the present invention, two signals having different periods are alternately generated at a predetermined period, so that stable jitter is generated at an occupancy rate of 50%: 50%.

[0025]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. Reference numeral 1 is a first oscillator that oscillates a signal of cycle A, 2 is a second oscillator that oscillates a signal of cycle B, and both oscillators 1 and 2 operate while a drive signal from the outside is input. To output the signal. In this embodiment, the cycle A is shorter than the cycle B.

Reference numeral 3 denotes a third oscillator that oscillates a signal of cycle C,
A frequency divider 4 divides the output signal of the third oscillator 3 by 2 and outputs a rectangular wave signal. The frequency divider 4 outputs a logical 1
(High) and logic 0 (Low) time ratio is 1: 1
Signal is output.

Reference numeral 5 is an OR gate, which inputs output signals from the two oscillators 1 and 2. The output signal of the frequency divider 4 is input to the drive signal input terminals of the two oscillators 1 and 2.
The first oscillator 1 operates while the logic 1 signal is input from the frequency divider 4, and the second oscillator 2 operates while the logic 0 signal is input from the frequency divider 4 and both oscillators are operated. Both 1 and 2 have the same phase (for example, zero) at the start of oscillation. The oscillation frequencies of the first and second oscillators 1 and 2 are integral multiples of the oscillation frequency of the third oscillator 3.

Therefore, at the output end of the OR gate 5,
Signals having different periods A and B are alternately generated at a half period of the output signal of the frequency divider 4. Moreover, a signal whose phase is continuous at the time of switching between the cycles A and B is generated from the output terminal of the OR gate 5. FIG. 5 shows the appearance frequency (occupancy time) of the output signals of the two cycles A and B from the OR gate 5, both of which are 50%: 50 on the time axis.
Have a percent occupancy. As is apparent from FIG. 5, the jitter amount or width of the output of the OR gate 5 is constant. The oscillation frequency of either or both of the first and second oscillators 1 and 2 does not necessarily have to be an integral multiple of the oscillation frequency of the third oscillator 3. That is, even in this case, since the output of the OR gate 5 is a constant signal alternately at a cycle of 1/2 of the output signal of the frequency divider 4, there is no problem as a calibration signal.

Reference numeral 6 is a pattern generating circuit, which outputs a signal of a predetermined pattern as described later in response to the output signal of the OR gate 5.

FIG. 6 shows another embodiment of the present invention. Reference numerals 7 and 8 are two DC voltage sources having different voltage values, and 9 is a voltage controlled oscillator (VCO). Reference numeral 10 denotes a changeover switch, which responds to the output from the frequency divider 4 in response to the output from the first DC voltage source 7 when the logic is 1, and the second output when the logic is 0.
The output from the DC voltage source 8 is selected, and this is
9 is applied to the control voltage input terminal.

Therefore, at the output terminal of the VCO 9, signals having different periods (for example, A and B) from each other are provided to the frequency divider 4.
The output signals are alternately generated at a cycle of 1/2, and the phase of the generated signal at the time when the cycles are switched is continuous. This output signal is also in the state shown in FIG.

In each of the above embodiments, unlike the conventional case where noise is added to generate jitter, the amount or width of the jitter of the calibration signal does not change depending on the oscillation frequency of the third oscillator 3 shown in FIGS. Furthermore, regarding the frequencies at which the jitters A and B appear with respect to the reference X in FIG. 5, that is, the oscillation frequencies of the oscillators 1 and 2 in FIG. 1 and the oscillation frequency of the VCO 9 determined by the DC voltage sources 7 and 8 in FIG. For example, 100 Hz, 1 kHz, 10 kHz, etc. can be arbitrarily determined and selected, and the frequency characteristic of the jitter meter that affects the display of the jitter amount or width of the jitter meter (jitter measuring instrument) can be stably and reliably inspected (measured). And a reliable, stable and traceable calibration signal at each arbitrarily defined frequency.

FIG. 7 shows an example of the pattern generation circuit 6.
Reference numeral 11 indicates an output signal of the OR gate 5 or an output signal of the VCO 9 input as a clock signal at the clock input terminal by M.
A frequency divider 12 is an address generation counter, which has an N-bit count output terminal, the output bit is shifted every 1-bit count, and the same output terminal is turned on every N-bit count. Reference numeral 13 denotes N predetermined digital patterns (A ₀ to
ROM (or RAM) stored at the address A _N-1 ). In this case, the digital pattern data is transferred from an external CPU at the time of starting the circuit operation of the generator, resetting, or the like. The N addresses (A _{0 to} A _N-1 ) are connected to the output terminals of the counter 12,
M-bit (parallel) data output is M-bit input / 1
Bit output parallel / serial (hereinafter referred to as P / S)
Input to the conversion circuit 14. The same signal as the signal input to the frequency divider 11 is input to the clock input terminal of the P / S conversion circuit 14.

Therefore, every time M clocks are input to the frequency divider 11, the counter 12 is updated to access the corresponding address of the ROM 13. ROM in response to this
M-bit digital data in the accessed address of 13 is read and input to the P / S conversion circuit 14,
The P / S conversion circuit 14 serially outputs one bit for each clock of the signal input to the frequency divider 11. This output signal contains the stable jitter contained in the output signal of the OR gate 5 or the output signal of the VCO 9 as it is.

As the digital pattern in the ROM 13, in addition to a pattern according to the EFM system used for CD, MD, etc., a pattern according to the 8-10 conversion system used for DAT, etc., a floppy disk or a hard disk. Signals used, P used for mobile communication, etc.
There are SK, MSK signals, FSK signals used for broadcasting signals, and the like, but the signals are not limited to these as long as they have a digital pattern.

It should be noted that, for example, a filter can be further provided on the output side of the P / S conversion circuit 14 according to each digital pattern in the ROM 13 or according to the conditions of the jitter meter to be calibrated. That is, for example, when the EFM digital pattern is stored in the ROM 13, an OTF (optical transform function) filter is provided on the output side of the P / S conversion circuit 14, and the signal from this filter is used as a calibration signal. It should be noted that the OTF filter has the same characteristic as the attenuation characteristic of light generated by the optical lens that constitutes a part of the pickup for the CD recording surface in the CD reproducing device, and the calibration through the filter having such characteristic is performed. By using the signal, the jitter meter applied to the signal from the pickup can be calibrated.

FIG. 8 shows another example of the pattern generating circuit 6. Reference numeral 15 is an address generation counter having an N-bit count output terminal, which is an OR gate output signal or VCO input as a clock signal to the clock input terminal.
The output bit shifts every time the output signal of 9 is counted by one clock, and the same output terminal is turned on every N clock count. Reference numeral 16 denotes a ROM (may be a RAM, which is the same as the ROM 13) in which a pattern in which each data obtained by analog / digital conversion of a desired analog voltage waveform has M bits is stored in N addresses. , That N
Each address is connected to each output terminal of the counter 15, and the M bit (parallel) data output is input to the digital / analog (D / A) conversion circuit 17 having an M bit input. D /
The output of the A conversion circuit 17 is input to the low pass filter 18, a desired analog voltage waveform is taken out and used as a calibration signal.

[0039]

As described above, according to the present invention, it is possible to generate a calibration signal having high traceability and stable jitter. Further, it is possible to generate a calibration signal having a desired jitter amount or width at a desired frequency. Further, it is possible to generate a calibration signal having a desired pattern according to the target jitter meter.

[0040]

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a signal waveform without jitter.

FIG. 3 is a diagram showing a signal waveform with jitter.

FIG. 4 is a diagram showing a distribution state of noise signals.

FIG. 5 is a diagram showing a distribution state of calibration signals according to the present invention.

FIG. 6 is a block diagram of another embodiment of the present invention.

FIG. 7 is a block diagram showing an example of a pattern generation circuit.

FIG. 8 is a block diagram showing another example of a pattern generation circuit.

[Explanation of symbols]

 1 1st oscillator 2 2nd oscillator 3 3rd oscillator 4 frequency divider 5 OR gate

Claims (13)

[Claims] 1. A calibration signal for a jitter meter, wherein a switching signal is generated at a predetermined cycle, and in response to the switching signal, a calibration signal whose cycle is alternately switched to two different values is generated. Method of occurrence. 2. The method for generating a calibration signal for a jitter meter according to claim 1, wherein the calibration signal has a continuous phase when the period is switched. 3. The method for generating a calibration signal for a jitter meter according to claim 1, wherein the calibration signal is alternately generated from two fixed period oscillating means at the predetermined period. 4. The calibration signal according to claim 1 or 2, wherein the calibration signal is generated from one voltage-controlled oscillation means for switching and inputting two different control voltages in response to the switching signal at the predetermined period. A method for generating a calibration signal for a jitter meter, comprising: 5. The method for generating a calibration signal for a jitter meter according to claim 1, 2, 3 or 4, wherein a signal having a predetermined pattern is generated in response to the calibration signal. 6. A switching signal generating means for generating a switching signal at a predetermined cycle, and a calibration signal for switching the cycle to each of two different values in response to the switching signal from the switching signal generating means. A calibration signal generation device for a jitter meter, comprising a calibration signal generation means. 7. The calibration signal generating device for a jitter meter according to claim 6, wherein the calibration signal generating means generates a calibration signal having a continuous phase when the period is switched. 8. The oscillating signal generating means according to claim 6 or 7, wherein in response to the switching signal, two oscillating means for oscillating signals of mutually different cycles which alternately operate at the predetermined cycle, A calibration signal generation device for a jitter meter, comprising: means for taking out signals from the two oscillating means as a calibration signal. 9. The calibration signal generating means according to claim 6 or 7, wherein the two voltage sources having different voltage values, the voltage control type oscillating means, and the two voltage sources in response to the switching signal. And a means for alternately applying the above voltage to the control voltage input terminal of the voltage control type oscillating means. 10. The method according to claim 6, 7, 8 or 9,
A calibration signal generating device for a jitter meter, comprising means for generating a signal of a predetermined pattern in response to the calibration signal. 11. The storage device according to claim 10, wherein the predetermined pattern generation means stores a predetermined voltage pattern responsive to the calibration signal as digital data, and the digital data in the storage means as the calibration signal. A calibration signal generator for a jitter meter, comprising: a means for responding and outputting; and a means for converting the outputted digital data into an analog voltage and outputting it. 12. The storage means according to claim 10, wherein the predetermined pattern generation means stores a predetermined digital pattern responsive to the calibration signal as digital data.
A calibration signal generating device for a jitter meter, comprising: means for outputting the digital data in the storage means in response to the calibration signal. 13. The calibration signal generator for a jitter meter according to claim 12, wherein a filter is provided on the output side of the output means.