JPH07321295A - Arrangement method of cell columns and wiring channels in a semiconductor integrated circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] Regarding a method of arranging a cell row and a wiring channel in a semiconductor integrated circuit, the cell arrangement area and the wiring area are distinctly separated, and even after rough wiring in the wiring process. It aims to enable modification of cell layout and improve the ease of wiring. [Structure] Temporarily arranging cell rows with the maximum number of multi-stage cells as the height of the cell row, and if there is a cell row that can be divided in the longitudinal direction, divide the cell row to provide a new wiring channel, and , Wiring channels are allocated to wiring segments on the assumption that the number of wiring tracks in each wiring channel is infinite, and the wiring channel width is determined to be n / 2 times the height of the basic cell (n: natural number). In order to optimize the segment allocation and also to optimize the wiring segment allocation, the cell row is moved to determine the wiring channel width n / 2 times (n: a natural number) of the height of the basic cell. When the alignment with the underlying basic cell array is lost due to the movement of the row, the cell row is inverted and rearranged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method suitable for arranging cell columns and wiring channels in a semiconductor integrated circuit called a spread type gate array integrated circuit in which basic cells are arranged in an array.

In a spread type gate array integrated circuit, basic cells are arranged in an array on a semiconductor substrate in advance,
After that, new metal wiring is formed to realize the required logical function, but various problems have occurred with the increase in scale, and these must be eliminated.

[0003]

2. Description of the Related Art In recent years, with the progress of microfabrication technology, the number of mounted basic cells per chip in a spread type gate array integrated circuit, that is, the number of mounted gates, has increased, and therefore the number of mounted basic cells has been increased accordingly. The scale of logic circuits is also increasing.

In the arranging step, the wiring area is secured by the gate usage rate and the like in the rough layout, and the wiring rate is improved by adopting the virtual wiring length and the like in the detailed layout.

FIG. 11 is a flow chart showing a layout design flow for arranging gates and wirings in a conventional standard spread type gate array integrated circuit.

Step (a) When the scale of the logic circuit is large, it takes an enormous amount of time to perform placement and wiring collectively, and the success rate of placement and wiring becomes low. The wiring has to be repeated. Therefore, the logic circuit is divided into blocks of an appropriate scale, the area of each block is estimated, and the blocks are arranged on the chip.

Step (b) The gate usage rate, that is, (the number of used gates / the number of mounted gates) is estimated from the number of gates, the number of terminals, the number of nets, etc. in the mounted logic circuit to determine the chip size. .

Step (c) Arrangement of basic cells and macro cells. By the way, in the conventional standard layout design, cells are arranged in consideration of the virtual wiring length so that they do not overlap, and the area where the cells are not arranged is set as the wiring area. I haven't done it.

○ Step (d) Perform rough wiring. Specifically, the power supply wiring, the clock wiring, and the critical path wiring are preferentially wired in advance, and other long wirings roughly determine the route.

Step (e) Detailed wiring is performed. That is, all wiring is performed.

Step (f) It is checked whether the layout specifications are satisfied. If "yes", the process proceeds to the next step, and if "no", the cell parameters are changed and the placement process is redone.

Step (g): If the answer is "yes" in step (f), the process ends.

[0013]

As described above, when the scale of the logic circuit becomes large, the wiring for realizing the logic function becomes complicated and the logic cell cannot be arranged, so that the wiring area is increased more. It is becoming necessary.

As a result, the gate usage rate (the number of used gates / the number of mounted gates) becomes small, which causes a problem that the mounted gates cannot be effectively used.

Moreover, since the wiring setting requirements considered in the wiring process are not appropriate, cells of various sizes are arranged in a complicated manner. Therefore, if all the wiring cannot be realized no matter how many trials are made in the wiring process, it is impossible to perform wiring without improving the layout of the logic cells.

In this case, since it is necessary to perform the wiring process again after changing the parameters and arranging the logic cells, even if the desired logic circuit can be realized, the logic cell arranging process and the wiring process are performed. There is a problem that a huge amount of time is spent.

In order to solve the above problem, it is known to move the cell row to improve the cell arrangement (if necessary, refer to Japanese Patent Laid-Open No. 63-1004744).

FIG. 12 shows a conventional technique (Japanese Patent Laid-Open No. 63-100).
7 is a flow chart showing a layout design flow extracted from the contents of Japanese Patent No. 744).

First, logic design is performed.

Step (a) When a hierarchical layout is designed, a floor plan is designed.

Step (b) The chip usage rate is estimated to determine the chip size.

Step (c): A true cell row and a temporary wiring channel are set. The height of the cell row set here does not decrease until the rearrangement is performed by changing the parameter.

Step (d) Temporary placement is performed. That is, the cells are arranged in the cell row. In the subsequent tentative wiring process, the absolute position of the cell row changes, but the relative position of the cell row and the cell does not change.

Step (e) Temporary wiring is performed. Specifically, a horizontal wiring segment is assigned to a wiring channel, and the height of the wiring channel is determined.

Step (f) It is checked whether the layout is possible by adjusting the heights of the wiring channel regions. If yes,
In the next step (g), the layout is determined by optimizing the height of the wiring channel region. If "No", the logic scale is too large to be realized on the chip, so the logic design is redone.

Step (g) As a result of the wiring estimation based on the temporary wiring, the wiring channel is narrowed where it is wide and narrow when it is wide, and the layout is determined by optimizing the height of the wiring channel region. ○ Step (h) Perform all wiring in the detailed wiring process.

Step (i) It is checked whether the layout is completed. If "yes", the process proceeds to the next step, and if "no", the process returns to step (c) to adjust the parameter of the cell and redo the process.

Step (j): If the answer is "yes" in step (h), the process ends.

The present invention makes it possible to control the arrangement of multi-stage cells by setting cell columns having different heights, and to finely set the height of wiring channels by performing relocation. By dividing the cell row,
Try to improve the ease of wiring.

[0030]

SUMMARY OF THE INVENTION Here, some of the terms necessary for explaining the present invention will be explained with reference to
It must be explained in connection with the diagram of the array integrated circuit.

FIG. 13 is a plan view of relevant parts showing various parts of a standard spread type gate array integrated circuit.

In the figure, 1 is a gate array substrate, 2
Is a basic cell, 2A is a basic cell column, 3 is a macro block, 4 is an input / output pad or I / O (input / out)
pad), 5 is a wiring track, 6 is a cell row (a group of a plurality of basic cell rows), 7 is a horizontal wiring segment, 8 is a vertical wiring segment, and H _C is the height of the basic cell. There is. The gate array substrate 1
May be considered as one chip.

In the following description, when the terms mentioned here appear, it can be recognized that the parts shown in FIG. 13 or similar parts are assumed.

In the method of arranging cell rows and wiring channels in a semiconductor integrated circuit according to the present invention, (1) multi-stage cells (one basic stage 12
Multiple stages: See Fig. 2) (see Fig. 2 and Fig. 3)
In the case of, the cell rows can be divided in the longitudinal direction after the cell rows (cell rows 13; see FIG. 2) are temporarily arranged with the cell row height (cell row height H _L : see FIG. 2) Cell row (cell row 1
02 or 105: see FIG. 3), the cell row is divided (cell rows 102A, 102B, 105A, 1).
05B or the like: see FIG. 4) or a step of newly providing a wiring channel (wiring channels 102C and 105C or the like: see FIG. 4), or

(2) Each wiring channel (wiring channel 1
(4: FIG. 2) assumes that the number of wiring tracks (wiring track 5: see FIG. 13) is infinite, and after performing wiring channel allocation of the wiring segment (horizontal wiring segment 7: see FIG. 13), The step of optimizing the wiring segment allocation by determining the wiring channel width to n / 2 times (n: natural number) of the height of the basic cell (height of the basic cell H _C : see FIG. 13 or 8) is included. It is characterized by becoming.

(3) Wiring segment (horizontal wiring segment 7: see FIG. 13) The cell row (cell row 303: see FIG. 7) is moved to optimize allocation, and the height of the basic cell (basic The cell height H _C : n / 2 times (n: natural number) of the cell height H _C (see FIG. 7) is determined, and the underlying cell array (gate array substrate 1: When the matching with the cell row is lost, the cell row is inverted and rearranged (cell row 303C: FIG. 10).
(See) is included.

[0037]

When the cell row is moved by adopting the above means, half of the height of the basic cell is set as the minimum unit, so that a better layout improvement can be performed. Further, since the wiring segments are reallocated, it is possible to delete the empty tracks and improve the degree of integration. Furthermore, if the required wiring cannot be obtained even after trying the wiring many times, it is possible to return to the previous step, easily and easily improve the layout, and perform the wiring step again. Since it is not necessary to change the parameters and improve the layout, the layout can be realized in a short period.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a spread type gate according to an embodiment of the present invention.
6 is a flow chart showing a layout design flow for arranging gates and wirings in an array integrated circuit.

Step (a) When a hierarchical layout is designed, a floor plan is designed.

Step (b): Estimate the gate usage rate. If the hierarchical layout design is performed, the number of gates, the number of nets, the number of terminals, etc. for realizing the desired logical function are obtained from the standard cell connection information (net list) of the block, otherwise, the block is obtained. Alternatively, the gate usage rate is estimated in consideration of the shape of the chip and the number of used layers of metal wiring. Here, the standard cell refers to a cell in which some wiring is provided to a plurality of basic cells to have a required function.

Step (c) Designate a temporary cell column and a temporary wiring channel. FIG. 2 is a plan view of a main part for explaining the arrangement of the temporary cell row and the temporary channel. In the figure, 11 is a block (or chip), 12 is one stage of a basic cell, 13 is a cell row, 14
Indicates the wiring channel, and H _LM indicates the maximum height of the cell row.

The illustrated example is a case where the maximum number of stages in the used gate is three. When there are few 3-tier cells in the net list, it is possible to limit the cell rows in which the 3-tier cells can be arranged and concentrate the 3-tier cells there. Further, the width of the temporary wiring channel is set to be wide in the central portion and narrow in the peripheral portion, so that it is possible to control the arrangement according to the same length of the temporary wiring as in the conventional case.

Step (d) Temporary placement is performed. That is, the cells are provisionally arranged on the provisional cell row. Here, by using a temporary channel as a cell placement prohibited area, it can be easily implemented even by a conventional automatic placement and routing tool. FIG. 3 is an explanatory plan view of relevant parts for explaining the result of the temporary arrangement. In the figure, 100 to 105 are cell columns.

Step (e): A true cell column is set and a temporary wiring channel is set again. Here, among the cell rows shown in FIG. 3, if there are cell rows that can be separated in the horizontal direction, they are separated and a wiring channel is generated between them. The cell columns that can be separated in this way are the columns in which there are no cells that straddle the cell columns, and therefore, the cells in FIG.
In that case, cell columns 102 and 105 are that.

FIG. 4 is a plan view of a principal part for explaining the separation of the cell rows. In the figure, 102A, 102B, 1
Reference numerals 05A and 105B indicate isolated cell rows obtained by separating the cell rows 102 and 105 (see FIG. 3), and 102C and 105C indicate newly created wiring channels, respectively.

As shown, the isolated cell row 102.
Between A and 102B, and also between the separate cell rows 105A and 10B.
Wiring channel 102C or 105C between 5B
Is newly generated. At this stage, the cells included in the cell row are fixed, and thereafter only the width of the wiring channel is changed.

Step (f) The wiring segment is assigned to a temporary wiring channel according to the rough wiring, and the height of the wiring channel is determined. Generally, for example, in the wiring channel shown in FIG. 4, the number of wiring tracks is physically uniquely determined according to the height of each wiring channel.

However, here, the wiring channel is
Regardless of its width, the horizontal wiring segments are channel-assigned assuming that each has an infinite number of tracks.

FIG. 5 is a plan view of a principal portion for explaining the wiring channel allocation of the horizontal wiring segments.
In the figure, (A) shows the number of tracks listed for comparison as 5
, (B) assumes that the number of tracks is infinite, and 201 and 202 indicate cell columns, respectively.

As is clear from the figure, when the number of tracks is 5 (A), one or more wiring channels must be used, but when the number of tracks is infinite (B), one wiring channel is used. Can be assigned.

By the way, if the wiring channel width is optimized in the next step (g) based on the result of the rough wiring performed in the step (f) before entering the step (g) through the step (f), It is possible to estimate whether or not all wiring is possible. In the flow chart, this is indicated by "Is layout possible?". If "Yes", proceed to step (g) and "No". If so, return to the appropriate step.

Step (g) Reassignment of horizontal wiring segments and optimization of wiring channel width in consideration of actual wiring tracks.

In the spread type gate array, the wiring channel width cannot be increased by one track.
If tracks are greedily assigned to each net, empty tracks will occur. Therefore, the wiring channel width is determined by reallocating the wiring segments in consideration of the actual number of wiring tracks.

By the way, when wiring is provided to cells, there are various patterns of wiring segment allocation depending on which cells are connected. Next, description will be given thereof.

FIG. 6 is an explanatory plan view of relevant parts for explaining the number in the case of horizontal wiring segment allocation. In the figure,
(A) to (G) are main part planes of different examples, 20
Reference numerals 1 to 203 denote cell columns, respectively.

When there is a wiring request between adjacent cell columns, the number in the case of segment allocation in which only that net is optimized is determined only as shown in (A).

However, when there is a wiring request on the same cell row, there are two types as shown in (B) and (C), and there is a wiring request between cell rows separated by one row. In some cases, the number of segment allocation cases will explode as seen in (C) through (G).

In step (g), the numbers in this case are combined so that the wiring channel widths of each are an integral multiple or half of the height of the basic cell (for example, the height H _{C of the} basic cell shown in FIG. 11). The optimization is performed so as to double.

7 to 10 are plan views of the principal parts for explaining the case where the cell array is moved on the gate array substrate.

FIG. 7 shows the state before the movement, FIG. 8 shows the state moved by the height of the basic cell, FIG. 9 shows the state moved by half the height of the basic cell, and FIG. 10 shows the ground by reversing. Each state is shown.

In each figure, 301 is one basic cell, 302 is one level of basic cell, 303 is a cell row, 30
3A is cell column after moving the cell row 303 only basic cell height H _C content, 303B cell string 303 the height H cell column after moving half of _C of the basic cell, 303C cell string 303 Is moved by half of the height H _C of the basic cell and is vertically inverted and rearranged. H _C is the basic cell 3
The height of 01 and _HL indicate the height of the cell row 303, respectively. The black triangle mark is an index for clarifying the correspondence relationship with the base when the cell row is moved.

Moving the cell column 303 shown in FIG. 7,
In the case of the cell array 303A shown in FIG. 8, if the moving distance is 2 m / 2 times the height H _C of the basic cell 301 (m: natural number), the underlying cell array required by the cell array 303A. That is, there is no mismatch with the cell array on the gate array substrate (gate array substrate 1 seen in FIG. 11).

However, the cell column 303 is moved, and as shown in FIG.
As can be seen from Fig. 3, when the cell column 303B has a moving distance of (2m + 1) / 2 times (m: natural number) of the height H _C of the basic cell, the base cell required by the cell column 303B is • It causes a mismatch with the array.

Step (h): Underlaying is performed in consideration of the inversion rearrangement. As described above, when the cell column 303 is moved by half the height H _C of the basic cell, a mismatch with the underlying cell array occurs.

Therefore, if the cell row 303 is moved and then each cell is turned upside down to form the cell row 303C as shown in FIG. 10, it is possible to match with the base.

Step (i) Perform detailed wiring.

Step (j) Check if the layout is completed. It is checked whether all the wiring requirements are satisfied, and if they are satisfied, the procedure proceeds to step (k) to end. If they are not satisfied, the wiring parameters are changed and the detailed wiring is redone. If the conditions are still not met, go to step

Return to (g) or (f), and further to (d) or (c) to redo the process.

[0069]

According to the method for arranging cell columns and wirings in a semiconductor integrated circuit according to the present invention, the maximum number of stages in the multi-stage cells forming the circuit is set as the height of the cell columns, and the cell columns are temporarily arranged. After that, if there is a cell row that can be divided in the longitudinal direction, divide the cell row to provide a new wiring channel, and assume that the number of wiring tracks in each wiring channel is infinite. After allocating the wiring channel of the wiring segment, the wiring channel width is determined to be n / 2 times (n: a natural number) the height of the basic cell to optimize the wiring segment allocation. N of the height of the basic cell is performed by moving the cell row in order to optimize
Double (n: natural number) wiring channel width is determined, and when the alignment with the underlying basic cell array is lost due to the movement of the cell column, the cell column is inverted and rearranged. I am trying.

According to the above configuration, when the cell row is moved, half of the height of the basic cell is set as the minimum unit, so that a better layout improvement can be performed. Further, since the wiring segments are reallocated, it is possible to delete the empty tracks and improve the degree of integration. Furthermore, if the required wiring cannot be achieved even if the wiring is tried many times, it is possible to return to the previous step, easily and easily improve the layout, and perform the wiring step again. Since it is not necessary to change the parameters to improve the layout, the layout can be realized in a short period.

[Brief description of drawings]

FIG. 1 is a flow chart showing a layout design flow for arranging gates and wirings in a spread type gate array integrated circuit according to an embodiment of the present invention.

FIG. 2 is an explanatory plan view of relevant parts for explaining the arrangement of temporary cell rows and temporary channels.

FIG. 3 is an explanatory plan view of relevant parts for explaining a result of temporary placement.

FIG. 4 is an explanatory plan view of relevant parts for explaining cell column separation.

FIG. 5 is a plan view of a principal part for explaining wiring channel allocation of horizontal wiring segments.

FIG. 6 is an explanatory plan view of relevant parts for explaining the number in the case of horizontal wiring segment allocation.

FIG. 7 is an explanatory plan view of relevant parts for explaining a case where a cell row is moved on a gate array substrate.

FIG. 8 is an explanatory plan view of relevant parts for explaining a case where a cell array is moved on a gate array substrate.

FIG. 9 is an explanatory plan view of relevant parts for explaining a case where a cell row is moved on a gate array substrate.

FIG. 10 is a plan view of relevant parts for explaining a case where a cell row is moved on a gate array substrate.

FIG. 11 is a flow chart showing a layout design flow for arranging gates and wirings in a conventional standard spread type gate array integrated circuit.

FIG. 12 is a flow chart showing a layout design flow extracted from the contents of a conventional technique (Japanese Patent Laid-Open No. 63-100744).

FIG. 13 is a plan view of relevant parts showing various parts of a standard spread type gate array integrated circuit.

[Explanation of symbols]

1 gate array substrate 2 basic cell 2A gate row 3 macro block 4 input / output pad or I / O (input / output)
t) Pad 5 Wiring track 6 Cell row 7 Horizontal (that is, horizontal) wiring segment 8 Vertical wiring segment H _C Height of basic cell 11 Block (or chip) 12 One stage of basic cell 13 Cell row 14 Wiring channel H Maximum height of _LM cell row 100 cell row 101 cell row 102 cell row 103 cell row 104 cell row 105 cell row 102A separation cell row 102B separation cell row 105A separation cell row 105B separation cell row 102C newly generated wiring channel 105C Newly generated wiring channel 201 Cell row 202 Cell row 203 Cell row 301 One basic cell 302 One step of basic cell 303 Cell row 303A After moving cell row 303 by the height H _C of the basic cell Cell row 303B of cell row 303 is moved by half the height H _C of the basic cell Subsequent cell row 303C Cell row HL after moving the cell row 303 by half the height H _C of the basic cell and inverting and repositioning the cell row _HL Cell row 303 height

Claims (3)

[Claims] 1. A cell row is divided when there is a cell row that can be divided in the longitudinal direction after the cell row is tentatively arranged with the maximum number of rows in a multi-stage cell forming a circuit as the height of the cell row. A method of arranging cell columns and wiring channels in a semiconductor integrated circuit, which further comprises the step of newly providing wiring channels. 2. A wiring channel is assigned to a wiring segment on the assumption that the number of wiring tracks of each wiring channel is infinite, and then the wiring channel is set to n / 2 times the height of a basic cell (n: natural number). A method of arranging a cell column and a wiring channel in a semiconductor integrated circuit, which comprises the step of determining a width and optimizing wiring segment allocation. 3. A cell row is moved to optimize wiring segment allocation to determine a wiring channel width of n / 2 times (n: a natural number) the height of a basic cell, and the cell row is moved. Cell array in a semiconductor integrated circuit, including the step of reversing the cell array upside down when the alignment with the underlying basic cell array is lost due to And wiring channel placement method.