JPH07321246A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH07321246A JPH07321246A JP6105290A JP10529094A JPH07321246A JP H07321246 A JPH07321246 A JP H07321246A JP 6105290 A JP6105290 A JP 6105290A JP 10529094 A JP10529094 A JP 10529094A JP H07321246 A JPH07321246 A JP H07321246A
- Authority
- JP
- Japan
- Prior art keywords
- plate
- circuit board
- semiconductor device
- sealing resin
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 90
- 229920005989 resin Polymers 0.000 claims abstract description 59
- 239000011347 resin Substances 0.000 claims abstract description 59
- 238000007789 sealing Methods 0.000 claims abstract description 55
- 229910000679 solder Inorganic materials 0.000 claims abstract description 13
- 239000007769 metal material Substances 0.000 claims description 9
- VYQRBKCKQCRYEE-UHFFFAOYSA-N ctk1a7239 Chemical compound C12=CC=CC=C2N2CC=CC3=NC=CC1=C32 VYQRBKCKQCRYEE-UHFFFAOYSA-N 0.000 abstract 1
- 230000009466 transformation Effects 0.000 abstract 1
- 230000017525 heat dissipation Effects 0.000 description 8
- 230000002093 peripheral effect Effects 0.000 description 6
- 238000000465 moulding Methods 0.000 description 5
- 238000004382 potting Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は樹脂封止型の半導体装置
に関し、さらに詳細には裏面に半球形の半田ボールが格
子状に並べられた回路基板の表面に半導体チップを搭載
し、該半導体チップ搭載面側を封止樹脂で封止して成る
半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device, and more specifically, a semiconductor chip is mounted on the surface of a circuit board on the back surface of which hemispherical solder balls are arranged in a grid pattern. The present invention relates to a semiconductor device having a chip mounting surface side sealed with a sealing resin.
【０００２】[0002]
【従来の技術】表面実装型の半導体装置の一つとして、
図１３に示すように、配線パターンが形成された回路基
板１０の裏面に半球形の半田ボール１２を格子状に並
べ、スルーホールによって配線パターンと半田ボール１
２を接続したことを特徴とするボール・グリット・アレ
イ（以下、ＢＧＡという）がある。ＢＧＡを製造する際
には、裏面に多数の半田ボール１２が設けられたエポキ
シ樹脂等の回路基板１０の表面に半導体チップ１４を載
せ、ワイヤボンディングによるワイヤ１６によって半導
体チップ１４と回路基板１０に形成された配線パターン
を接続する。このようにして半導体チップ１４を、ワイ
ヤ１６とスルーホールを介して半田ボール１２に電気的
に接続する。そして、回路基板１０上に搭載された半導
体チップ１４を、封止樹脂１８で封止する。2. Description of the Related Art As one of surface mount type semiconductor devices,
As shown in FIG. 13, hemispherical solder balls 12 are arranged in a grid pattern on the back surface of the circuit board 10 on which the wiring patterns are formed, and the wiring patterns and the solder balls 1 are formed by through holes.
There is a ball grid array (hereinafter referred to as BGA) which is characterized by connecting two. When manufacturing a BGA, the semiconductor chip 14 is placed on the surface of the circuit board 10 made of epoxy resin or the like having a large number of solder balls 12 provided on the back surface, and the semiconductor chip 14 and the circuit board 10 are formed by the wires 16 by wire bonding. Connect the wiring pattern. In this way, the semiconductor chip 14 is electrically connected to the solder balls 12 via the wires 16 and the through holes. Then, the semiconductor chip 14 mounted on the circuit board 10 is sealed with the sealing resin 18.
【０００３】このＢＧＡによれば、パッケージの四つの
側面すべてからリードが出ているクワッド・フラット・
パッケージ（以下、ＱＦＰという）に比べ、パッケージ
の大きさを小さくでき、半導体装置の多ピン化にも対応
できる。また、ＢＧＡは、ＱＦＰと違い、リードの変形
の恐れがないという利点もある。According to this BGA, a quad flat type with leads extending from all four sides of the package
The size of the package can be made smaller than that of the package (hereinafter, referred to as QFP), and the number of pins of the semiconductor device can be increased. In addition, unlike the QFP, the BGA has an advantage that there is no fear of lead deformation.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、従来の
ＢＧＡでは、裏面に多数の半田ボール１２が設けられる
ため、図１３に示すように、半導体チップ１４が搭載さ
れた片面のみが封止樹脂１８で封止され、回路基板１０
の半導体チップ搭載面側に封止樹脂１８が偏っている。
このため、封止樹脂１８が硬化する際に収縮することに
よってパッケージが半導体チップ搭載面側に反ってしま
う。また、封止樹脂１８と回路基板１０との膨張率、弾
性率、回路基板側のレジスト膜と封止樹脂１８の密着性
等の不整合によって、パッケージの変形が発生する。そ
して、パッケージの薄型化の要求に伴い、最近はパッケ
ージの厚さが数ｍｍ程度の薄形になり、樹脂封止によっ
て反りが発生し易くなっている。さらにＢＧＡでは、Ｑ
ＦＰのように後でリードを修正曲げすることが不可能で
あるため、一旦変形が発生した場合は再生できない。そ
して、ＢＧＡに反りが発生すると、半田ボールの全てを
実装基板の実装面に接しさせることができず、ＢＧＡを
実装基板上へ確実に実装できないという課題がある。ま
た、樹脂封止型の半導体装置は熱放散性が低く、発熱量
の大きな半導体チップは搭載できないという課題もあるHowever, in the conventional BGA, since many solder balls 12 are provided on the back surface, as shown in FIG. 13, only one surface on which the semiconductor chip 14 is mounted is sealed with the sealing resin 18. Sealed and circuit board 10
The encapsulating resin 18 is biased toward the semiconductor chip mounting surface side.
For this reason, the package warps toward the semiconductor chip mounting surface side due to contraction of the sealing resin 18 when it is cured. In addition, the expansion of the encapsulation resin 18 and the circuit board 10, the elastic modulus, and the mismatch of the adhesion between the resist film on the circuit board side and the encapsulation resin 18 cause the package to be deformed. In response to the demand for thinner packages, the thickness of the packages has recently been reduced to about several millimeters, and warping is likely to occur due to resin sealing. Furthermore, in BGA, Q
Since it is impossible to correct and bend the lead later as in the FP, it cannot be reproduced once the deformation occurs. When the BGA warps, all the solder balls cannot be brought into contact with the mounting surface of the mounting board, which causes a problem that the BGA cannot be reliably mounted on the mounting board. In addition, the resin-encapsulated semiconductor device has a low heat dissipation property, and there is a problem that a semiconductor chip having a large heat generation amount cannot be mounted.
【０００５】本発明はこれら問題点を解消すべくなされ
たものであり、その目的とするところは、封止樹脂によ
って半導体チップを封止することに起因するパッケージ
の変形を小さくすることで、製品の信頼性を向上できる
と共に、パッケージの薄型化を図ることができるＢＧＡ
型の半導体装置を提供しようとするものである。The present invention has been made to solve these problems, and an object of the present invention is to reduce the deformation of the package due to the sealing of the semiconductor chip with a sealing resin to reduce the product. BGA that can improve the reliability of the package and reduce the package thickness
Type semiconductor device.
【０００６】[0006]
【課題を解決するための手段】本発明は上記目的を達成
するため次の構成を備える。すなわち、本発明は、表面
に配線パターンが形成され、裏面に該配線パターンと電
気的に接続された複数の半田ボールが形成された回路基
板の表面側に半導体チップが搭載され、該半導体チップ
の搭載面側が封止樹脂で封止されてなる半導体装置にお
いて、少なくとも前記半導体チップに対向する範囲の大
きさに透孔を形成したプレートが、前記封止樹脂の表面
に前記回路基板と対向して固着されていることを特徴と
する。The present invention has the following constitution in order to achieve the above object. That is, according to the present invention, a semiconductor chip is mounted on the front surface side of a circuit board having a wiring pattern formed on the front surface and a plurality of solder balls electrically connected to the wiring pattern on the back surface, and the semiconductor chip is mounted on the circuit board. In a semiconductor device in which the mounting surface side is sealed with a sealing resin, a plate having a through hole formed at least in a size facing the semiconductor chip is provided on the surface of the sealing resin so as to face the circuit board. It is characterized by being fixed.
【０００７】上記の半導体装置において、前記プレート
が、前記封止樹脂の表面にインサートモールドされて固
着されていることによって、プレートを好適に固着で
き、パッケージの反り等の変形を確実に抑えることがで
きる。In the above semiconductor device, since the plate is insert-molded and fixed to the surface of the sealing resin, the plate can be suitably fixed and deformation such as warpage of the package can be surely suppressed. it can.
【０００８】また、前記プレートの外形が、前記封止樹
脂の表面端縁と略同一の大きさであることによって、特
に角部の変形を好適に抑制できる。Further, since the outer shape of the plate has substantially the same size as the surface edge of the sealing resin, the deformation of the corners can be particularly suitably suppressed.
【０００９】また、前記プレートの透孔が、前記回路基
板に搭載された半導体チップと該回路基板に設けられた
配線パターンとがワイヤボンディングされた範囲に略相
当する大きさであることによって、回路基板とプレート
の間隔を狭めることができ、半導体装置をより薄型化で
きる。Further, since the through hole of the plate has a size substantially corresponding to a range in which the semiconductor chip mounted on the circuit board and the wiring pattern provided on the circuit board are wire-bonded, The distance between the substrate and the plate can be narrowed, and the semiconductor device can be made thinner.
【００１０】また、前記プレートの外周に、前記回路基
板の表面に接近する方向へ鍔部が形成されていることに
よってプレートの剛性を向上させることができ、半導体
装置の変形を抑制することができる。Further, since the flange portion is formed on the outer periphery of the plate in the direction approaching the surface of the circuit board, the rigidity of the plate can be improved and the deformation of the semiconductor device can be suppressed. .
【００１１】また、前記プレートに前記回路基板の表面
に当接する支持突起が形成されていることで、回路基板
とプレートとの間隔を規定どおりに保つことができる。Further, since the plate is provided with the support protrusions that come into contact with the surface of the circuit board, the distance between the circuit board and the plate can be maintained as specified.
【００１２】また、前記プレートに前記封止樹脂と接す
る小孔またはディンプルが形成されていることによっ
て、プレートと封止樹脂との密着性を向上させることが
できる。Further, since the small holes or dimples that are in contact with the sealing resin are formed in the plate, the adhesion between the plate and the sealing resin can be improved.
【００１３】また、前記プレートが金属材からなること
によって、半導体装置の放熱性を向上できる。Further, since the plate is made of a metal material, the heat dissipation of the semiconductor device can be improved.
【００１４】さらに、前記金属材からなるプレートの前
記回路基板と対向または接する部分の表面に電気的絶縁
層が形成されていることで、金属材からなるプレートを
回路基板の表面の任意の位置に接触させて搭載でき、設
計上の制約を少なくすることができる。Further, since the electrically insulating layer is formed on the surface of the portion of the plate made of the metal material facing or in contact with the circuit board, the plate made of the metal material can be placed at any position on the surface of the circuit board. They can be mounted in contact with each other, and design restrictions can be reduced.
【００１５】[0015]
【作用】本発明によれば、ＢＧＡ型の半導体装置におい
て、少なくとも半導体チップに対向する範囲が透孔に形
成されたプレートを、封止樹脂の表面側に回路基板と対
向させて固着しているため、パッケージの反り等の変形
を抑えることができると共に、パッケージの薄型化を図
ることができる。また、プレートを放熱部品として利用
でき、半導体装置の放熱性を向上できる。According to the present invention, in a BGA type semiconductor device, a plate having a through hole formed at least in a region facing a semiconductor chip is fixed to a surface side of a sealing resin so as to face a circuit board. Therefore, deformation such as warpage of the package can be suppressed, and the thickness of the package can be reduced. Further, the plate can be used as a heat dissipation component, and the heat dissipation of the semiconductor device can be improved.
【００１６】[0016]
【実施例】以下、本発明の好適な実施例を添付図面に基
づいて詳細に説明する。図１は本発明に係るＢＧＡ型の
半導体装置の一実施例の構成を示す断面図である。ま
た、図２は図１の実施例の平面図である。１０は回路基
板であり、ガラスエポキシ樹脂等のプリント基板、また
はセラミック基板よりなる。裏面には半球形の半田ボー
ル１２が格子状に並べられて固着されている。表面には
配線パターン１１が形成されており、その配線パターン
１１と半田ボール１２がスルーホール１３によって電気
的に接続されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a sectional view showing the configuration of an embodiment of a BGA type semiconductor device according to the present invention. 2 is a plan view of the embodiment shown in FIG. Reference numeral 10 denotes a circuit board, which is made of a printed board such as glass epoxy resin or a ceramic board. On the back surface, hemispherical solder balls 12 are arranged and fixed in a grid pattern. A wiring pattern 11 is formed on the surface, and the wiring pattern 11 and the solder balls 12 are electrically connected by the through holes 13.
【００１７】この回路基板１０の表面に半導体チップ１
４が搭載され、ワイヤボンディングによるワイヤ１６に
よって半導体チップ１４と回路基板１０の表面に形成さ
れた配線パターン１１とが接続されている。このように
して半導体チップ１４が、ワイヤ１６、配線パターン１
１およびスルーホール１３を介して半田ボール１２に電
気的に接続されている。そして、回路基板１０上に搭載
された半導体チップ１４が、封止樹脂１８によって封止
されている。The semiconductor chip 1 is formed on the surface of the circuit board 10.
4 is mounted, and the semiconductor chip 14 and the wiring pattern 11 formed on the surface of the circuit board 10 are connected by the wire 16 formed by wire bonding. In this way, the semiconductor chip 14 includes the wires 16 and the wiring pattern 1.
1 and the through holes 13 are electrically connected to the solder balls 12. The semiconductor chip 14 mounted on the circuit board 10 is sealed with the sealing resin 18.
【００１８】２０はプレートであり、半導体チップ１４
に対向する部分が透孔２０ａに形成されている。このプ
レート２０は、封止樹脂１８の表面に回路基板１０と対
向させてインサートモールドによって固着されている。
すなわち、封止樹脂１８の表面に、露出するように薄い
プレート２０が配置され、透孔２０ａ内に封止樹脂１８
が充填された状態となっている。このように封止樹脂１
８が充填されて半導体チップ１４が封止されるため、プ
レート２０を半導体チップ１４に干渉しないように回路
基板１０へ近接して配設でき、パッケージを薄型化でき
る。また、インサートモールドによって、プレート２０
が封止樹脂１８と固着されるため、両者の密着性がよ
く、パッケージの変形を防止できる。Reference numeral 20 denotes a plate, which is a semiconductor chip 14
Is formed in the through hole 20a. The plate 20 is fixed to the surface of the sealing resin 18 by insert molding while facing the circuit board 10.
That is, the thin plate 20 is arranged so as to be exposed on the surface of the sealing resin 18, and the sealing resin 18 is provided in the through hole 20a.
Is in a filled state. Thus, the sealing resin 1
Since 8 is filled and the semiconductor chip 14 is sealed, the plate 20 can be disposed close to the circuit board 10 so as not to interfere with the semiconductor chip 14, and the package can be thinned. Moreover, the plate 20 is formed by insert molding.
Is adhered to the sealing resin 18, the two have good adhesion, and the deformation of the package can be prevented.
【００１９】プレート２０は、回路基板１０の材料と同
一素材の物が、熱膨張率および弾性率が同じため望まし
いが、コスト面で有利なアルミニウム板や、ガラスエポ
キシ樹脂板でも良い。プレート２０の厚みは、薄くなく
てはならないが、薄すぎる場合は反り等の変形を抑える
効果が小さくなるため、例えば厚さ数ｍｍ程度の半導体
装置では、プレート２０の厚さは０．２ｍｍ程度が好ま
しい。また、プレート２０としては、銅板あるいはアル
ミニウム板等の剛性があって熱放散性が優れた金属材を
用いれば、パッケージの変形を抑制できると共に放熱性
を向上できるという利点がある。The plate 20 is preferably made of the same material as the material of the circuit board 10 because it has the same coefficient of thermal expansion and elastic modulus, but may be an aluminum plate or a glass epoxy resin plate which is advantageous in terms of cost. The thickness of the plate 20 must be thin, but if it is too thin, the effect of suppressing deformation such as warpage becomes small. Therefore, for example, in a semiconductor device having a thickness of about several mm, the thickness of the plate 20 is about 0.2 mm. Is preferred. Further, if the plate 20 is made of a metal material such as a copper plate or an aluminum plate that has rigidity and excellent heat dissipation, there is an advantage that deformation of the package can be suppressed and heat dissipation can be improved.
【００２０】また、図２に示すようにプレート２０が、
封止樹脂１８の表面全面と略同一外形のプレート状に形
成されている。このようにプレート２０が形成されてい
れば、特に反り等の変形が発生して寸法誤差が大きくな
り易い回路基板１０の角部の変形を防止できる。Further, as shown in FIG. 2, the plate 20 is
It is formed in a plate shape having substantially the same outer shape as the entire surface of the sealing resin 18. If the plate 20 is formed in this way, it is possible to prevent deformation of the corners of the circuit board 10, which are likely to cause deformation such as warpage and cause large dimensional errors.
【００２１】図３は本発明の半導体装置にかかる他の実
施例を示す平面図であり、図４は図３の実施例のＡ−Ａ
断面図である。この実施例においては、プレート２２の
透孔２２ａが、少なくとも回路基板に搭載された半導体
チップ１４、および半導体チップ１４を回路基板１０に
設けられた配線パターンとを電気的に接続するワイヤ１
６がボンディングされた範囲に相当する大きさである。
このようにプレートが形成されていれば、ワイヤ１６と
プレート２２との接触を防げ、回路基板１０とプレート
２２の間隔を狭めることができ、パッケージをより薄型
化できる。FIG. 3 is a plan view showing another embodiment of the semiconductor device of the present invention, and FIG. 4 is an AA of the embodiment of FIG.
FIG. In this embodiment, the through hole 22a of the plate 22 electrically connects at least the semiconductor chip 14 mounted on the circuit board and the wiring pattern provided on the circuit board 10 to the semiconductor chip 14.
6 is a size corresponding to the bonded area.
If the plate is formed in this way, the contact between the wire 16 and the plate 22 can be prevented, the distance between the circuit board 10 and the plate 22 can be narrowed, and the package can be made thinner.
【００２２】図５の実施例では、プレート２４の外周
に、回路基板１０の表面に接近する方向へ鍔部２４ａが
形成されている。これによりプレート２４の剛性を向上
させることができ、パッケージの変形をより好適に抑制
することができる。鍔部２４ａの先端が回路基板１０表
面と接するように鍔部２４ａを成形してもよいが、封止
樹脂が半導体チップ１４を封止する際に流動できるよう
に少なくとも部分的には所定の間隔を開けておくとよ
い。In the embodiment shown in FIG. 5, a flange 24a is formed on the outer periphery of the plate 24 in a direction approaching the surface of the circuit board 10. Thereby, the rigidity of the plate 24 can be improved, and the deformation of the package can be suppressed more preferably. The brim portion 24a may be molded so that the tip of the brim portion 24a is in contact with the surface of the circuit board 10. However, at least a predetermined interval is provided so that the sealing resin can flow when sealing the semiconductor chip 14. It is good to open the.
【００２３】図６は本発明にかかるプレート２６の透孔
の内周面２６ａ形状の一実施例を示す断面図である。こ
の透孔の内周面２６ａは表端面方向へ拡開するように形
成されている。このため、封止樹脂１８が、断面形状と
しては斜面に形成された透孔の内周面２６ａに沿って表
面まで充填され、プレートと封止樹脂とが剥離しないよ
う、その密着性を向上させることができる。なお、透孔
を表端面方向へ拡開するには、上記のように内周面を斜
面とすることに限らず、階段状に拡径してもよい。FIG. 6 is a sectional view showing an embodiment of the shape of the inner peripheral surface 26a of the through hole of the plate 26 according to the present invention. The inner peripheral surface 26a of the through hole is formed so as to widen in the front end surface direction. Therefore, the sealing resin 18 is filled up to the surface along the inner peripheral surface 26a of the through hole formed in the inclined surface as a cross-sectional shape, and the adhesion is improved so that the plate and the sealing resin are not separated. be able to. In order to expand the through hole toward the front end surface, the inner peripheral surface is not limited to the inclined surface as described above, and the diameter may be increased stepwise.
【００２４】図７は図１の実施例の半導体装置をモール
ド成形する金型を示す断面図である。図中の二点鎖線
は、その金型によってモールド成形された半導体装置の
概略の形状を示す。プレート２０は、半導体チップ１４
を樹脂封止する際、インサート部品として封止金型（上
金型２８、下金型３０）によって形成されるキャビティ
３２内の底面上にセットされ、半導体チップ１４が搭載
された回路基板１０と一体に固着されるように、インサ
ートモールドされる。すなわち、この封止金型によれ
ば、半導体チップ１４が下を向いた状態で樹脂封止がな
されるため、プレート２０がキャビティ３２の最下部に
セットされなければならない。このようにプレート２０
を位置させるには、単にプレート２０を下金型３０のキ
ャビティ凹部内に落としておくだけでよく、特別な支持
手段を要せず、容易にインサートモールドすることが可
能である。なお、３４は封止金型のランナー部であり、
３６は封止金型のポット部である。FIG. 7 is a sectional view showing a die for molding the semiconductor device of the embodiment shown in FIG. The two-dot chain line in the figure shows the general shape of the semiconductor device molded by the mold. The plate 20 is a semiconductor chip 14
And the circuit board 10 on which the semiconductor chip 14 is mounted, which is set on the bottom surface inside the cavity 32 formed by the sealing mold (upper mold 28, lower mold 30) as an insert part when the resin is sealed with resin. It is insert-molded so as to be fixed integrally. That is, according to this sealing die, the resin is sealed with the semiconductor chip 14 facing downward, so that the plate 20 must be set at the bottom of the cavity 32. Plate 20
In order to position, the plate 20 may be simply dropped into the cavity concave portion of the lower mold 30, and no special supporting means is required, and insert molding can be easily performed. In addition, 34 is a runner part of the sealing die,
36 is a pot portion of the sealing die.
【００２５】図８の実施例では、プレート３８に回路基
板１０方向に突起して回路基板１０表面に当接する支持
突起３８ａが設けられている。この支持突起３８ａによ
って、回路基板１０とプレート３８との間隔を規定どお
りに保つことができ、寸法精度を向上できる。そして、
上記の実施例ではプレート３８が金属材で形成されてい
るため、プレート３８の表面の少なくとも一部である回
路基板１０と接触する部分は電気的絶縁層３９に形成さ
れている。このように電気的絶縁層３９が形成されるこ
とで、プレート３８を配線パターンとの電気的短絡を回
避して回路基板１０上の配線パターンと接触するように
形成でき、設計上の制約を軽減することができる。電気
的絶縁層としては、たとえばプレート３８がアルミニウ
ム製の場合はアルマイト処理を施して絶縁層としたり、
銅等を用いる場合はポリイミド等の電気的絶縁体をコー
ティングして形成することができる。In the embodiment shown in FIG. 8, the plate 38 is provided with a support protrusion 38a which protrudes toward the circuit board 10 and contacts the surface of the circuit board 10. The support projections 38a can maintain the distance between the circuit board 10 and the plate 38 as specified, and improve the dimensional accuracy. And
In the above-described embodiment, since the plate 38 is made of a metallic material, at least a part of the surface of the plate 38, which is in contact with the circuit board 10, is formed in the electrically insulating layer 39. By thus forming the electrically insulating layer 39, the plate 38 can be formed so as to be in contact with the wiring pattern on the circuit board 10 while avoiding an electrical short circuit with the wiring pattern, thereby reducing design restrictions. can do. As the electrically insulating layer, for example, when the plate 38 is made of aluminum, an alumite treatment is performed to form an insulating layer,
When copper or the like is used, it can be formed by coating an electrical insulator such as polyimide.
【００２６】なお、支持突起３８ａの一部分に絶縁層３
９を形成せず、この部分を基板１０上の配線パターン中
の接地パターンと接続すれば、プレート３８を接地電位
とすることができる。プレート３８を接地電位とすると
電磁遮蔽効果を得ることができるので、半導体チップの
ノイズを半導体装置外部に漏らすことを防止できるし、
半導体装置外部のノイズが半導体チップに悪影響を及ぼ
すことを防止できる。The insulating layer 3 is formed on a part of the support protrusion 38a.
If this portion is connected to the ground pattern in the wiring pattern on the substrate 10 without forming 9, the plate 38 can be set to the ground potential. Since the electromagnetic shielding effect can be obtained by setting the plate 38 to the ground potential, it is possible to prevent the noise of the semiconductor chip from leaking to the outside of the semiconductor device,
It is possible to prevent noise external to the semiconductor device from adversely affecting the semiconductor chip.
【００２７】図９の実施例では、プレート４０に複数の
小孔４１を設けている。これにより、プレート４０と封
止樹脂１８とが剥離しないように密着性を向上できる。
すなわち、小孔４１内に封止樹脂１８が入り込んでモー
ルド成形されるようにし、プレート４０が封止樹脂１８
から剥離しにくくしている。この小孔４１は、図６の実
施例の透孔の内周面２６ａと同様に表端面に向かって拡
開した形状に形成されている。なお、小孔４１を段階状
に拡径する逆止孔形状にすることでプレート４０を封止
樹脂１８から剥離しにくくすることもできる。In the embodiment of FIG. 9, the plate 40 is provided with a plurality of small holes 41. Thereby, the adhesion can be improved so that the plate 40 and the sealing resin 18 are not separated.
That is, the sealing resin 18 enters the small holes 41 to be molded, and the plate 40 is sealed with the sealing resin 18.
It is hard to peel off from. This small hole 41 is formed in a shape that widens toward the front end face, similarly to the inner peripheral surface 26a of the through hole of the embodiment of FIG. The plate 40 can be made difficult to peel off from the sealing resin 18 by forming the small hole 41 into a check hole shape in which the diameter is increased stepwise.
【００２８】また、プレート４０が封止樹脂１８から剥
離しないように密着性を向上するには、封止樹脂１８が
付着する面に予めディンプルを形成したり、付着する面
を粗面に形成したりすればよい。電気的絶縁層として絶
縁樹脂を使用した場合には、たとえば樹脂に銅箔をラミ
ネートした後、銅箔をエッチング除去することによって
粗面にする方法が利用できる。In order to improve the adhesion so that the plate 40 does not peel off from the sealing resin 18, dimples are previously formed on the surface to which the sealing resin 18 is attached, or the surface to be attached is formed to be a rough surface. You can do it. When an insulating resin is used as the electrically insulating layer, for example, a method of laminating a copper foil on the resin and then removing the copper foil by etching to form a rough surface can be used.
【００２９】図１０は半導体装置のさらに他の実施例を
示す。この実施例では回路基板１０上にのせるプレート
４２をその外縁に近い位置でＶ形に折り曲げて支持突起
４４ａを設け、回路基板１０とプレート４２との間に所
定の間隔ができるようにしている。これによってもパッ
ケージを反らせるように働く曲げ力に抗する剛性を、好
適に得ることができる。プレート４２が金属材の場合
は、少なくともプレート４２の回路基板１０と接する部
分に電気的絶縁層を４３を設ける。FIG. 10 shows still another embodiment of the semiconductor device. In this embodiment, the plate 42 placed on the circuit board 10 is bent into a V shape at a position close to the outer edge of the plate 42 to provide support protrusions 44a so that a predetermined space can be provided between the circuit board 10 and the plate 42. . Also by this, it is possible to suitably obtain the rigidity that resists the bending force that acts to warp the package. When the plate 42 is made of a metal material, an electrically insulating layer 43 is provided on at least a portion of the plate 42 that contacts the circuit board 10.
【００３０】また、本発明の半導体装置は、半導体チッ
プ上に液状樹脂を滴下し硬化させて封止するポッティン
グによっても形成することができる。この場合、次の様
にして半導体装置は形成される。図１１に示すように、
半導体チップの搭載された回路基板上に、液状樹脂（封
止樹脂５０）を滴下し、半硬化させる。次に図１２に示
すように、半硬化の封止樹脂５０の表面にプレート５２
を乗せ、樹脂を完全に硬化することによりプレート５２
を固着する。ポッティングは少量多品種の生産に適して
いるが、封止樹脂の表面に凹凸が発生してしまい、外観
上の不都合がある。しかし、ポッティングによる封止樹
脂表面にプレート５２を装着すると、プレート５２によ
りポッティングした封止樹脂表面の凹凸を吸収すること
ができ、封止樹脂５０の形状を均一化することができ
る。」The semiconductor device of the present invention can also be formed by potting in which a liquid resin is dropped on a semiconductor chip, cured, and sealed. In this case, the semiconductor device is formed as follows. As shown in FIG.
A liquid resin (sealing resin 50) is dropped on the circuit board on which the semiconductor chip is mounted, and is semi-cured. Next, as shown in FIG. 12, a plate 52 is formed on the surface of the semi-cured sealing resin 50.
The plate 52 by completely hardening the resin.
To fix. Although potting is suitable for small-lot production of a wide variety of products, unevenness occurs on the surface of the encapsulating resin, which is disadvantageous in appearance. However, when the plate 52 is mounted on the surface of the sealing resin by potting, the unevenness of the surface of the sealing resin potted by the plate 52 can be absorbed, and the shape of the sealing resin 50 can be made uniform. "
【００３１】以上の実施例の半導体装置は回路基板１０
の半導体チップ１４を搭載した側にプレートを設けたこ
とによって、封止樹脂１８が回路基板１０の半導体チッ
プ１４搭載面側に偏在することによりパッケージが反る
等変形することを防止することができる。同時にプレー
トには透孔が設けられているため、回路基板１０とプレ
ートとの間隔を狭めることができ、パッケージを薄型化
できる。また、プレートを熱放射性のよい金属材で形成
することによって、半導体装置の放熱性も向上できる。The semiconductor device according to the above-described embodiments is the circuit board 10.
By providing the plate on the side on which the semiconductor chip 14 is mounted, it is possible to prevent the package 18 from being deformed such as warped due to uneven distribution of the sealing resin 18 on the semiconductor chip 14 mounting surface side of the circuit board 10. . At the same time, since the plate has through holes, the distance between the circuit board 10 and the plate can be narrowed, and the package can be made thin. In addition, the heat dissipation of the semiconductor device can be improved by forming the plate with a metal material having good heat radiation.
【００３２】なお、上記説明ではプレートを設けたこと
による効果としてパッケージの変形防止、薄型化および
パッケージの放熱性の改善について説明したが、プレー
トを設けたことにより、合わせてパッケージの強度を向
上させることができると共に、パッケージの耐湿性を向
上させることもできる。以上、本発明の好適な実施例に
ついて種々述べてきたが、本発明はこの実施例に限定さ
れるものではなく、発明の精神を逸脱しない範囲内でさ
らに多くの改変を施し得るのはもちろんのことである。In the above description, the deformation of the package, the reduction in thickness, and the improvement of the heat dissipation of the package have been described as the effects of the provision of the plate. However, the provision of the plate also improves the strength of the package. It is also possible to improve the moisture resistance of the package. Although various preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and many modifications can be made without departing from the spirit of the invention. That is.
【００３３】[0033]
【発明の効果】本発明にかかる半導体装置によれば、Ｂ
ＧＡ型の半導体装置において、少なくとも半導体チップ
に対向する範囲が透孔に形成されたプレートを、封止樹
脂の表面側に回路基板と対向させてインサートモールド
によって固着している。このため、封止樹脂によって半
導体チップを封止することに起因するパッケージの変形
を小さくすることで、製品の信頼性向上できると共に、
パッケージの薄型化を図ることができるという著効を奏
する。According to the semiconductor device of the present invention, B
In a GA type semiconductor device, a plate in which at least a region facing a semiconductor chip is formed as a through hole is fixed to the front surface side of a sealing resin by an insert mold so as to face a circuit board. Therefore, by reducing the deformation of the package caused by sealing the semiconductor chip with the sealing resin, it is possible to improve the reliability of the product,
A remarkable effect that the package can be made thinner.
【図１】本発明にかかる半導体装置の一実施例を示す断
面図である。FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention.
【図２】図１の実施例の平面図である。2 is a plan view of the embodiment of FIG. 1. FIG.
【図３】本発明にかかる半導体装置の他の実施例を示す
平面図である。FIG. 3 is a plan view showing another embodiment of the semiconductor device according to the present invention.
【図４】図３の実施例のＡ−Ａ断面図である。4 is a cross-sectional view taken along the line AA of the embodiment shown in FIG.
【図５】プレートの外周部に鍔部が形成された実施例を
示す断面図である。FIG. 5 is a cross-sectional view showing an embodiment in which a flange portion is formed on the outer peripheral portion of the plate.
【図６】プレートの透孔の形状にかかる一実施例を示す
断面図である。FIG. 6 is a cross-sectional view showing an example relating to the shape of a through hole of a plate.
【図７】本発明にかかる半導体装置のモールド成形を説
明する断面図である。FIG. 7 is a cross-sectional view illustrating molding of a semiconductor device according to the present invention.
【図８】プレートに支持突起が形成された実施例を示す
断面図である。FIG. 8 is a cross-sectional view showing an example in which a support protrusion is formed on a plate.
【図９】プレートに透孔の他に小孔が形成された実施例
を示す断面図である。FIG. 9 is a sectional view showing an embodiment in which small holes are formed in the plate in addition to the through holes.
【図１０】プレートに支持突起が形成された実施例を示
す断面図である。FIG. 10 is a cross-sectional view showing an example in which a support protrusion is formed on a plate.
【図１１】本発明にかかる半導体装置がポッティングに
よって形成される際の状況を説明する断面図である。FIG. 11 is a cross-sectional view illustrating a situation when the semiconductor device according to the present invention is formed by potting.
【図１２】ポッティングによって形成された本発明にか
かる半導体装置を示す断面図である。FIG. 12 is a cross-sectional view showing a semiconductor device according to the present invention formed by potting.
【図１３】従来の技術を説明する断面図である。FIG. 13 is a cross-sectional view illustrating a conventional technique.
１０ 回路基板 １１ 配線パターン １２ 半田ボール １３ スルーホール １４ 半導体チップ １６ ワイヤ １８ 封止樹脂 ２０、２２、２４、２６、３８、４０、４２ プレート ２０ａ、２２ａ 透孔 ２４ａ 鍔部 ３９、４３ 電気的絶縁層 ３８ａ、４４ａ 支持突起 ４１ 小孔 ５０ 封止樹脂 ５２ プレート 10 Circuit Board 11 Wiring Pattern 12 Solder Ball 13 Through Hole 14 Semiconductor Chip 16 Wire 18 Sealing Resin 20, 22, 24, 26, 38, 40, 42 Plate 20a, 22a Through Hole 24a Collar 39, 43 Electrical Insulation Layer 38a, 44a Support protrusion 41 Small hole 50 Sealing resin 52 Plate
Claims (9)
該配線パターンと電気的に接続された複数の半田ボール
が形成された回路基板の表面側に半導体チップが搭載さ
れ、該半導体チップの搭載面側が封止樹脂で封止されて
なる半導体装置において、 少なくとも前記半導体チップに対向する範囲の大きさに
透孔を形成したプレートが、前記封止樹脂の表面に前記
回路基板と対向して固着されていることを特徴とする半
導体装置。1. A semiconductor chip is mounted on the front surface side of a circuit board having a wiring pattern formed on the front surface and a plurality of solder balls electrically connected to the wiring pattern on the back surface, and the semiconductor chip is mounted. In a semiconductor device in which the surface side is sealed with a sealing resin, a plate having a through hole formed at least in a size facing the semiconductor chip is fixed to the surface of the sealing resin so as to face the circuit board. A semiconductor device characterized by being provided.
インサートモールドされて固着されていることを特徴と
する請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the plate is insert-molded and fixed to the surface of the sealing resin.
表面端縁と略同一の大きさであることを特徴とする請求
項１または２記載の半導体装置。3. The semiconductor device according to claim 1, wherein the outer shape of the plate has substantially the same size as the surface edge of the sealing resin.
搭載された半導体チップと該回路基板に設けられた配線
パターンとがワイヤボンディングされた範囲に略相当す
る大きさであることを特徴とする請求項１、２または３
記載の半導体装置。4. The through hole of the plate has a size substantially corresponding to a range in which a semiconductor chip mounted on the circuit board and a wiring pattern provided on the circuit board are wire-bonded. Claim 1, 2 or 3
The semiconductor device described.
表面に接近する方向へ鍔部が形成されていることを特徴
とする請求項１、２、３または４記載の半導体装置。5. The semiconductor device according to claim 1, wherein a flange is formed on an outer periphery of the plate in a direction approaching a surface of the circuit board.
する支持突起が形成されていることを特徴とする請求項
１、２、３、４または５記載の半導体装置。6. The semiconductor device according to claim 1, wherein the plate is formed with a support protrusion that abuts against the surface of the circuit board.
孔またはディンプルが形成されていることを特徴とする
請求項１、２、３、４、５または６記載の半導体装置。7. The semiconductor device according to claim 1, wherein a small hole or a dimple that contacts the sealing resin is formed on the plate.
徴とする請求項１、２、３、４、５、６または７記載の
半導体装置。8. The semiconductor device according to claim 1, wherein the plate is made of a metal material.
基板と対向または接する部分の表面に電気的絶縁層が形
成されていることを特徴とする請求項８記載の半導体装
置。9. The semiconductor device according to claim 8, wherein an electrically insulating layer is formed on a surface of a portion of the plate made of the metal material that faces or contacts the circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6105290A JPH07321246A (en) | 1994-05-19 | 1994-05-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6105290A JPH07321246A (en) | 1994-05-19 | 1994-05-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07321246A true JPH07321246A (en) | 1995-12-08 |
Family
ID=14403559
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6105290A Pending JPH07321246A (en) | 1994-05-19 | 1994-05-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07321246A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6037656A (en) * | 1996-08-12 | 2000-03-14 | Nec Corporation | Semiconductor integrated circuit device having short signal paths to terminals and process of fabrication thereof |
| US6308938B1 (en) | 1997-09-26 | 2001-10-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device |
| US6818476B2 (en) | 2001-02-23 | 2004-11-16 | Shinko Electric Industries Co., Ltd | Insert-moldable heat spreader, semiconductor device using same, and method for manufacturing such semiconductor device |
| US6921683B2 (en) | 2002-02-25 | 2005-07-26 | Seiko Epson Corporation | Semiconductor device and manufacturing method for the same, circuit board, and electronic device |
| JP2007537589A (en) * | 2004-05-11 | 2007-12-20 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Notched heat slug for integrated circuit device packages |
-
1994
- 1994-05-19 JP JP6105290A patent/JPH07321246A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6037656A (en) * | 1996-08-12 | 2000-03-14 | Nec Corporation | Semiconductor integrated circuit device having short signal paths to terminals and process of fabrication thereof |
| US6308938B1 (en) | 1997-09-26 | 2001-10-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device |
| KR100328370B1 (en) * | 1997-09-26 | 2002-04-17 | 다니구찌 이찌로오, 기타오카 다카시 | Semiconductor integrated circuit device |
| US6818476B2 (en) | 2001-02-23 | 2004-11-16 | Shinko Electric Industries Co., Ltd | Insert-moldable heat spreader, semiconductor device using same, and method for manufacturing such semiconductor device |
| US6921683B2 (en) | 2002-02-25 | 2005-07-26 | Seiko Epson Corporation | Semiconductor device and manufacturing method for the same, circuit board, and electronic device |
| JP2007537589A (en) * | 2004-05-11 | 2007-12-20 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Notched heat slug for integrated circuit device packages |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6624058B1 (en) | Semiconductor device and method for producing the same | |
| US7679172B2 (en) | Semiconductor package without chip carrier and fabrication method thereof | |
| US5739588A (en) | Semiconductor device | |
| US6130477A (en) | Thin enhanced TAB BGA package having improved heat dissipation | |
| US6731015B2 (en) | Super low profile package with stacked dies | |
| US5241133A (en) | Leadless pad array chip carrier | |
| US6215180B1 (en) | Dual-sided heat dissipating structure for integrated circuit package | |
| JP3291368B2 (en) | Structure of ball grid array type semiconductor package | |
| KR19990007268A (en) | Semiconductor devices | |
| EP0563264B1 (en) | Leadless pad array chip carrier | |
| JP2000031343A (en) | Semiconductor device | |
| KR20040037575A (en) | Micro leadless package having oblique etching line | |
| US6819565B2 (en) | Cavity-down ball grid array semiconductor package with heat spreader | |
| JPH07321246A (en) | Semiconductor device | |
| JPH08250625A (en) | Plastic molded type semiconductor device | |
| JP2768315B2 (en) | Semiconductor device | |
| JPH0778921A (en) | Semiconductor device | |
| KR0173930B1 (en) | Ball grid array for lead frame | |
| KR100221918B1 (en) | Chip scale package | |
| KR100459820B1 (en) | Chip scale package and its manufacturing method | |
| KR100258351B1 (en) | Semiconductor Package | |
| KR100760953B1 (en) | Bidirectional semiconductor package with heat sink | |
| KR100426501B1 (en) | manufacturing method of semiconductor package | |
| JPH08213418A (en) | Method for manufacturing semiconductor device and mold used for the method | |
| KR0138296Y1 (en) | Hi-Pin Package |