JPH07321234A - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a memory cell having a small required area which is compatible with a logic process by using a resistance lowering means such as salicide. [Structure] The resistance lowering means of the gate electrode of the transfer transistor and the formation means of the local wiring are common, and the local wiring is arranged on the driving transistor. [Effect] It is possible to provide an on-chip SRAM having high integration and soft error resistance, and a high-performance microprocessor chip.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to a source / drain of an insulated gate field effect transistor type semiconductor device and a low resistance material on the surface of a gate electrode, which is laminated on the gate electrode. The present invention relates to a semiconductor integrated circuit device that provides a static random access memory having local wiring formed by self-alignment and having high integration and soft error resistance, and a manufacturing method thereof.

[0002]

2. Description of the Related Art A conventional semiconductor integrated circuit device relates to an insulated gate field effect transistor (IG) on a silicon substrate.
A low resistance material is formed in a self-aligned manner on the surface of a high-concentration impurity region forming a source / drain of a FET (hereinafter, referred to as a general MIS transistor) and the surface of a gate electrode, thereby increasing the device speed and reducing the number of process steps. A highly integrated static random access memory (hereinafter abbreviated as SRAM) formed by using a so-called salicide process for the purpose of reduction will be described.

FIG. 23 shows a pair of driving MIS transistors Q1 and Q2 and a pair of transfer MIS transistors Q3.
Q4, and a pair of load MIS transistors Q5,
An equivalent circuit of a general SRAM memory cell composed of Q6 is shown. FIG. 24 shows a plan view of the prior art of the SRAM memory cell shown in FIG. In FIG. 24, Q
1, Q2 are n-channel driving MIS transistors, Q
3, Q4 are n-channel transfer MIS transistors, Q
Reference numerals 5 and Q6 denote p-channel load MIS transistors, both of which are formed on the surface of the silicon substrate. Here, the gate electrode 91 of the driving MIS transistor Q1
Is a transfer MIS transistor Q3 including a high-concentration n-type impurity region 84 via local wirings 95, 97, and 99.
Drain (or source), high-concentration n-type impurity region 8
The drain of the driving MIS transistor Q2 composed of 3;
The drains of the load MIS transistors Q6 formed of the high-concentration p-type impurity regions 90 are connected to each other, and drive M
The gate electrode 92 of the IS transistor Q2 has a common high-concentration n-type impurity region 81 via the local wirings 96 and 98.
23 is connected to the drain of the drive MIS transistor Q1 and the drain (or source) of the transfer MIS transistor Q4, and the drain of the load MIS transistor Q5 formed of the high-concentration p-type impurity region 88. Storage node N shown in the circuit
1 and N2, and transfer MIS transistors Q3 and Q4
Common gate electrode 93 forms the word line 55.

Further, as shown in FIG. 24, the opening 1 of the source (or drain) of each of the transfer MIS transistors Q3 and Q4 composed of high-concentration n-type impurity regions 85 and 86.
02 and 103, the first-layer aluminum electrode 106,
107 is connected, and the openings 110 and 111 are further connected.
Through the upper second layer aluminum electrode 112, 1
A data line consisting of 13 is connected. The source regions of the driving MIS transistors Q1 and Q2 formed of the high-concentration n-type impurity regions 80 and 82 have openings 100 and 1 respectively.
The common ground wiring formed of the first-layer aluminum electrode 108 is connected via 01, and the load MIS transistor Q5 formed of the high-concentration p-type impurity regions 87 and 89.
The source region of Q6 is connected to the ground wiring made of the common first-layer aluminum electrode 109 through the openings 104 and 105, respectively, and supplies a predetermined potential to all the memory cells.

Next, a method for connecting a high-concentration impurity region and a gate electrode by using a local wiring is shown in FIG.
A detailed description will be given in the order of steps with reference to FIGS. 25A to 25E show Y in FIG.
The forming process up to the local wiring is shown for the cross section of the −Y ′ portion.

First, as shown in FIG. 25A, after forming a p-type well 114 and an n-type well in a silicon substrate (only the p-type well is shown in the figure), a thickness of 400 to
Field oxide film 115 of 500 nm and thickness 10
nm gate oxide film 116 is formed, and a 200 nm-thick polycrystalline silicon film is patterned into a predetermined shape by photolithography and dry etching to form a gate electrode 117, and ion implantation and predetermined annealing are performed to increase the source / drain height. A concentration n-type impurity region 118 is formed.

Next, as shown in FIG.
A silicon oxide film of about 300 nm is deposited on the silicon substrate by the CVD method, the silicon oxide film is etched back by anisotropic dry etching, and the spacer insulating film 119 of the silicon oxide film is formed on the side wall of the gate electrode.

Next, as shown in FIG. 25 (c), a titanium film 120 having a thickness of 100 nm is deposited on the silicon substrate 1 by sputtering, and then an amorphous silicon film 122 is formed to 500 as shown in FIG. 25 (d). Deposition is carried out at a temperature of .degree. C., and the photoresist 121 is used as a mask to perform patterning in the shape of local wiring.

Then, as shown in FIG.
By subjecting titanium 120 to the high-concentration n-type impurity region 118, the polycrystalline silicon film 117, and the amorphous silicon film 122 by performing a heat treatment at about ° C, the high-concentration n-type impurity amount region 118 and the high-concentration n-type impurity region 118 A titanium silicide film 123 is formed on the surface of the crystalline silicon film 117, the amorphous silicon film is replaced with the titanium silicide film 123, and the gate electrode 117 and the high-concentration n-type impurity region 118 can be connected at a desired portion. . The unreacted titanium film is removed with hydrogen peroxide solution. Although not shown in the formation process diagram of FIG. 25, the high-concentration p-type impurity region of the p-channel MIS transistor can be similarly connected to the gate electrode at the desired portion.

The local wiring formed by utilizing the salicidation described above is, for example, IEDM Tec.
hndial Digest, Dec. 1984,
pp. 118-121 and IEDM Technic
al Digest, Dec. 1985, pp.
590-593, and according to the conventional example, MI
A local wiring of a titanium silicide film or a titanium nitride film can be formed in self-alignment with the source / drain region of the S transistor and the gate electrode.

[0011]

In the conventional SRAM cell using the local wiring, the titanium silicide film connecting the gate electrode of the MIS transistor and the high-concentration impurity region is always in contact with the gate electrode. The local wiring could not be used as a three-dimensional wiring extending over the MIS transistor. Therefore, the local interconnection cannot be used to form the cross-connection of the flip-flop portion of the SRAM memory cell, and therefore, in the conventional SRAM cell, the flip-flop is formed by the high-concentration impurity region in the silicon substrate and the gate electrode of the MIS transistor. Since the cross connection of the circuits was formed, an extra area for mask alignment with the isolation region and the gate electrode was required, so that the memory cell area could not be further reduced.

When the salicide technique is not used, that is, when the resistance of the gate electrode and the source / drain regions are individually reduced, a known self-alignment technique can be used to form a high-density local wiring, but the resistance is low. There is a problem in that the number of process steps for forming the semiconductor device and the number of process steps for forming the local wiring increase.

Further, when an α ray generated when a radioactive element such as uranium or thorium contained in a small amount in a packaging material or a resin material used for sealing a memory chip is disintegrated into a memory cell, α A pair of electrons and holes are generated along the range of the line, forming a storage node pn
It mixes in the junction and changes the potential of the storage node, and as a result, the information in the memory cell is destroyed. This phenomenon is known as a soft error. In the conventional SRAM, since the area of the memory cell is large, the capacitance value of the storage node itself including the pn junction capacitance and the gate capacitance is large, and the charge enough to compensate for the charge loss due to α-rays can be stored in the storage node. However, when the memory cell area is miniaturized, the amount of charge that can be stored in the storage node is also reduced, and there is a problem that the resistance of the memory cell to α-ray irradiation deteriorates.

A first object of the present invention is a semiconductor integrated circuit device in which the high-concentration impurity regions of the source / drain of a MIS transistor and the gate electrode have a low resistance.
S (Complementary MOS) and Bi-C
Another object of the present invention is to provide a semiconductor integrated circuit device having high density local wiring in a memory cell of a static random access memory in addition to a MOS circuit.

A second object of the present invention is to provide a semiconductor integrated circuit device having a highly reliable static random access memory having high soft error resistance and good data stability at low voltage.

[0016]

The first object is to provide a first impurity region on the surface of a semiconductor substrate, a first conductive film and a second conductive film formed in the same layer via a first insulating film. A plurality of fourth conductive films are formed through the second insulating film so that at least a part of the conductive film and the second conductive film overlap each other.
A part of the second conductive film other than the overlapping part of the first conductive film and the fourth conductive film on the conductive film of
The third conductive film having a low resistance is simultaneously formed by a means including at least the method for forming a conductive film, and one of the fourth conductive films is insulated from the gate electrode of one driving MIS transistor, and the other end of the fourth conductive film is formed. It is achieved by connecting to the gate electrode of the driving MIS transistor.

Further, the second object of the present invention can be achieved by forming a capacitive element between the gate electrode of the driving MIS transistor of the static random access memory cell and the local wiring.

[0018]

The fourth conductive film forms cross-connections of the flip-flop circuits in the memory cell, and the high-density local wiring makes it possible to miniaturize the memory cell. Further, the above-mentioned capacitive element supplies electric charge to the storage node of the memory cell, and it is possible to prevent the electron-hole pair generated when the memory cell is irradiated with α-ray from changing the potential of the storage node, and it is possible to prevent the soft error. Can be increased.

[0019]

EXAMPLES The present invention will be described in detail below with reference to examples.

<Embodiment 1> In this embodiment, the present invention is applied to CMIS.
(Complimentary MIS) SRA
This is applied to the M cell. 1 and 2 are plan views showing a 1-bit portion of this embodiment.
Shows a cross-sectional structure taken along line YY 'of FIG. 1 is a plan view showing an n-channel driving MIS transistor, a transfer MIS transistor, and a p-channel load MIS transistor formed on the surface of a silicon substrate, and FIG. 2 is a plan view showing two layers of electrode wiring. It is a figure. The equivalent circuit diagram of the memory cell is the same as that shown in FIG. 23. A pair of driving MIS transistors Q1 and Q2 and a pair of transfer MIS transistors Q3 and Q4 each having one gate cross-connected to the other drain are provided. And a pair of load MIS transistors Q5 and Q6 are connected to the storage nodes N1 and N.
2 are connected to each.

In FIG. 1, the drain of the driving MIS transistor Q1 and the source (or drain) of the transfer MIS transistor Q3 have a common high concentration n-type impurity region 2.
The drain of the drive MIS transistor Q2 and the drain (or source) of the transfer MIS transistor Q4 are formed of a common high-concentration n-type impurity region 5. Also,
The common gate electrode 13 of the driving MIS transistor Q1 and the load MIS transistor Q5 is connected to the local wiring 20 through the opening 16, and further, the high-concentration n-type impurity region 5 and the opening are provided through the opening 15. High concentration p which becomes the drain of the load MIS transistor Q6 via 17
It is connected to the type impurity region 10. Similarly, for driving M
IS transistor Q2 and load MIS transistor Q6
Common gate electrode 14 is connected to the local wiring 19 through the opening 16, and further has a high concentration n-type impurity region 2 through the opening 15 and a load MI through the opening 17.
It is connected to the high-concentration p-type impurity region 8 serving as the drain of the S transistor Q5. In this way, the storage nodes N1 and N2 shown in the equivalent circuit of the static random access memory cell of FIG. 23 are formed respectively.

On the other hand, transfer MIS transistors Q3 and Q
The common gate electrode 11 of 4 is the word line 5 in FIG.
It is 5. The gate electrode 12 is of a transfer MIS transistor of an adjacent cell.

Further, as shown in FIG. 2, the first layer of aluminum is formed in the openings (23, 24) of the sources (or drains) of the transfer MIS transistors Q3, Q4 composed of the high-concentration n-type impurity regions 3, 6. The electrodes 27 and 28 are connected to each other, and further the data lines formed of the upper second aluminum electrodes 33 and 34 are connected through the openings 31 and 32. Further, in the source regions of the driving MIS transistors Q1 and Q2 composed of the high-concentration n-type impurity regions 1 and 4 in FIG. 1, a common first-layer aluminum electrode as shown in FIG. 2 is provided through the openings 21 and 22. The ground wiring 29 is connected.

Further, the high-concentration p-type impurity regions 7 and 9 shown in FIG.
2 are connected to the source regions of the load MIS transistors Q5 and Q6, respectively, through the openings 25 and 26, respectively, and are connected to the common first-layer aluminum electrode 30 as shown in FIG. A predetermined potential is supplied to the memory cell.

Next, the structure of the local wiring will be described with reference to the sectional view of FIG. FIG. 3 is a sectional view of the SRAM cell taken along the line YY ′ of FIG. In the figure,
The n-type silicon substrate 35 has a p-well 36 and an n-well 37 each having a depth of 2 μm, a field oxide film 38 having a thickness of 400 nm, and a gate oxide film 3 having a thickness of 10 nm.
9 is formed. Gate electrodes 11 and 12 of transfer MIS transistor, gate electrode 13 of drive MIS transistor, gate electrode 14 of load MIS transistor
Each is made of a polycrystalline silicon film having a thickness of 200 nm. The high-concentration n-type impurity region 2 is a common drain (or source) of the driving MIS transistor and the transfer MIS transistor, and the high-concentration n-type impurity region 3 is a common drain (or source) of the transfer MIS transistor. And the high-concentration p-type impurity region 10 is the load MIS.
This is the drain of the transistor.

The surfaces of the gate electrodes 11 and 12 of the transfer MIS transistor and a part of the gate electrode 14 of the drive MIS transistor, and the high concentration n.
A titanium silicide film 42 having a thickness of 50 nm is formed on the entire surface or a part of the type impurity regions 2 and 3 and the high-concentration p-type impurity region 10 by a so-called salicide technique to reduce the resistance. Further, the titanium silicide film 4 on the high-concentration n-type impurity region 2 and the high-concentration p-type impurity region 10
Reference numeral 2 is a titanium silicide film 42 also formed on the silicon oxide film 41, which are automatically connected to each other. In addition, the titanium silicide film 4 on the high-concentration n-type impurity region 3
A contact hole is opened in the silicon oxide film 43 on 2 and the aluminum electrode 27 of the first layer is connected.

Next, the manufacturing process of this embodiment will be described with reference to FIGS. 4 (a) to 6 (b). 4 (a) to 6
1B shows a cross section taken along the line YY 'in the plan view of FIG.

First, the p-type well 36 and the n-type well 37 having an impurity concentration of about 1 × 10 ¹⁶ / cm ² and a depth of 1 μm are formed in the n-type silicon substrate 35 having a specific resistance of about 10 Ωcm by ion implantation and thermal diffusion. Then, a silicon oxide film (field oxide film 38) for element isolation having a thickness of 400 nm is formed by a known selective oxidation method, and then MIS is formed.
A gate oxide film 42 having a thickness of about 10 nm is formed in a portion which becomes an active region of the transistor. Here, when the field oxide film 38 is formed, a channel stopper layer for preventing n inversion is usually formed under the field oxide film in the p-type well 36, but a drawing omitting this is used here. The channel stopper layer may be formed by the ion implantation method after forming the field oxide film. Further, the impurity concentration distribution in the well may be such that the impurity concentration increases in the depth direction, and in this case, the ion implantation for forming the p well can be performed after forming the field oxide film. Further, in this case, the ion implantation energy may be of multiple types. Next, ion implantation for adjusting the threshold voltage of the MOS transistor is performed. As the ion implantation, for example, BF ₂
Ions are about 2 × 10 ¹² / cm at an energy of 40 keV
A driving amount of ² is appropriate. If the ion implantation for adjusting the threshold voltage is performed before the gate oxidation step, damage or contamination of the gate oxide film in the ion implantation step can be prevented. [FIG. 4 (a)] Next, as shown in FIG. 4 (b), for example, a polycrystalline silicon film having a thickness of 200 nm is formed by low pressure chemical vapor deposition (LPCVD).
The polycrystalline silicon film is doped with impurities to reduce the resistance. As an impurity doping method, for example, an n-type impurity such as phosphorus is introduced by vapor phase diffusion. Subsequently, the polycrystalline silicon film is processed into patterns of the gate electrodes 11 to 14 by photolithography and dry etching. Then, using these gate electrode and photoresist as an ion implantation mask, an n channel MIS is formed.
The n-type impurity ions such as arsenic in ejection amount of the transistor region, for example, about 2 × 10 ¹⁵ / cm ² ion implantation, p-type, such as boron, in applying amount 2 × 10 about ¹⁵ / cm ^2, for example, in the p-channel region Impurity ions are implanted and annealed in a nitrogen atmosphere at 850 ° C. to activate the impurity ions, and the high-concentration n-type impurity regions 2 and 3 and the high-concentration p-type impurity region 10 having a depth of about 0.1 μm are formed. Form. Although not described in this embodiment, a so-called LDD (Lightl) in which a low-concentration n-type impurity region is provided in the source / drain of the MOS transistor in order to prevent deterioration in long-term reliability of the MOS transistor.
(y Doped Drain) structure may be used. The method of adding impurities to the polycrystalline silicon film of the gate electrode may be a method of implanting ions at the time of forming the source / drain or a method of introducing it at the time of forming the polycrystalline silicon film (doped polysilicon). [FIG. 4 (b)] Next, a silicon oxide film having a thickness of about 150 nm is deposited by the LPCVD method by thermal decomposition of monosilane gas, and then etched back by anisotropic dry etching to form spacer insulation on the sidewalls of the gate electrodes 11-14. A film 40 is formed to expose the upper portion of the gate electrode and the high concentration impurity region on the surface of the silicon substrate. Then, a silicon oxide film 41 having a thickness of about 30 nm is deposited by the same LPCVD method, and subsequently an amorphous silicon film 45 having a thickness of about 50 nm is deposited on the silicon oxide film 41 at a temperature of about 520 ° C. by the LPCVD method. To do. Next, the amorphous silicon film 45 is patterned into the shape of local wiring by photolithography and dry etching. The amorphous silicon film 45 may be a polycrystalline silicon film. [FIG. 5 (a)] Next, using the photoresist 46 as a mask, openings are formed in the silicon oxide film 41 by dry etching [15-FIG.
18] is formed. Here, although the amorphous silicon 45 is partially exposed in the opening, the silicon oxide film 41 in that portion is not dry-etched. [FIG. 5B] Next, a titanium film having a thickness of 50 nm is deposited on the entire surface by a sputtering method. [FIG. 5C] Next, heat treatment is performed in a nitrogen atmosphere to expose the exposed high concentration n-type impurity regions 2 and 3 and high concentration p-type impurity region 10.
A titanium silicide film 42 is formed on the exposed gate electrodes 11, 12, and 14 and the exposed amorphous silicon film 45. Unreacted titanium is removed with hydrogen peroxide solution or the like. During the formation of titanium silicide, the titanium silicide film 42 on the silicon substrate rises up the step of the silicon oxide film 41 by heat treatment so as to come into contact with the titanium silicide film 42 formed by reacting with the amorphous silicon film 45. Different heat treatment conditions are used. At this time, the titanium silicide film 42 and the gate electrode 13 are insulated by the silicon oxide film 41. Then, the titanium silicide film 42 is annealed in a nitrogen atmosphere at 800 ° C. to reduce the resistance of the titanium silicide film 42. [FIG. 6A] Next, a silicon oxide film 43 is deposited on the titanium silicide film 42, and the openings 21 to 26 (not shown in FIG. 6) shown in FIG. 1 are formed by photolithography and dry etching. After opening, the first layer aluminum electrodes 27, 29, 3 are formed by photolithography and dry etching.
Pattern 0. It is desirable to use a low temperature for forming the silicon oxide film 42 so that the composition of the titanium silicide film is not affected. [FIG. 6B] Although only the memory cell has been described in the present embodiment,
For the source / drain and the gate electrode of the CMIS transistor group around the memory cell, the salicidation can be applied by etching the silicon oxide film 41 at a desired portion like the word line of the memory cell.
Furthermore, although titanium silicide is described in the present embodiment, a material such as cobalt silicide which easily rises on the oxide film can be used. In addition, known compounds of refractory metal such as platinum silicide, nickel silicide, tungsten silicide, tantalum silicide, and silicon can also be used.

Furthermore, a refractory metal capable of selectively growing on the silicon surface, such as tungsten, can be directly grown on the silicon substrate, the gate electrode, or the amorphous silicon film. In this case, the growth conditions for tungsten include a CVD method using a tungsten hexafluoride gas.

According to this embodiment, since titanium salicide on the silicon substrate and the gate electrode can be formed simultaneously and the local wiring of the laminated structure can be formed at the same time, the source / drain, and the local drain can be formed without significantly increasing the number of steps. It is possible to reduce the resistance of the gate electrode, and by using the local wiring of the laminated structure at the cross connection portion of the memory cells, it is possible to reduce the memory cell area at the same time. Further, according to the present embodiment, the local wiring connected to the high-concentration n-type impurity region of the drain is formed on the drain end of the driving MIS transistor and has the same potential as the drain. When the LDD structure is adopted for the MIS transistor, it is possible to suppress the deterioration of the driving ability due to the LDD layer by the fringe electric field of the local wiring, and it is possible to provide a memory cell which is stable in operation and has excellent noise characteristics.

<Embodiment 2> This embodiment relates to a method for connecting a local wiring and a silicon substrate. FIG. 7 is a sectional structure of the SRAM memory cell according to the present embodiment, which is an enlarged view of the local wiring portion in the sectional view along the line AA ′ shown in FIG. 5B. The process up to forming the MIS transistor on the silicon substrate is the same as the process up to FIG. 5B of the first embodiment. In FIG. 7, a high density n-type impurity region 2 exposed in the opening of the silicon oxide film 41 and the gate electrode 14 of the driving MIS transistor are selectively grown to grow polycrystalline silicon, thereby patterning a local wiring pattern. Connection is made to the crystalline silicon film 45 by self-alignment. As a means for selectively growing polycrystalline silicon, a film is formed by LPCVD using dichlorosilane and hydrogen chloride gas at a temperature of 750 ° C to 800 ° C. Also in this case, the polycrystalline silicon film is selectively grown also on the source / drain of the CMIS transistor of the peripheral circuit other than the memory cell group, and on the gate electrode. The source / drain and the gate electrode will not be short-circuited if controlled to a level difference. Further, although the polycrystalline silicon film grows on the amorphous silicon film 45 in the above manufacturing method,
It is omitted in the figure. The subsequent steps may be exactly the same as those of FIG.

According to this embodiment, the silicon substrate and the gate electrode can be easily connected to the local wiring. Furthermore, in the peripheral CMIS transistor, polycrystalline silicon grows on the source / drain,
This polycrystalline silicon film serves as a supply source of silicon at the time of forming silicide, and silicon in the high concentration impurity region is not consumed by the silicidation reaction. as a result,
It is also possible to reduce the leak current at the pn junction.

<Embodiment 3> This embodiment relates to a method for connecting a local wiring and a silicon substrate, and relates to a method different from the embodiment 2. FIG. 8 is a sectional structure of the SRAM memory cell according to the present embodiment, which is an enlarged view of only the local wiring portion in the sectional view shown in FIG. The process up to forming the MIS transistor on the silicon substrate is the first embodiment.
Is the same as the process up to FIG. In FIG. 5B, after exposing the opening of the silicon oxide film 41, 5
As shown in FIG. 8, high-concentration n-type impurity region 2 is formed by depositing 0 nm of amorphous silicon on the entire surface by LPCVD and then etching back by dry etching.
Further, a sidewall 49 of amorphous silicon is formed on the sidewalls of the silicon oxide film 41 and the amorphous silicon film 45 in the opening of the gate electrode 14 of the driving MIS transistor to form the amorphous silicon film 45 of the local wiring pattern. High concentration n
The type impurity region 2 and the gate electrode 14 are connected. In this case, the source / drain of the MIS transistor,
In addition, the gate electrode is etched back by etching, but it is desirable to appropriately control the etching amount so as not to cause a problem. The subsequent steps may be exactly the same as those of FIG.

According to this embodiment, the silicon substrate and the gate electrode can be easily connected to the local wiring.

<Embodiment 4> This embodiment relates to a method for connecting a local wiring and a silicon substrate, and relates to a method different from the embodiments 2 and 3. FIG. 9 shows the SRA according to this embodiment.
FIG. 2 is an enlarged view showing only a local wiring portion in the sectional view shown in FIG. 1 in the sectional structure of the M memory cell. The process up to forming the MIS transistor on the silicon substrate is the same as the process up to FIG. 5B of the first embodiment. After forming the opening to the silicon oxide film 41 in FIG. 5B, the photoresist 46 used when forming the opening is left as it is and exposed to the opening of the silicon oxide film 41 as shown in FIG. Amorphous silicon film 4
The silicon oxide film 41 under 5 is side-etched. Wet etching using a hydrofluoric acid aqueous solution is suitable as the side etching method. The subsequent steps may be exactly the same as those of FIG.

According to this embodiment, the silicon substrate, the gate electrode and the local wiring can be easily connected.

<Embodiment 5> This embodiment is the SRA of Embodiment 1.
The present invention relates to a capacitive element using a gate electrode and a local wiring in an M cell. FIG. 10 shows S according to this embodiment.
3 is a cross-sectional view of a RAM memory cell. FIG. In the figure, a thickness of 2 is formed on the gate electrode 13 of the driving MIS transistor.
A 0 nm silicon nitride film 50 is deposited by the LPCVD method, and a titanium silicide film 42 of a local wiring is formed on the nitride film 50. Therefore, the gate electrode 13, the nitride film 50, and the titanium silicide film 42 form a capacitive element connected between the storage nodes.

Although the insulating film of the capacitive element is the silicon nitride film in this embodiment, it may be a composite film of the silicon nitride film and the silicon oxide film. Further, an insulating film material having a high dielectric constant such as tantalum pentoxide can also be used.

Next, a plan view of the memory cell will be described with reference to FIG. In FIG. 11, the area of the electrode is widened in order to increase the capacitance of the capacitance element of the storage node. In FIG. 11, a titanium silicide film 53 of a local wiring is connected to the high-concentration n-type impurity region 2 of the storage node, and a capacitive element is formed between the high-concentration n-type impurity region 2 and the lower gate electrode 51 connected to the opposite storage node. Has been formed. On the other hand, the high-concentration n-type impurity region 5 which is the opposite storage node is connected with the titanium silicide film 54 of the local wiring, and the lower gate electrode 5 connected to the storage node.
2 and a capacitive element are formed between the two. By doing as described above, two capacitance elements composed of the gate electrode of the driving MIS transistor and the laminated titanium silicide film are provided between the storage nodes of the SRAM, as shown in C1 and C2 of FIG. Can be connected in parallel.

According to this embodiment, the number of manufacturing steps is not increased, and the memory cell area is not increased.
Since the capacitor can be formed between the storage nodes of the RAM, the amount of charge accumulated in the storage node can be efficiently increased, and a malfunction of the memory cell which occurs when the memory cell is irradiated with α rays can be prevented. be able to.

<Embodiment 6> This embodiment is the SRA of Embodiment 1.
The present invention relates to a method for forming a contact hole in an M cell. FIG. 13 is a plan view of the SRAM memory cell according to this embodiment. In the figure, openings 58 and 59 are opened on the high-concentration n-type impurity regions 1 and 4 of the source region of the driving MIS transistor, and the titanium silicide film described in the first embodiment is formed. Similarly,
Openings 60 and 61 are formed on the high-concentration p-type impurity regions 7 and 9 of the source region of the load MIS transistor, and the titanium silicide film 42 described in Embodiment 1 with reference to FIG.
Are formed. In addition, in FIG.
Structures other than 61 are the same as those in FIG. 1 of the first embodiment, and therefore description thereof is omitted here.

Also. When this embodiment is applied to the fifth embodiment, the silicon nitride film 50 used as the insulating film of the capacitive element shown in FIG. 10 when forming the openings 58 to 61.
Is etched in the dry etching process of the opening, so that the silicon nitride film 50 is formed in the portions where the contact holes on the high concentration n-type impurity regions 1 and 4 and the high concentration p-type impurity regions 7 and 9 are formed. It does not survive.

According to the present embodiment, titanium silicide is formed in all the openings 21 to 26 for connecting the first-layer aluminum electrode to the high-concentration impurity region on the silicon substrate in the salicidation process. Because it is formed
The cleaning process performed when depositing the first-layer aluminum electrode is facilitated. Examples of this cleaning process include sputter cleaning with argon gas. In addition, in the portion where the contact hole is formed,
Since the silicon nitride film forming the capacitive element is removed, it is possible to prevent disconnection of the aluminum wiring in the contact hole.

<Embodiment 7> This embodiment relates to a local wiring having a polycide structure. FIG. 14 is a sectional view of the SRAM cell taken along line YY ′ of FIG. 1 in the first embodiment. In the figure, an n-type silicon substrate 35 has a p-well 36 and an n-well 37 each having a depth of 2 μm, a field oxide film 38 having a thickness of 400 nm, and a thickness of 1
A 0 nm gate oxide film 39 is formed. Transfer M
Gate electrodes 11 and 12 of OS transistor, drive MOS
The gate electrode 13 of the transistor and the gate electrode 14 of the load MOS transistor are both made of a polycrystalline silicon film having a thickness of 200 nm. In addition, the high concentration n-type impurity region 2
Is a common drain (or source) of the driving MOS transistor and the transfer MOS transistor, the high-concentration n-type impurity region 3 is a common drain (or source) of the transfer MOS transistor, and the high-concentration p-type impurity region 1
Reference numeral 0 is the drain of the load MOS transistor.

The surface of the gate electrodes 11 and 12 of the transfer MOS transistor and a part of the gate electrode 14 of the drive MOS transistor, and the high concentration n.
A titanium silicide film 42 having a thickness of 50 nm is formed on the entire surface or a part of the type impurity regions 2 and 3 and the high-concentration p-type impurity region 10 by a so-called salicide technique to reduce the resistance. Further, the local wiring is made of a composite film (polycide film) of a polycrystalline silicon film 62 and a titanium silicide film 42 formed on the upper portion thereof by the salicide process, and has a high concentration n-type impurity region 2 and a high concentration p-type impurity region 10. The upper titanium silicide film 42 is automatically connected to each other by the titanium silicide film 42 formed on the polycrystalline silicon film 62. Note that the methods of Examples 2 to 4 can be applied to the method of connecting the local wiring to the silicon substrate or the gate electrode. Furthermore, the present embodiment can be applied to the structure for forming the capacitive element of the fifth embodiment. At that time, it is preferable to add impurities to the polycrystalline silicon film 62. Particularly, since boron has a smaller diffusion rate in titanium silicide than arsenic or phosphorus, a high concentration in the silicon substrate is obtained. It is possible to suppress an increase in contact resistance between the impurity region and the local wiring. In this case, as a method of introducing impurities, for example, by ion implantation immediately after the deposition of the polycrystalline silicon film 62, 2
Ion implantation of BF ₂ is performed with an acceleration energy of 5 keV and an implantation amount of 5 × 10 ¹⁵ / cm ² . Note that the activation of the impurities can also serve as a heat step when forming the silicide layer.

Further, the inside of the polycrystalline silicon film 62 may be divided into a region to which an n-type impurity is added and a region to which a p-type impurity is added. In this method, ion implantation may be performed using a photoresist as a mask. In this case, the polycrystalline silicon film 62 added with an n-type impurity is connected to the high-concentration n-type impurity region in the silicon substrate, and the p-type impurity is included in the high-concentration p-type impurity region in the silicon substrate. It is desirable that the polycrystalline silicon film 62 added with is connected.

As a method of manufacturing the above local wiring, a thickness of 150 nm is used in place of the amorphous silicon film 41 when forming the amorphous silicon film 45 shown in FIG.
A polycrystalline silicon film having a certain degree may be used. Although titanium is used as the material for the salicide reaction in this embodiment, a known compound of refractory metal such as cobalt silicide, platinum silicide, nickel silicide, tungsten silicide, tantalum silicide and silicon can also be used. Further, a composite film of the refractory metal and the polycrystalline silicon film may be used.

According to this embodiment, the mechanical stress applied to the underlying silicon oxide film 41 when forming the titanium silicide of the local wiring can be relaxed by the polycrystalline silicon film 62, and the dielectric breakdown of the silicon oxide film 41 can be achieved. It is possible to prevent an increase in leak current of the oxide film. In particular, Example 5
Highly reliable SR when applied to the formation of capacitive elements
AM can be provided.

<Embodiment 8> This embodiment relates to a method for forming a local wiring. FIG. 15 is a plan view of this embodiment. In the figure, a region 63 to which a high concentration of oxygen is added is formed in a part of the local wirings 19 and 20. As a method for adding oxygen, a known method such as an ion implantation method can be used. The region to which a high concentration of oxygen is added acts to suppress mutual diffusion of n-type impurities and p-type impurities in the local wiring. In FIG. 15, the structure other than the local wiring is the same as that of the first embodiment shown in FIG.

According to this embodiment, the contact resistance between the high-concentration impurity region in the silicon substrate and the local wiring is increased, and the characteristics such as the threshold voltage and the drain current of the driving MOS transistor are changed and dispersed. Can be suppressed.

<Embodiment 9> This embodiment relates to an aluminum wiring in the SRAM memory cell of the first embodiment. FIG. 16 is a plan view of the SRAM cell according to the present embodiment and shows the aluminum wiring portion. The MOS transistor portion is exactly the same as that of the first embodiment. In FIG. 16, the aluminum electrode 29 of the first layer of the ground wiring and the aluminum electrode 3 of the first layer of the power wiring
The aluminum electrode 64 of the first layer is formed between 0. The aluminum electrode 64 short-circuits the word line divided for each memory mat.

According to the present embodiment, the resistance of the word line can be substantially reduced, so that a high speed SRAM can be provided.

<Embodiment 10> This embodiment is the CM of Embodiment 1.
The present invention relates to a semiconductor integrated circuit device in which an SRAM using an OS transistor and a bipolar transistor are formed on the same semiconductor substrate. 17 (a) to 18 (c) are sectional views of the manufacturing process of this embodiment showing the bipolar element and the CMOS transistor portion, and the SRAM memory cell portion is omitted. Hereinafter, FIG. 17 (a)
This embodiment will be described in the order of manufacturing steps with reference to FIG.

First, a known self-alignment technique is used to form an n-type buried layer 66 by diffusion of antimony on the p-type silicon substrate 65 and a p-type buried layer 67 by ion implantation of boron and annealing. As antimony diffusion conditions, for example, about 1175 ° C. for about 30 minutes, and as boron ion implantation conditions, an acceleration energy of 50 keV and a dose amount of 7 × 10 ¹² / cm ² are suitable. Then, the thickness 1 formed by epitaxial growth
An n well 36 and a p well 37 are formed in a μm silicon layer, and a field oxide film 38 having a thickness of 400 nm is further formed.
To form. The n-well 36 is the n-type buried layer 6
6 and the p well 37 is formed on the p type buried layer 67 by the same method as in the first embodiment. [FIG. 17 (a)] Next, as in the first embodiment, the gate oxide film 3 having a thickness of 10 nm is formed.
After forming 9, the polycrystalline silicon film having a thickness of 200 nm is deposited by the LPCVD method, and the gate electrode 72 is patterned. Then, using the photoresist as a mask, phosphorus ion implantation is performed, and the bipolar collector lead-out portion 6
8 is formed. Similarly, high-concentration n-type impurity regions 70 are simultaneously formed in the source / drain of the n-channel MOS transistor and the collector of the bipolar transistor by ion implantation of arsenic. Further, in the same manner, the high-concentration p-type impurity amount region 71 of the source / drain portion of the p-channel MOS transistor and the high-concentration p-type impurity region 69 of the base extraction portion of the bipolar transistor are simultaneously formed by ion implantation of BF2. The conditions of these ion implantations may be the same as in the first embodiment. [FIG. 17 (b)] Next, a p-type impurity region 73 is formed in a portion serving as the base of the bipolar transistor by ion implantation of boron and predetermined annealing using a photoresist as a mask. The conditions for ion implantation are: BF2 ion implantation, acceleration energy of 50 keV, and implantation amount of 2 × 10 ^14.
/ Cm ² is used. Then, after depositing a silicon oxide film 41 with a thickness of 50 nm by the LPCVD method, the silicon oxide film 41 in the portion which will become the emitter of the bipolar transistor is removed by dry etching using a photoresist mask. [FIG. 17C] Next, the polycrystalline silicon film 62 having a thickness of 200 nm is LP-coated.
A high-concentration n-type impurity region 74 of the emitter layer is formed by depositing it by the CVD method and reducing the resistance by ion implantation of arsenic and predetermined annealing. Ion implantation conditions are, for example, implantation energy of 80 keV, 1 ×
The implantation amount of 10 ¹⁶ / cm ² is good. Further, after patterning the polycrystalline silicon film 62 into the shape of the emitter electrode by photolithography, the silicon oxide film 46 in the portion is etched using the photoresist 46 as a mask to expose the silicon substrate and the gate electrode. [FIG. 18 (a)] Next, on the exposed silicon substrate and the gate electrode,
And Example 1 by salicidation on the emitter electrode
A titanium silicide film 42 is formed in the same manner as in [FIG.
8 (b)].

The subsequent wiring process can be the same as that of the first embodiment [FIG. 18 (c)]. Although the present embodiment has been described on the premise of the local wiring using titanium silicide, as the low resistance material, besides titanium silicide, a refractory metal such as cobalt, tantalum, nickel, tungsten, or platinum, or a refractory metal and silicon is used. The compound (silicide) or the like can also be used.

According to the present embodiment, the highly integrated SRA having the laminated structure of the calcal wiring using salicidation is used.
An M memory cell, a bipolar element and a CMOS transistor can be formed simultaneously, and an SRAM capable of high speed operation can be provided.

<Embodiment 11> This embodiment is C of Embodiment 10.
The present invention relates to a semiconductor integrated circuit device in which an SRAM using a MOS transistor and a bipolar transistor are formed on the same semiconductor substrate, and a method for forming no silicide layer on an emitter electrode. FIG. 19 is a sectional view of this embodiment showing a bipolar element and a CMOS transistor portion, and the SRAM memory cell portion is omitted. In the figure, the polycrystalline silicon film 6 of the emitter electrode
The silicon oxide film 76 is formed on the second layer 2, and the silicide film 42 is not formed.

Next, the manufacturing process of the bipolar transistor will be described with reference to the manufacturing process described in the tenth embodiment. First, when patterning the polycrystalline silicon film 62 of the emitter [corresponding to the step shown in FIG. 18A of Example 10], a silicon oxide film 76 having a thickness of 80 nm is deposited on the polycrystalline silicon film 62. After patterning the silicon oxide film 76 into the shape of the emitter electrode, the polycrystalline silicon film 62 is patterned using the silicon oxide film 76 as a dry etching mask. Then, in the step of exposing the silicon substrate and the gate electrode on the occasion of silicidation, the silicon oxide film 41 is dry-etched with a photoresist pattern [corresponding to FIG. 18A] that covers the emitter electrode. The subsequent salicide process and aluminum wiring formation process are the same as in the tenth embodiment.

Although the polycrystalline silicon film 62 of this embodiment is an emitter electrode, a resistance element can be formed by using the polycrystalline silicon film 62 in a portion other than the emitter.

According to the present embodiment, since the polycrystalline silicon film of the emitter electrode of the bipolar transistor is not silicidized, there is no influence of the diffusion of impurities into the silicide film and the high concentration n-type impurity region of the emitter in the silicon substrate is obtained. It becomes easy to control the impurity distribution of the. Therefore, a high performance bipolar transistor having a high current gain can be provided.

<Embodiment 12> This embodiment is C of Embodiment 10.
The present invention relates to a semiconductor integrated circuit device in which an SRAM using a MOS transistor and a bipolar transistor are formed on the same semiconductor substrate, and one using local wiring for a lead electrode of a base. FIG. 20 is a sectional view of this embodiment showing a bipolar element and a CMOS transistor portion, and the SRAM memory cell portion is omitted. 20, a high-concentration p-type impurity region 69 of the base region of the bipolar transistor, a polycrystalline silicon film 62 forming a common local wiring with the emitter electrode, and a high-concentration n-type impurity region 70 of the MOS transistor.
Are connected to each other by a titanium silicide film 42, and the titanium silicide film 42 is also formed on the polycrystalline silicon film 62. Further, as shown in FIG. 20, an opening may be provided on the titanium silicide film 42 on the polycrystalline silicon film 62 to connect the aluminum wiring 75. In this embodiment, the local wiring is connected to the source / drain of the n channel.
It can also be connected to the source / drain of the channel.
Further, this embodiment can be applied to the eleventh embodiment to omit the silicidation of the emitter electrode.

According to this embodiment, the required area for connecting the base of the bipolar transistor and the source / drain of the MOS transistor can be made smaller than usual,
Highly integrated SRAM cells as well as high speed SRAMs can be provided.

<Embodiment 13> This embodiment relates to a local wiring using a titanium nitride film. Figure 21
22A to 22B show cross sections of the manufacturing process of the present embodiment. The manufacturing process of this embodiment will be described below with reference to the drawings. First, the steps up to forming the MOS transistor on the silicon substrate and depositing the silicon oxide film 41 on the upper portion are the same as those in FIG. 4C of the first embodiment. Next, using the photoresist 46 as a mask, an opening is formed in the silicon oxide film 41 to expose the silicon substrate and the gate electrode [FIG. 21 (a)]. Then, a titanium film 77 having a thickness of 50 nm is deposited on the entire surface by sputtering [FIG. 21 (b)]. Then, in a nitrogen atmosphere at 675 ° C., 30
The surface of the titanium film 77 is converted into a titanium nitride film 78 by annealing for 1 minute, and the high-concentration n-type impurity regions 2 and 3 and the high-concentration p-type impurity region 1 are formed on the silicon substrate.
A titanium silicide film 79 is formed on 0 and the gate electrodes 11, 12, 13, and 14. Next, using the photoresist 46 as a mask, unnecessary portions of the titanium nitride film 78 and unreacted titanium film are removed by dry etching and wet etching containing a hydrogen peroxide solution. The annealing temperature and time are adjusted so that the film thicknesses of the titanium silicide film and the titanium nitride film have desired values. Then, the titanium nitride film 78 and the titanium silicide film 79 are annealed in a nitrogen atmosphere at 800 ° C. to reduce the resistance. [FIG. 22A] Subsequent formation of aluminum wiring is the same as in the first embodiment. [FIG. 22 (b)] According to the present embodiment, the local wiring of the SRAM memory cell can be formed of the titanium nitride film that serves as a barrier against diffusion of impurities, so that the n-channel MOS transistor and the p-channel MOS transistor are formed. There is no problem that impurities in the high-concentration impurity region of the transistor diffuse in the silicide and increase the contact resistance at the interface of the silicon substrate.

<Embodiment 14> This embodiment relates to a capacitive element formed in a circuit element group using CMIS transistors around the portion other than the memory cell. FIG. 26 shows a cross-sectional structure of this example. In the figure, an n-type well 37 and a field oxide film 38, and a gate oxide film 39 and a gate electrode 124 are formed on an n-type silicon substrate 35, and the gate electrode 124 is used as a mask for ion implantation to obtain a high concentration of n. The impurity regions 125 of the type are formed at the same time as the source / drain regions of the MIS transistor. Note that these steps are the normal C described in the first embodiment.
It is formed by the MIS process. Further, a titanium silicide film 127 of a local wiring is formed on the gate electrode 124 via a silicon oxide film 126, one end of the titanium silicide film 127 is connected to the high concentration n-type impurity region 125, and the gate is formed. The electrodes are connected to the aluminum wiring 128.

With the above structure, a MIS capacitor is formed between the gate electrode 124 and the n-type well 37, and a capacitor element is further formed between the gate electrode 124 and the titanium silicide film 127 of the local wiring. Although the titanium silicide film is used as the local wiring in the present embodiment, the polycide structure can be applied by applying the embodiment 7.
Further, although the present embodiment describes the MIS capacitance of the n-type well, the conductivity types of the impurities may be reversed with respect to the MIS capacitance of the p-type well. Note that the capacitor element formed in this embodiment can be used, for example, in a step-down circuit or a step-up circuit for power supply voltage.

According to this embodiment, there is no additional step other than the manufacturing step of the memory cell according to the present invention, and moreover, the two capacitive elements can be formed without increasing the required area on the silicon substrate. A capacitor with a small area can be formed.

<Embodiment 15> This embodiment relates to a resistance element formed in a circuit element group using CMIS transistors around the portion other than the memory cell. FIG. 27 shows the cross-sectional structure of this example. In the figure, a p-type well 36 and a field oxide film 38 are formed on an n-type silicon substrate 35, and a higher concentration n-type impurity region 125 is formed.
Are formed at the same time as the source / drain regions of the MIS transistor, and the silicon oxide film 126 is formed on the upper part. Note that these steps are formed by the normal CMIS process described in the first embodiment. Further, the silicon oxide film 126 is selectively etched in the portion to which the aluminum wiring 128 is connected, and the titanium silicide film 127 is formed in a portion on the high concentration impurity region 125 in the salicide process.

With the above structure, the n-type high-concentration impurity region 1 is formed.
25 is a resistance element. The resistance element formed in this embodiment can be used in, for example, an input protection circuit.

According to this embodiment, the resistance element can be formed without any additional step other than the manufacturing step of the memory cell according to the present invention and without increasing the required area on the silicon substrate.

<Embodiment 16> This embodiment relates to a method for connecting a local wiring and a silicon substrate. FIG. 28 is a sectional structure of the SRAM memory cell according to the present embodiment, which is an enlarged view of the local wiring portion in the sectional view taken along the line AA 'shown in FIG. The process up to forming the MIS transistor on the silicon substrate is shown in FIG.
This is the same as the process up to (c). In FIG. 5 (c),
The titanium nitride film 78 formed at the same time when the polycrystalline silicon film 45 is silicidized is patterned by photolithography in the same manner as that described in the thirteenth embodiment to leave a desired portion. The high-concentration n-type impurity region 2 and the titanium silicide film 41 are connected via the film 78 (FIG. 28). The subsequent steps may be the same as those in FIG. 6B of the first embodiment.

According to this embodiment, the silicon substrate and the gate electrode can be easily connected to the local wiring.

[0072]

According to the present invention, a low resistance material is formed on each surface of a source / drain and a gate electrode of a MIS transistor by a salicide process, and a local wiring can be formed by laminating on the gate electrode. Highly integrated, soft error resistant, and fully CMOS type SR with good compatibility with logic processes.
A semiconductor integrated circuit device having an AM cell can be provided.

[0073]

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a plan view of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 4 is a sectional view for explaining the manufacturing process for the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining the manufacturing process of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 6 is a sectional view for explaining the manufacturing process for the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 7 is a sectional view of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 8 is a sectional view of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 9 is a sectional view of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 10 is a sectional view of a semiconductor integrated circuit device according to a fifth embodiment of the present invention.

FIG. 11 is a plan view of a semiconductor integrated circuit device according to a sixth embodiment of the present invention.

FIG. 12 is an equivalent circuit diagram of a semiconductor integrated circuit device according to a sixth embodiment of the present invention.

FIG. 13 is a plan view of a semiconductor integrated circuit device according to a sixth embodiment of the present invention.

FIG. 14 is a sectional view of a semiconductor integrated circuit device according to a seventh embodiment of the present invention.

FIG. 15 is a plan view of a semiconductor integrated circuit device according to an eighth embodiment of the present invention.

FIG. 16 is a plan view of a semiconductor integrated circuit device according to a ninth embodiment of the present invention.

FIG. 17 is a sectional view for explaining the manufacturing process for the semiconductor integrated circuit device according to the tenth embodiment of the present invention.

FIG. 18 is a sectional view for explaining the manufacturing process for the semiconductor integrated circuit device according to the tenth embodiment of the present invention.

FIG. 19 is a sectional view of a semiconductor integrated circuit device according to an eleventh embodiment of the present invention.

FIG. 20 is a sectional view of a semiconductor integrated circuit device according to a twelfth embodiment of the present invention.

FIG. 21 is a cross-sectional view of the manufacturing process of the semiconductor integrated circuit device of the thirteenth embodiment of the present invention.

FIG. 22 is a cross-sectional view of the manufacturing process of the semiconductor integrated circuit device of the thirteenth embodiment of the present invention.

FIG. 23 is an equivalent circuit diagram of a static random access memory cell.

FIG. 24 is a plan view of a conventional static random access memory cell.

FIG. 25 is a cross-sectional view for explaining a manufacturing process of the conventional static random access memory cell.

FIG. 26 is a sectional view of a semiconductor integrated circuit device according to a fourteenth embodiment of the present invention.

FIG. 27 is a sectional view of a semiconductor integrated circuit device according to a fifteenth embodiment of the present invention.

FIG. 28 is a sectional view of a semiconductor integrated circuit device according to a sixteenth embodiment of the present invention.

[Explanation of symbols]

1, 2, 3, 4, 5, 6, ... High-concentration n-type impurity region (MO
Source / drain of S-transistor), 7, 8, 9, 1
0 ... High-concentration p-type impurity region (source / drain of p-channel MOS transistor), 11, 12, 13, 14 ...
Gate electrode, 15, 16, 17, 18 ... Opening portion, 19,
20 ... Local wiring, 21, 22, 23, 24, 25,
26 ... Openings 27, 28, 29, 30 ... First layer aluminum wiring, 31, 32 ... Openings, 33, 34 ... Second
Layer aluminum wiring, 35 ... N-type silicon substrate, 36
... p-type well, 37 ... n-type well, 38 ... field oxide film, 39 ... gate oxide film, 40 ... spacer insulating film, 4
1 ... Silicon oxide film, 42 ... Titanium silicide film, 4
3, 44 ... Silicon oxide film, 45 ... Amorphous silicon film,
46 ... Photoresist, 47 ... Titanium film, 48 ... Selective polycrystalline silicon film, 49 ... Amorphous silicon sidewall, 50 ... Silicon nitride film, 51, 52 ... Gate electrode,
53, 54 ... Local wiring, 55 ... Word lines, 56, 5
7 ... Data line, 58, 59, 60, 61 ... Opening part, 62
... Polycrystalline silicon film, 63 ... Silicon implantation region, 64 ...
First layer aluminum wiring, 65 ... p-type silicon substrate,
66 ... N-type buried layer, 67 ... P-type buried layer, 68 ... N
Type impurity region (collector extraction), 69 ... p type impurity region (base), 70 ... high concentration n type impurity region (source / drain of n channel MOS transistor), 71 ...
High-concentration p-type impurity region (source / drain of p-channel MOS transistor), 72 ... Gate electrode, 73 ... P-type impurity region (intrinsic base), 74 ... High-concentration n-type impurity region (emitter), 75 ... First layer Eye aluminum wiring, 7
6 ... Silicon oxide film, 77 ... Titanium film, 78 ... Titanium nitride film, 79 ... Titanium silicide film, 80, 8
1, 82, 83, 84, 85, 86 ... High-concentration n-type impurity regions, 87, 88, 89, 90 ... High-concentration p-type impurity regions, 91, 92, 93, 94 ... Gate electrodes, 95, 9
5, 97, 98, 99 ... Local wiring, 100, 10
1, 102, 103, 104, 105 ... Opening part, 10
6, 107, 108, 109 ... First layer aluminum wiring, 110, 111 ... Openings, 112, 113 ... Second layer aluminum wiring, 114 ... P-type well, 115 ... Field oxide film, 116 ... Gate oxide film Reference numeral 117 ... Gate electrode, 118 ... High-concentration n-type impurity region, 119 ... Spacer insulating film, 120 ... Titanium film, 121 ... Photoresist, 122 ... Amorphous silicon film, 123 ... Titanium silicide film, 124 ... Polycrystalline silicon film (Gate electrode), 1
25 ... High-concentration n-type impurity region, 126 ... Silicon oxide film, 127 ... Titanium silicide film, 128 ... Aluminum electrode, 129 ... Boundary between n-type well and p-type well.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 29/78 21/336 (72) Inventor Kenichi Kikushima 2326 Imai, Ome, Tokyo Hitachi, Ltd. In-house Device Development Center (72) Inventor Shinichiro Mitani 2326 Imai, Ome-shi, Tokyo Inside Hitachi Device Development Center (72) Inventor Kazushige Sato 2326 Imai, Ome-shi, Tokyo Inside Hitachi Device Development Center (72) Inventor Akira Fukami 1-280, Higashi Koigokubo, Kokubunji, Tokyo, Central Research Laboratory, Hitachi, Ltd. (72) Inventor Masaya Iida 2326, Imai, Ome, Tokyo (72) Inventor, Hitachi Ltd. (72) Inventor Akihiro Shimizu 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo SII Engineering Co., Ltd.

Claims (23)

[Claims] 1. A plurality of insulated gate type semiconductor devices comprising a first impurity region on a surface of a semiconductor substrate and a first conductive film and a second conductive film formed in the same layer with a first insulating film interposed therebetween. In a semiconductor integrated circuit device in which a field effect transistor is formed, a part of the first impurity region and a first conductive film on the first conductive film are formed.
And a third conductive film having a lower resistance than the second conductive film is formed, and the resistance value of the first conductive film is lower than the resistance value of the second conductive film. Integrated circuit device and manufacturing method thereof. 2. A first impurity region on a surface of a semiconductor substrate, a first conductive film and a second conductive film formed in the same layer with a first insulating film interposed therebetween, and a second conductive film on the second conductive film. In a semiconductor integrated circuit device in which a plurality of fourth conductive films are formed on a second insulating film via the second insulating film, the second insulating film is formed so that at least a part of the fourth conductive film overlaps with the second conductive film. The first impurity region is formed over the first conductive film and a part of the second conductive film other than the overlapping portion of the first conductive region and the fourth conductive film. Alternatively, a third conductive film having a lower resistance than the first conductive film is formed, and the resistance value of the first conductive film is the second conductive film.
Lower than the resistance value of the conductive film of No. 4, the fourth electrokinetic film is formed by a method including at least means for forming the third electrokinetic film, and the other second conductive film is the same as the fourth conductive film. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is connected to the semiconductor integrated circuit device. 3. A step of forming a first impurity region on a surface of a semiconductor substrate, a step of forming a first insulating film, a step of forming first and second conductive films, and the first and the second conductive films. The step of forming a second insulating film on the second conductive film, and then the fifth step.
And the step of forming the conductive film of the second conductive film, and subsequently, an opening to the first conductive film and an opening to the first impurity region extending over the fifth conductive film are simultaneously formed and the second insulating film is removed. And the step of lowering the resistance of the fifth conductive film, the third conductive film is selectively formed on the first conductive film exposed in the opening and a part of the first impurity region. The step of forming by alignment,
3. The semiconductor integrated circuit device according to claim 2, and a method of manufacturing the same, including a step of connecting the third conductive film to the first impurity region and the fourth conductive film at the relevant portion. 4. A flip-flop circuit having a first storage node and a second storage node, wherein one drain and the other gate of a pair of driving insulated gate field effect transistors for driving are cross-connected to each other; A pair of insulated gate field effect transistors for transfer and a pair of load elements connected to the first and second storage nodes, respectively, and a word line formed of a common gate electrode of the insulated gate field effect transistors for transfer. In the static random access memory cell, the gate insulating film of the electrically insulating gate type field effect transistor for driving and the insulating gate type field effect transistor for transfer is composed of a first insulating film. The resistance value of the gate electrode is the resistance of the gate electrode of the driving insulated gate field effect transistor. And a method for manufacturing the same. 5. The gate electrodes of the driving insulated gate field effect transistor and the load insulated gate field effect transistor of the memory cell group are formed of the second conductive film.
A gate electrode of the insulated gate field effect transistor for transfer of the memory cell group and a gate electrode of the insulated gate field effect transistor of the peripheral circuit group have the first conductive film and the third conductive film having a resistance lower than that of the first conductive film. 5. A semiconductor integrated circuit device according to claim 1 and claim 4 and a method for manufacturing the same, which is composed of a composite film with a conductive film. 6. A pair of transfer MIS transistors, a pair of transfer MIS transistors, and a pair of drive MIS transistors are respectively arranged in the X direction, and transfer M transistors are provided.
In the static random access memory cell in which the gate electrode of the IS transistor extends in the X direction and the common gate electrode of the driving MIS transistor and the load MIS transistor extends in the Y direction, a pair of local Wirings are formed on the common gate electrodes of the driving MIS transistor and the load MIS transistor so as to extend in the Y direction, respectively, and each of the pair of local wirings is formed by using the same connecting means. One is connected to the high-concentration n-type impurity region of the drain of the one driving MIS transistor at the end side wall, and the other of the pair of local wirings is connected to the high drain of the other driving MIS transistor at the end side wall. One of the pair of local wirings is connected to the concentration n-type impurity region, and one of the pair of local wirings has an end side wall and the other driving MIS transistor. Connected to the gate electrode of the transistor, and the other of the pair of local wirings is connected to the gate electrode of one of the driving MIS transistors at the end side wall, and a semiconductor integrated circuit device and its manufacture. Method. 7. A first impurity region, a first conductive film and a pair of second conductive films formed in the same layer via a first insulating film are formed on the surface of a semiconductor substrate. Further, a pair of fourth conductive films is formed on the second conductive film via a second insulating film, and the pair of transfer insulated gate field effect transistor gate electrodes is formed by the first conductive film. And a gate electrode of the pair of driving insulated gate field effect transistors is formed by the second conductive film, and the first or second storage node has at least a first impurity region. In the semiconductor integrated circuit device including the fourth conductive film, the fourth conductive film is formed through the second insulating film so that at least part of the fourth conductive film overlaps with the second conductive film. The first impurity region and the second conductive film A third conductive film having a lower resistance than the first impurity region or the second conductive film is simultaneously formed in a part other than the overlapping portion with the fourth conductive film, and one of the fourth conductive films is Is insulated from the gate electrode of the driving insulated gate field effect transistor of, and is connected to the gate electrode of the other driving insulated gate field effect transistor to form a local interconnection in the memory cell. A semiconductor integrated circuit device according to claim 5 or 6, and a method for manufacturing the same. 8. The pair of load elements are composed of a pair of insulated gate field effect transistors for driving which are opposite in conductivity type to the insulated gate field effect transistor for driving, and are connected to the same storage node. The gate type field effect transistor and the driving insulated gate field effect transistor have a common gate electrode, and are connected to one storage node at the drain of the driving and load insulated gate field effect transistor and at the other storage node. 8. The gate electrodes of the connected driving and load insulated gate field effect transistors are connected to each other by the fourth conductive film to form a cross connection of flip-flop circuits. Integrated circuit device and its manufacturing method. 9. A portion of the first conductive film, the second conductive film, and the first impurity region other than an overlapping portion of the fourth conductive film is masked with the fourth conductive film. 3. A low resistance third conductive film is formed.
A semiconductor integrated circuit device according to claim 7, and a method for manufacturing the same. 10. The first and second conductive films are made of doped polycrystalline silicon, and the third conductive film is made of a refractory metal such as W, Ti, Co, Pt, Ni and Ta. 6. A conductor integrated circuit device according to claim 1 and claim 5, characterized by comprising a compound with silicon, and a method for manufacturing the same. 11. The first and second conductive films are made of doped polycrystalline silicon, and the third conductive film is made of a refractory metal such as W, Ti, Co, Pt, Ni and Ta. The semiconductor integrated circuit device according to claim 1 or 5, and the method for manufacturing the same. 12. The fourth conductive film comprises W, Ti, C
8. A semiconductor integrated circuit device according to claim 2, wherein the compound is a compound of a refractory metal such as o, Pt, Ni, Ta, and silicon, and a method for manufacturing the same. 13. The fourth conductive film comprises W, Ti, C
8. The semiconductor integrated circuit device according to claim 2 and claim 7, wherein the semiconductor integrated circuit device is made of a refractory metal such as o, Pt, Ni, Ta, etc. 14. The fourth conductive film is made of W, Ti, C.
8. A semiconductor integrated circuit device according to claim 2 and claim 7, and a method for manufacturing the same, which is composed of a composite film of a compound of high melting point metal such as o, Pt, Ni, Ta and silicon and polycrystalline silicon. 15. The fourth conductive film comprises W, Ti, C
3. A composite film comprising a polycrystalline silicon and a refractory metal such as o, Pt, Ni or Ta.
A semiconductor integrated circuit device according to claim 7, and a method for manufacturing the same. 16. The semiconductor integrated circuit device according to claim 14 and claim 15, wherein said polycrystalline silicon is doped with a P-type impurity at a high concentration. 17. The second conductive film, the second insulating film, and the fourth conductive film form a capacitive element that supplies charges to the second conductive film. A semiconductor integrated circuit device according to claim 2, and a method for manufacturing the same. 18. The semiconductor integrated circuit device according to claim 17, wherein the capacitance element is connected between the first and second storage nodes, and a manufacturing method thereof. 19. The semiconductor integrated circuit device according to claim 2, wherein the second insulating film includes a silicon nitride film, and a method of manufacturing the same. 20. In a semiconductor integrated circuit device in which a bipolar transistor and an insulated gate field effect transistor are formed on the same semiconductor substrate, an emitter electrode of the bipolar transistor is formed of the fourth conductive film. A semiconductor integrated circuit device according to claim 2 and claim 7, and a manufacturing method thereof. 21. In a semiconductor integrated circuit device, a power supply wiring and a ground wiring for supplying power to a static random access memory cell array are made of an aluminum wiring of a first layer, and a data line is made of an aluminum wiring of a second layer. 8. The semiconductor integrated circuit device according to claim 5, wherein the logic circuit other than the memory cell array is composed of three or more layers of aluminum wiring. 22. The semiconductor integrated circuit according to claim 21, wherein the aluminum wiring of the first layer is formed in the word line direction, and a plurality of word lines on extension lines of the word line are connected. Device and manufacturing method thereof. 23. In a semiconductor integrated circuit device in which a static random access memory and a logic element of a microprocessor are formed on the same semiconductor substrate, the gate electrode of an insulated gate field effect transistor of the logic element group is the first electrode. 8. A semiconductor integrated circuit device according to claim 5, wherein the semiconductor integrated circuit device comprises a composite film of a conductive film and the third conductive film, and a method of manufacturing the same.