JPH07320996A - Method and jig for electrostatic bonding - Google Patents
Method and jig for electrostatic bondingInfo
- Publication number
- JPH07320996A JPH07320996A JP10937394A JP10937394A JPH07320996A JP H07320996 A JPH07320996 A JP H07320996A JP 10937394 A JP10937394 A JP 10937394A JP 10937394 A JP10937394 A JP 10937394A JP H07320996 A JPH07320996 A JP H07320996A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- wafers
- insulating substrate
- bonded
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims abstract description 27
- 235000012431 wafers Nutrition 0.000 claims abstract description 109
- 239000000758 substrate Substances 0.000 claims abstract description 46
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 36
- 239000010703 silicon Substances 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims description 19
- 238000010438 heat treatment Methods 0.000 claims description 11
- 239000011521 glass Substances 0.000 claims description 5
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 claims description 3
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 239000005297 pyrex Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 230000001133 acceleration Effects 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 5
- 238000001514 detection method Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Landscapes
- Pressure Sensors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は静電接合方法に関し、特
に、圧力検知や加速度検知に使用される半導体センサの
製造に用いられる静電接合方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic bonding method, and more particularly to an electrostatic bonding method used for manufacturing a semiconductor sensor used for pressure detection and acceleration detection.
【０００２】[0002]
【従来の技術】一般に、産業機械、自動車、或いは、各
種家電製品等に使用され、圧力検知や加速度検知を行う
半導体圧力センサや加速度センサが知られている。この
ような半導体圧力センサ及び半導体加速度センサは、そ
れぞれ図３（ａ）及び（ｂ）に示すような構造となって
いる。即ち、可動電極としてダイヤフラム部３１ａ（３
１ｂ）が形成されたシリコン基板３２ａ（３２ｂ）と、
固定電極部３３ａ（３３ｂ）を形成した絶縁基板３４ａ
（３４ｂ）とを互いに接着してセンサを構成している。
ここで、絶縁基板３４ａ（３４ｂ）としては、一般に、
ソーダガラスが用いられる。2. Description of the Related Art Generally, there are known semiconductor pressure sensors and acceleration sensors used for industrial machines, automobiles, various home appliances, etc. for detecting pressure and acceleration. Such a semiconductor pressure sensor and a semiconductor acceleration sensor have structures as shown in FIGS. 3 (a) and 3 (b), respectively. That is, the diaphragm portion 31a (3
1b) is formed on the silicon substrate 32a (32b),
Insulating substrate 34a on which fixed electrode portion 33a (33b) is formed
(34b) is bonded to each other to form a sensor.
Here, as the insulating substrate 34a (34b), generally,
Soda glass is used.
【０００３】圧力センサでは、図３（ａ）に示すように
絶縁基板３４ａに貫通孔３５が設けられており、この貫
通孔３５に加えられる圧力（比較圧力）Ｐ0 と、外部か
ら加えられる圧力Ｐ1 との差によってダイヤフラム部３
１ａが変形し、ダイヤフラム部３１ａと固定電極部３３
ａとの距離が変化して静電容量が変化する。この静電容
量の変化によって圧力Ｐ1 を検出することができる。In the pressure sensor, as shown in FIG. 3A, a through hole 35 is provided in the insulating substrate 34a, and the pressure (comparative pressure) P 0 applied to this through hole 35 and the pressure applied from the outside. Diaphragm part 3 due to the difference with P 1
1a is deformed and the diaphragm portion 31a and the fixed electrode portion 33 are deformed.
The distance from a changes and the capacitance changes. The pressure P 1 can be detected by the change in the electrostatic capacitance.
【０００４】また、加速度センサでは、図３（ｂ）に示
すようにダイヤフラム部におもり３６が設けられてお
り、加速度が加えられたとき、おもり３６によって発生
する力がダイヤフラム部３１ｂを変形させる。Further, in the acceleration sensor, the diaphragm 36 is provided with a weight 36 as shown in FIG. 3 (b), and when acceleration is applied, the force generated by the weight 36 deforms the diaphragm portion 31b.
【０００５】従来、シリコン基板３２ａ（３２ｂ）と絶
縁基板３３ａ（３３ｂ）とを接着する方法として、静電
接合の手法が採用されている。この方法は、図４に示す
ように、まず、シリコン基板パターンが形成されたシリ
コンウエハー４１と、絶縁基板パターンが形成された絶
縁基板ウエハー４２とを重ねて金属製加熱プレート４３
上に置く。次に、ウエハー移動用チャック４４に絶縁基
板ウエハー４２を吸着させる。そして、顕微鏡４５など
の光学系を用いてシリコン基板パターンと絶縁基板パタ
ーンと位置関係を確認しながら、ウエハー移動用チャッ
ク４４を微調移動させて、シリコンウエハー４１と絶縁
基板ウエハー４２の相互位置の調節を行う。なお、絶縁
基板ウエハー４２は、シリコン基板ウエハー４１とほぼ
同じ熱膨脹係数を有する石英ガラス、ソーダガラス、パ
イレックスガラス等が使用されている。Conventionally, as a method of adhering the silicon substrate 32a (32b) and the insulating substrate 33a (33b), an electrostatic bonding method has been adopted. In this method, as shown in FIG. 4, first, a silicon wafer 41 having a silicon substrate pattern formed thereon and an insulating substrate wafer 42 having an insulating substrate pattern formed thereon are overlapped with each other to form a metal heating plate 43.
put on top. Next, the insulating substrate wafer 42 is attracted to the wafer moving chuck 44. Then, while confirming the positional relationship between the silicon substrate pattern and the insulating substrate pattern using an optical system such as a microscope 45, the wafer moving chuck 44 is finely moved to adjust the mutual position of the silicon wafer 41 and the insulating substrate wafer 42. I do. The insulating substrate wafer 42 is made of quartz glass, soda glass, Pyrex glass, or the like having the same coefficient of thermal expansion as the silicon substrate wafer 41.
【０００６】次に、電圧印加電極棒４６を絶縁基板ウエ
ハー４２の上面の中央近傍に接触させ、金属製加熱プレ
ート４３（シリコンウエハー４１）をアースとして、絶
縁基板ウエハー４２にマイナスの高電圧（−４００〜６
００Ｖ）を印加する。そして、金属加熱プレート４３の
温度を予備加熱状態（１００℃前後）から、４００〜５
００℃に上昇させて、約４〜５時間、その温度を保持す
る。すると、始め電界強度の強い中央部から徐々に周辺
部へと、シリコンウエハー４１と絶縁基板ウエハー４２
とが静電接着され、４〜５時間後には全面に渡って接着
される。Next, the voltage applying electrode rod 46 is brought into contact with the vicinity of the center of the upper surface of the insulating substrate wafer 42, and the metal heating plate 43 (silicon wafer 41) is used as a ground, so that a high negative voltage (-) is applied to the insulating substrate wafer 42. 400-6
00V) is applied. Then, the temperature of the metal heating plate 43 is set to 400 to 5 from the preheating state (around 100 ° C.).
Raise to 00 ° C and hold at that temperature for about 4-5 hours. Then, the silicon wafer 41 and the insulating substrate wafer 42 are gradually moved from the central portion where the electric field strength is strong to the peripheral portion.
And are electrostatically adhered, and after 4 to 5 hours, they are adhered over the entire surface.
【０００７】[0007]
【発明が解決しようとする課題】従来の静電接合方法で
は、一組のシリコンウエハーと絶縁基板ウエハーとの接
合に４〜５時間かかる。しかも、シリコンウエハーと絶
縁基板ウエハーとのパターン合わせは一組ずつ行なわな
ければならず、また、パターン合わせの工程と静電接合
工程とは連続して行わなければならないので、結果とし
て４〜５時間で１組しか処理することができない。即
ち、従来の静電接合方法は、非常に生産効率が悪いとい
う問題点がある。In the conventional electrostatic bonding method, it takes 4 to 5 hours to bond a set of silicon wafer and insulating substrate wafer. In addition, the pattern matching of the silicon wafer and the insulating substrate wafer must be performed one by one, and the pattern matching process and the electrostatic bonding process must be performed continuously, resulting in 4 to 5 hours. Can process only one set. That is, the conventional electrostatic bonding method has a problem that the production efficiency is very low.
【０００８】本発明は、生産効率の高い静電接合方法を
提供することを目的とする。An object of the present invention is to provide an electrostatic bonding method with high production efficiency.
【０００９】[0009]
【課題を解決するための手段】本発明によれば、シリコ
ンウエハーと絶縁基板ウエハーとを重ね合わせ、相互位
置の調整を行った後、前記シリコンウエハー及び前記絶
縁基板ウエハーを加熱しながら、前記シリコンウエハー
をアースとして前記絶縁基板ウエハーに負の高電圧を第
１の所定時間印加して、前記シリコンウエハーと前記絶
縁基板ウエハーとを局部的に接着して仮接着ウエハーと
する第１の工程と、該第１の工程を繰り返して、複数の
仮接着ウエハーを得る第２の工程と、前記複数の仮接着
ウエハーを同時に加熱すると共に、該複数の仮接着ウエ
ハーの各々について前記シリコンウエハーをアースとし
て前記絶縁基板ウエハーに負の高電圧を前記第１の所定
時間よりも長い第２の所定時間印加して前記シリコンウ
エハーと前記絶縁基板ウエハーとを全面に渡って接着す
る第３の工程を含むことを特徴とする静電接合方法が得
られる。According to the present invention, after the silicon wafer and the insulating substrate wafer are superposed on each other and their mutual positions are adjusted, the silicon wafer and the insulating substrate wafer are heated while the silicon wafer is heated. A first step in which a negative high voltage is applied to the insulating substrate wafer for a first predetermined time with the wafer as the ground, and the silicon wafer and the insulating substrate wafer are locally bonded to each other to form a temporary bonded wafer; The second step of repeating the first step to obtain a plurality of temporary bonded wafers and the plurality of temporary bonded wafers are simultaneously heated, and the silicon wafer is grounded for each of the plurality of temporary bonded wafers. A negative high voltage is applied to the insulating substrate wafer for a second predetermined time longer than the first predetermined time to insulate the silicon wafer from the insulating wafer. Electrostatic bonding method characterized in that it comprises a third step of bonding across the plate wafer the entire surface is obtained.
【００１０】また、本発明によれば、所定形状のウエハ
ーを収容するための収容部が複数形成された金属製ケー
スと、前記収容部にそれぞれ配設され、該収容部に前記
ウエハーが収容されたとき該ウエハーに接触する電圧印
加用電極棒とを有することを特徴とする静電接合用治具
が得られる。Further, according to the present invention, a metal case having a plurality of accommodating portions for accommodating a wafer having a predetermined shape and the accommodating portion are respectively disposed, and the wafer is accommodated in the accommodating portion. An electrostatic bonding jig is obtained which has a voltage applying electrode rod that comes into contact with the wafer.
【００１１】[0011]
【実施例】以下に、図面を参照して本発明の実施例を説
明する。本実施例の静電接合方法では、まず、仮接着工
程が実施される。この工程は、図１（ａ）に示すよう
に、従来の静電接合方法による接着工程と同じ工程であ
る。ただし、シリコンウエハー４１をアースとして絶縁
基板ウエハー４２に負の高電圧を印加する時間は、従来
の工程に比べて短い。その時間は、シリコンウエハー４
１と絶縁基板ウエハー４２との中央部（電界の集中する
電圧印加電極棒の周辺）が互いに接着されるに必要な時
間（例えば、２０〜３０分）とする。この仮接着工程に
より、シリコンウエハー４１と絶縁基板ウエハー４２と
は互いに中央部が接着され一体的に（仮接着ウエハー１
１として）取り扱えるようになる。したがって、この仮
接着ウエハー１１を接合用治具から取り外すことが可能
となり、別のシリコンウエハーと絶縁基板ウエハーとを
処理することが可能となる。Embodiments of the present invention will be described below with reference to the drawings. In the electrostatic bonding method of this embodiment, first, a temporary bonding step is carried out. As shown in FIG. 1A, this step is the same as the bonding step by the conventional electrostatic bonding method. However, the time for applying the negative high voltage to the insulating substrate wafer 42 with the silicon wafer 41 as the ground is shorter than that in the conventional process. That time is silicon wafer 4
1 and the central portion of the insulating substrate wafer 42 (the periphery of the voltage applying electrode rod where the electric field is concentrated) are required to be bonded to each other (for example, 20 to 30 minutes). By this temporary bonding process, the silicon wafer 41 and the insulating substrate wafer 42 are bonded at their central portions to each other (temporarily bonded wafer 1
Can be handled (as 1.). Therefore, the temporary bonded wafer 11 can be removed from the bonding jig, and another silicon wafer and an insulating substrate wafer can be processed.
【００１２】上記仮接着工程を繰り返し実行し、所定数
の仮接着ウエハーが得られたら、全面接着工程に入る。
全面接着工程では、図１（ｂ）に示すような接合治具を
使用する。この接合治具は、仮接着ウエハー１１を収容
するための収容部１２が複数（本実施例では４つ）形成
された金属ケース１３と、各収容部１２に配設された電
圧印加用電極棒１４を有している。The above temporary adhesion step is repeatedly performed, and when a predetermined number of temporary adhesion wafers are obtained, the entire surface adhesion step is started.
In the whole surface bonding step, a joining jig as shown in FIG. 1 (b) is used. This bonding jig includes a metal case 13 in which a plurality of accommodating portions 12 (four in this embodiment) for accommodating the temporarily bonded wafer 11 are formed, and a voltage applying electrode rod disposed in each accommodating portion 12. Have fourteen.
【００１３】仮接着ウエハー１１は、シリコンウエハー
を下側にして（金属ケース１３に接触する用にして）金
属ケース１３の収容部１２に収容される。電圧印加用電
極棒１４は、このとき、絶縁基板ウエハーのほぼ中央に
接触する用に、収容部１２の上部に取り付けられてい
る。The temporarily bonded wafer 11 is housed in the housing portion 12 of the metal case 13 with the silicon wafer facing downward (for contacting the metal case 13). At this time, the voltage applying electrode rod 14 is attached to the upper portion of the housing portion 12 so as to come into contact with substantially the center of the insulating substrate wafer.
【００１４】全面接着工程は、仮接着ウエハー１１を収
容部１２に収容した金属ケース１３を図示しない恒温槽
に入れて行う。恒温槽内を４００〜５００℃に保ち、金
属ケースをアースとして電極印加用電極棒に−４００〜
−６００Ｖの電圧を印加して４〜５時間維持すれば、す
べての仮接着ウエハー１１のシリコンウエハーと絶縁基
板ウエハーとを全面に渡って接着することができる。The entire surface bonding step is carried out by placing the metal case 13 in which the temporary bonding wafer 11 is housed in the housing portion 12 in a thermostat which is not shown. Keep the temperature in the constant temperature bath at 400-500 ° C, and use the metal case as the ground for the electrode bar for electrode application -400-
If a voltage of −600 V is applied and maintained for 4 to 5 hours, the silicon wafer and the insulating substrate wafer of all temporary adhesion wafers 11 can be bonded over the entire surface.
【００１５】１個の仮接着ウエハーを製作するのに要す
る時間をＴ１［時間］、全面接着工程で１度に処理でき
る枚数をＮ［枚］、全面接着ウエハーを製作するのに要
する時間をＴ２［時間］とすると、本実施例を用いてＮ
［枚］のシリコンウエハーと絶縁基板ウエハーとの全面
接着ウエハーを作成するのに要する時間は，Ｔ１×Ｎ＋
Ｔ２、となる。従来の方法では、Ｔ２×Ｎ時間必要だっ
たので、本実施例によれば、処理時間を（Ｔ１×Ｎ＋Ｔ
２）／（Ｔ２×Ｎ）＝Ｔ１／Ｔ２＋１／Ｎに短縮するこ
とができる。例えば、Ｔ１＝０．５、Ｔ２＝４、Ｎ＝４
の場合、従来の１／２以下に短縮することができる。The time required to manufacture one temporary bonded wafer is T1 [hours], the number of wafers that can be processed at one time in the whole surface bonding process is N [sheets], and the time required to manufacture a whole bonded wafer is T2. If [time] is set, N is set using this embodiment.
The time required to form a [wafer] silicon wafer and insulating substrate wafer over the entire surface is T1 × N +
It becomes T2. Since the conventional method requires T2 × N time, according to the present embodiment, the processing time is (T1 × N + T).
2) / (T2 × N) = T1 / T2 + 1 / N can be shortened. For example, T1 = 0.5, T2 = 4, N = 4
In the case of, it can be shortened to 1/2 or less of the conventional case.
【００１６】なお、上記実施例では、金属ケースを用い
て全面接着工程を行ったが、図２に示すように仮接着ウ
エハー１１を複数載置できる金属製加熱プレート２１を
用いて行ってもよい。この場合、電圧印加用電極棒２２
は、金属製加熱プレート２１表面の仮接着ウエハー１１
が載置される位置に対向して設けられる。In the above embodiment, the whole surface bonding process is performed using the metal case, but as shown in FIG. 2, a metal heating plate 21 on which a plurality of temporary bonding wafers 11 can be placed may be used. . In this case, the voltage applying electrode rod 22
Is a temporarily bonded wafer 11 on the surface of the metal heating plate 21.
Is provided so as to face the position where the is placed.
【００１７】[0017]
【発明の効果】本発明によれば、シリコンウエハーと絶
縁基板ウエハーとの接着を、仮接着工程と全面接着工程
とに分け、まず、仮接着工程によって複数の仮接着ウエ
ハーを個々に作成した後、これら複数の仮接着ウエハー
に対して全面接着工程を一度に行うようにしたことで、
製造時間を大幅に短縮することができる。According to the present invention, the bonding between the silicon wafer and the insulating substrate wafer is divided into a temporary bonding step and a whole surface bonding step, and first, a plurality of temporary bonding wafers are individually prepared by the temporary bonding step. By performing the whole surface bonding process on these temporary bonded wafers at once,
The manufacturing time can be significantly reduced.
【００１８】また、本発明の接合用治具を用いれば、複
数の仮接合ウエハーを同時に全面接合することができ
る。Further, by using the bonding jig of the present invention, a plurality of temporary bonded wafers can be simultaneously bonded on the entire surface at the same time.
【図１】本発明の一実施例に使用される接合用治具の一
例の斜視図である。FIG. 1 is a perspective view of an example of a joining jig used in an embodiment of the present invention.
【図２】本発明の一実施例に使用される接合用治具の他
の例の斜視図である。FIG. 2 is a perspective view of another example of the joining jig used in the embodiment of the present invention.
【図３】（ａ）半導体圧力センサおよび（ｂ）加速度セ
ンサの断面図である。FIG. 3 is a sectional view of (a) a semiconductor pressure sensor and (b) an acceleration sensor.
【図４】従来の静電接合方法を説明するための図であ
る。FIG. 4 is a diagram for explaining a conventional electrostatic bonding method.
１１ 仮接着ウエハー １２ 収容部 １３ 金属ケース １４ 電圧印加用電極棒 ２１ 金属製加熱プレート ２２ 電圧印加用電極棒 ３１ａ，３１ｂ ダイヤフラム部 ３２ａ，３２ｂ シリコン基板 ３３ａ，３３ｂ 固定電極部 ３４ａ，３４ｂ 絶縁基板 ３５ 貫通孔 ３６ おもり ４１ シリコンウエハー ４２ 絶縁基板ウエハー ４３ 金属製加熱プレート ４４ ウエハー移動用チャック ４５ 顕微鏡 ４６ 電圧印加電極棒 11 Temporary Bonded Wafer 12 Housing 13 Metal Case 14 Voltage Applying Electrode 21 Metal Heating Plate 22 Voltage Applying Electrode 31a, 31b Diaphragm 32a, 32b Silicon Substrate 33a, 33b Fixed Electrode 34a, 34b Insulating Substrate 35 Penetrating Hole 36 Weight 41 Silicon wafer 42 Insulating substrate wafer 43 Metal heating plate 44 Wafer moving chuck 45 Microscope 46 Voltage applying electrode rod
Claims (4)
を重ね合わせ、相互位置の調整を行った後、前記シリコ
ンウエハー及び前記絶縁基板ウエハーを加熱しながら、
前記シリコンウエハーをアースとして前記絶縁基板ウエ
ハーに負の高電圧を第１の所定時間印加して、前記シリ
コンウエハーと前記絶縁基板ウエハーとを局部的に接着
して仮接着ウエハーとする第１の工程と、該第１の工程
を繰り返して、複数の仮接着ウエハーを得る第２の工程
と、前記複数の仮接着ウエハーを同時に加熱すると共
に、該複数の仮接着ウエハーの各々について前記シリコ
ンウエハーをアースとして前記絶縁基板ウエハーに負の
高電圧を前記第１の所定時間よりも長い第２の所定時間
印加して前記シリコンウエハーと前記絶縁基板ウエハー
とを全面に渡って接着する第３の工程を含むことを特徴
とする静電接合方法。1. A silicon wafer and an insulating substrate wafer are overlapped with each other and their mutual positions are adjusted, and then while heating the silicon wafer and the insulating substrate wafer,
A first step in which a negative high voltage is applied to the insulating substrate wafer for a first predetermined time with the silicon wafer as a ground, and the silicon wafer and the insulating substrate wafer are locally bonded to each other to form a temporary bonded wafer. And a second step of repeating the first step to obtain a plurality of temporary adhesion wafers, simultaneously heating the plurality of temporary adhesion wafers, and grounding the silicon wafer for each of the plurality of temporary adhesion wafers. And a third step of applying a negative high voltage to the insulating substrate wafer for a second predetermined time longer than the first predetermined time to bond the silicon wafer and the insulating substrate wafer over the entire surface. An electrostatic bonding method characterized by the above.
ラス、石英ガラス、または、パイレックスガラスが用い
られることを特徴とする請求項１の静電接合方法。2. The electrostatic bonding method according to claim 1, wherein soda glass, quartz glass, or Pyrex glass is used as the insulating substrate wafer.
容部が複数形成された金属製ケースと、前記収容部にそ
れぞれ配設され、該収容部に前記ウエハーが収容された
とき該ウエハーに接触する電圧印加用電極棒とを有する
ことを特徴とする静電接合用治具。3. A metal case having a plurality of accommodating portions for accommodating a wafer having a predetermined shape, and a metal case disposed in each of the accommodating portions and contacting the wafer when the wafer is accommodated in the accommodating portion. A jig for electrostatic bonding, comprising:
面を有する金属製加熱プレートと、前記表面に対向配置
され、該表面の所定位置に前記ウエハーを載置したとき
該ウエハーに接触する複数の電圧印加用電極棒を有する
ことを特徴とする静電接合用治具。4. A metal heating plate having a surface on which a plurality of wafers having a predetermined shape can be mounted, and a plurality of metal heating plates arranged to face the surface and contacting the wafer when the wafer is mounted at a predetermined position on the surface. A jig for electrostatic bonding, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10937394A JPH07320996A (en) | 1994-05-24 | 1994-05-24 | Method and jig for electrostatic bonding |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10937394A JPH07320996A (en) | 1994-05-24 | 1994-05-24 | Method and jig for electrostatic bonding |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07320996A true JPH07320996A (en) | 1995-12-08 |
Family
ID=14508598
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10937394A Withdrawn JPH07320996A (en) | 1994-05-24 | 1994-05-24 | Method and jig for electrostatic bonding |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07320996A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6309950B1 (en) | 1998-08-04 | 2001-10-30 | Micron Technology, Inc. | Methods for making silicon-on-insulator structures |
| US6423613B1 (en) * | 1998-11-10 | 2002-07-23 | Micron Technology, Inc. | Low temperature silicon wafer bond process with bulk material bond strength |
| US6852167B2 (en) | 2001-03-01 | 2005-02-08 | Micron Technology, Inc. | Methods, systems, and apparatus for uniform chemical-vapor depositions |
| US7160577B2 (en) | 2002-05-02 | 2007-01-09 | Micron Technology, Inc. | Methods for atomic-layer deposition of aluminum oxides in integrated circuits |
| US7560793B2 (en) | 2002-05-02 | 2009-07-14 | Micron Technology, Inc. | Atomic layer deposition and conversion |
| WO2009125763A1 (en) * | 2008-04-08 | 2009-10-15 | 株式会社島津製作所 | Adhesive injection device |
| US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
| US8921914B2 (en) | 2005-07-20 | 2014-12-30 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
| CN115611231A (en) * | 2022-10-31 | 2023-01-17 | 华东光电集成器件研究所 | Wafer-level bonding method for SOI silicon wafer and glass |
-
1994
- 1994-05-24 JP JP10937394A patent/JPH07320996A/en not_active Withdrawn
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6309950B1 (en) | 1998-08-04 | 2001-10-30 | Micron Technology, Inc. | Methods for making silicon-on-insulator structures |
| US6538330B1 (en) | 1998-08-04 | 2003-03-25 | Micron Technology, Inc. | Multilevel semiconductor-on-insulator structures and circuits |
| US6423613B1 (en) * | 1998-11-10 | 2002-07-23 | Micron Technology, Inc. | Low temperature silicon wafer bond process with bulk material bond strength |
| US6630713B2 (en) | 1998-11-10 | 2003-10-07 | Micron Technology, Inc. | Low temperature silicon wafer bond process with bulk material bond strength |
| US7410668B2 (en) | 2001-03-01 | 2008-08-12 | Micron Technology, Inc. | Methods, systems, and apparatus for uniform chemical-vapor depositions |
| US6852167B2 (en) | 2001-03-01 | 2005-02-08 | Micron Technology, Inc. | Methods, systems, and apparatus for uniform chemical-vapor depositions |
| US7160577B2 (en) | 2002-05-02 | 2007-01-09 | Micron Technology, Inc. | Methods for atomic-layer deposition of aluminum oxides in integrated circuits |
| US7560793B2 (en) | 2002-05-02 | 2009-07-14 | Micron Technology, Inc. | Atomic layer deposition and conversion |
| US8921914B2 (en) | 2005-07-20 | 2014-12-30 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
| WO2009125763A1 (en) * | 2008-04-08 | 2009-10-15 | 株式会社島津製作所 | Adhesive injection device |
| US8496037B2 (en) | 2008-04-08 | 2013-07-30 | Shimadzu Corporation | Adhesive injection device |
| US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
| US8389385B2 (en) | 2009-02-04 | 2013-03-05 | Micron Technology, Inc. | Semiconductor material manufacture |
| CN115611231A (en) * | 2022-10-31 | 2023-01-17 | 华东光电集成器件研究所 | Wafer-level bonding method for SOI silicon wafer and glass |
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