JPH07319824A - Information processing system and method therefor - Google Patents

Abstract

PURPOSE:To provide information processing system and method capable of accurately holding a built-in clock. CONSTITUTION:A 1st information processor 120 has an accurate clock 100. When a 2nd information processor 130 is connected to the processor 120, the processor 120 reads out a date and time from the clock 100 and sends the read date and time to the processor 130 through transmitters/receivers 104, 106. The processor 130 sets up the received date and time in a clock 109 by a setting device 108. The transmission of the date and time can be executed also at the time of transferring data from the processor 130. In the case of transferring data and time from the processor 130, time values indicated by both the clocks 100, 109 are mutually compared and the date and time can be transferred based upon the compared result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a built-in clock such as a host computer and a terminal device, and an information processing system constituted by the same.

[0002]

2. Description of the Related Art Handy terminals (portable terminal devices,
Hereinafter, referred to as HT) is used as a terminal for collecting data at a location distant from the host computer. The data collected by the HT is transferred to the host computer for processing. Thus, what is most important when collecting data separately from the host computer that performs final processing is whether the data input / updated on the HT side is correctly transmitted to the host computer side. . For example, carelessness of the operator may cause forgetting to transfer the data collected in the HT to the host computer, or transferring old data where the latest input data should be transferred. It must be prevented by all means.

Therefore, in actual operation, when data is input, the date and time at that time are stored together with the data so that the latest one can be easily identified even if there are a plurality of data. In addition, even on the side of the host computer, by processing the latest data after processing it, it is possible to design an application so as to prevent the mistake of forgetting to transfer from the HT.

Therefore, most HTs currently have a built-in clock. Since the built-in clock can read the current date and time by software, it is possible to read the date and time in the application software and store the date and time when the data was collected in the storage device.

[0005]

By the way, not only HT but all watches must be set to the correct time before use. The HT has a command to initialize the contents of the uncertain storage device at the time of factory shipment so that it can be used correctly, but as for the built-in clock, a clock that has some kind of correct time ticked like a general clock. This had to be adjusted, which made the user inconvenient.

The present invention has been made in view of the above-mentioned conventional example, and an object thereof is to provide an information processing system and method for always keeping the time of an internal clock accurate.

[0007]

In order to solve the above problems, the present invention has the following constitution. That is, a first time measuring means for measuring the date and time, a first communication means for communicating with an external device, and a transmitting means for transmitting the date and time measured by the first time measuring means by the communication means. Information processing apparatus, second time measuring means for measuring the date and time, second communication means for communicating with an external device, receiving means for receiving the date and time transmitted by the transmitting means, and receiving by the receiving means. The date and time is the second
And a second information processing device having setting means for setting the present time as the current time measured by the time measuring means.

As another aspect, the following configuration is provided. That is, a first time measuring means for measuring the date and time, a first communication means for communicating with an external device, a first transmitting means for transmitting the stored data by the communication means, and a current measuring means for the first time measuring means. A first information processing apparatus having a setting means for setting the date and time, a second timing means for timing the date and time, a second communication means for communicating with an external device, and a data transmitted by the transmitting means. Second receiving means for transmitting data to the first information processing means by the communication means when the data is received by the receiving means.
The information processing means of No. 3, and the setting means sets the date and time received by the communication means as the current time in the first clock means.

In addition, as another aspect, it has the following configuration. That is, first time measuring means for measuring the date and time, first communication means for communicating with an external device, first transmitting means for transmitting the date and time by the time measuring means by the communication means, and the first time measuring means. A first information processing device having setting means for setting the current date and time, and a second information processing device for timing the date and time
And a second communication means for communicating with an external device,
Receiving means for receiving the date and time transmitted by the first transmitting means, date and time received by the receiving means, and the second
Comparing means for comparing the difference with the date and time by the time measuring means, and as a result of the comparison by the comparing means, when the difference between the two is a predetermined value or more, the date and time measured by the second time measuring means,
Second information processing means having second transmitting means for transmitting to the first information processing means by the communication means, and the setting means uses the date and time received by the communication means as the current time. Set to 1 for timekeeping.

[0010]

With the above structure, the date and time measured by one clock can be transferred to the other clock and both can be kept at the same time.

[0011]

【Example】

[First Embodiment] A first embodiment will be described below with reference to the drawings.

<Device Configuration> FIG. 1 is a block diagram of a first embodiment of the present invention composed of a first information processing device 120 having an accurate time and a second information processing device 130 having no time set. It is a block diagram.

The first information processing apparatus 120 includes components having block numbers 100 to 104. First
The clock 100 has data 101 and other control commands 10
In addition to the above, the data creation device 103 for transmission converts the contents of the blocks 100 to 102 into a format for transmission, and the data is transmitted from the transmission / reception device 104.

The data output from the transmitting / receiving device 104 is transferred to the transmitting / receiving device 106 having an equivalent function via the cable 105.

The second information processing device 130 includes the constituent elements of block numbers 106 to 111. The transfer data received by the transmission / reception device 106 is discriminated by the data analysis device 107 in the type and content of the instruction, and branches from the next block number 108 to 111. The information of the first clock is sent to the second clock 10 by the instruction of the setting device 108.
9 is written. Other than the clock information, depending on the contents, it is sent to the data storage device 110 or other control command execution device to perform desired processing.

Next, as a more specific example, an embodiment will be shown in which a host computer is used as an information processing device having an accurate time and an information processing device handy terminal whose time is not set yet. FIG. 2 is a block diagram of a handy terminal (hereinafter referred to as HT) which is an embodiment of the present invention.

The CPU 6 includes a ROM 1 and a RAM 2 which will be described later.
Is for executing the program stored in the computer to control various devices connected to the bus to realize the present invention, and is included in the 16-bit microprocessor V40 manufactured by NEC in this embodiment. The CPU is operated at a clock frequency of 7.3728 MHz.

The ROM 1 stores information such as a basic OS program for HT and font data for display / printing that need not be rewritten. A program for executing the algorithm of this embodiment is stored in the ROM 1 in advance.

The RAM 2 has a program area for storing an application program downloaded from an external host computer, a work area necessary for executing the program, a data area for storing data, and a video R.
It has an AM area and the like. The contents of RAM2 are RO
Since the value is uncertain until the initialization program stored in M1 is executed, execution of this initialization program is instructed from the keyboard 4 which will be described later, or clears as will be described in this embodiment. The directory block must be transferred from the host computer.

The display 3 is an output device that uses a part of the RAM 2 as a video RAM and displays the fonts in the ROM 1 and arbitrary bit information as graphic information.

The keyboard 4 is an input device, and can notify the CPU 6 of the contents input by the operator.

The printer 7 is an output device for printing according to a command from the CPU 6, and is composed of a print head (not shown), print paper, and a paper feed device for feeding the print paper. A desired character can be printed by feeding the print paper after the font is developed into bits and sent to the print head to print on the print paper. It is also possible to print a user font, a graphic, or the like, which is not originally included in the font, by sending the print image to the print head after the print image is once bit-developed in the work area in the RAM 2.

The buzzer 8 is an output device that can be activated by a command from the CPU 6. By controlling the pitch and tone of the buzzer 8, various kinds of warnings can be given to the user.

The timer 5 is a time measuring device and is used not only as a real-time clock for managing the date / time, but also as a time-out process or a printing process for performing an exceptional process when a no-input state continues for a certain time or more. It is also used to determine the timing of the energization time of the print head, the paper feed speed, etc., and the time information can be acquired / set from the CPU 6. Each block of the HT of this embodiment is powered by a power supply device (not shown) to be driven, but the real-time clock of the timer 6 is constantly energized from the backup power supply in the power supply device, so that the CPU 6 and It is always running even if other blocks are stopped.

The baud rate generator 9 is an SCU which will be described later.
A device for setting / supplying 10 baud rates,
The baud rate RTCLK of various frequencies is selected by dividing the basic clock of 460.8 KHz by a maximum of 65535 by an instruction from the CPU 6, and the output terminal C is selected.
It can be output to LKOUT. Specifically, the timer / counter unit TCU # 1 incorporated in the NEC-made 16-bit microprocessor V40 is used.

The SCU (= serial control unit) 10 is a device for performing asynchronous serial communication, and the output terminal CL of the baud rate generator 9 described above.
It has a function of converting parallel data and serial data in synchronization with the baud rate RTCLK of the signal output from KOUT for transmission and reception, and at the same time, for interrupting the CPU 6 to complete transmission and reception. It also detects communication control signals /
It also has the function of controlling the reception permission with the device of the communication partner by operating. At the time of the parallel / serial conversion described above, the SCU 10 automatically converts the start bit and stop bit before and after the serial data, and the parity bit in some cases, so that the CPU 6 described later does not need to be aware of bits other than these data. Absent. This SCU
Similarly to the baud rate generator 9 described above, 10 also uses the one incorporated in a 16-bit microprocessor V40 manufactured by NEC, and TxD, RxD, SRDY among them is used.
Each signal line of is used for SD (transmission data), RD (reception data), RS (transmission request), and I / O 1
The signal line is used for CS (transmission possible: RS response).

The level converter 11 is the SCU 10 described above.
And a connector 12 which will be described later, for converting the signal voltage (CMOS level) of the SCU 10 and the voltage of the RS232C standard.

The connector 12 is for connecting to a detachable cable 14, which will be described later, and for electrically connecting the present HT to a host computer or another HT.

The I / O 13 is an HT which is an option such as a memory card reader / writer or a magnetic stripe reader (not shown).
Is for electrically connecting control / data signals to the CPU 6.

The 16-bit microprocessor V40 manufactured by NEC used in this embodiment does not limit the present invention and may be constituted by a CPU and peripheral circuits having similar functions.

FIG. 3 is an external view of the HT of this embodiment, in which the display device 3, the keyboard 4, the printer 7, and the connector 12 are arranged as shown.

FIG. 4 is an external view of the cable 14. The cable 14 is an HT connector 12 and a host computer (IBM PC / AT or compatible machine) RS23.
It is for connecting the D-SUB9P connector of 2C, but both are DTE (Data Terminal Equipment), so SD and RD, and CS and R in the middle of the cable.
The cross connection is such that S intersects.

The ferrite core 15 is for reducing noise that may occur during data transmission.

Both ends of the cable 14 are provided with a connector 16 for connecting to the HT and a connector 17 for connecting to a host computer (not shown).

The host computer is a PC / AT manufactured by IBM Corporation or a compatible machine, and the OS is MS-DOS manufactured by Microsoft Corporation. This computer has a real-time clock, and MS-
It is widely known that DOS manages date and time using this real-time clock.
That is, in the present embodiment, a technique regarding time acquisition by the host computer is known. Further, in this embodiment, it is assumed that an accurate date and time has already been set in the built-in clock of the host computer.

FIG. 5 shows a host computer and H in this embodiment.
It is a communication format used for communication between Ts. This format is based on a communication format generally called "Intel HEX format". In the present embodiment, the data that was originally represented as ASCII hexadecimal numbers in the Intel HEX format is represented in binary form to halve the amount of communication data to increase the communication speed. In addition, in the Intel HEX format, a 1-byte start symbol and a C-type end symbol are added to this format.
Two bytes of R and LF are added, but in this embodiment, no termination symbol is provided in order to reduce the amount of communication data. This is because the size of one block can be determined by referring to the data number n described later.

At the head of the block, the number of data n, which indicates the number of bytes of the data part d described later, is stored in a length of 1 byte. In this format, since only the data part d has a variable length, the number of bytes of the entire block can be obtained by referring to this value. As can be inferred from the fact that the number of data n is expressed by 1 byte, the size of the data part d is 0 bytes at the minimum and 255 bytes at the maximum.

Next, the offset hl is 2 bytes from the offset +1 from the beginning. This is the start address (0000
H to 0FFFFH), and h
Indicates the upper 8 bits and l indicates the lower 8 bits. In addition,
This value has no meaning when the type indicated by the block type t described later is other than the data block.

One byte at the position +3 from the beginning is the block type t. The block type indicates the meaning of the block, and in addition to the data block representing the content of the data itself, there are those shown in FIG. 4 described later.

The block portion d exists from the position +4 from the beginning and occupies an area from a minimum of 0 bytes to a maximum of 255 bytes. Specifically, the programs and data to be transferred are stored in this part.

The last 1 byte is the checksum c,
The value from the number n of data at the beginning to the end of the data part d is 1
It stores the 2's complement of the lower 1 byte of the sum obtained by adding each byte. In actual operation, the block receiving side, like the transfer side, calculates the checksum value from the beginning to the end of the data part, and transfers it by comparing it with the value of the sent checksum c. Check the validity of the data.

In this case, the only thing that can be determined is whether or not there is an error in the block that has been sent, and it is not possible to guess the location of the erroneous data and correct it. Therefore, it is effective to provide an error recovery means such as retransmitting a block when an erroneous block is transferred, but it is not a limitation in carrying out the present invention, and in general communication technology. It is known.

Furthermore, this format itself does not limit the present invention and is applicable to all formats capable of sending data and commands.
Of course, it is apparent that the conventional Intel HEX format can also be applied by expanding the command.

FIG. 6 is a list of the block types t described above. The block type 0 means the command for data transfer described in the above description.

The block type 1 is an end block command which means the end of communication, and the receiving side executes the end processing of communication. As described above, the offset within the block does not make sense in the subsequent blocks.

Block type 2 is an extended address block. Since the offset hl in the block is 16 bits, only a maximum of 64 KB can be specified. 64K
Intel's 808 to specify addresses B and above
Similar to the concept of 6 CPU segment, address A19
16 addresses from A to A4 are designated.

Block types 3 and later are specially provided for this embodiment, and are different (or newly added) from the block types originally defined in the Intel HEX format. First, the block type 3 is a header block, and when a special work area is required in the RAM 2 when executing the program transferred in the data block, the work area is secured by the value given in this header block. belongs to.

The block type 4 is a change directory block, which is defined to enable the directory described in the data section d and thereafter perform data transfer to that directory.

The block type 5 is a clear directory block, which is used as a code for initializing a directory for storing data / program in the RAM 2 of the HT main body. Therefore, even if the consistency of the directory data structure of the RAM 2 is not maintained at the time of factory shipment, when the program is downloaded from the host computer, this block is sent first to automatically initialize and store the program as well. You can

The block type 6 is a block type indicating a date / time block which is a newly provided command. This will be described with reference to the following figure.

FIG. 7 shows the format of the date / time block. Since it is based on the block structure in FIG.
The explanation will be given again using the name in. First, the number of data n is always 06H because the size of the data part d is fixed at 6 bytes. The subsequent offset hl is always 0000H, but this is not a particularly significant value, but a value for standardizing the format. The block type t has a value 06H indicating that it is a date / time block. Next data part d
The date and time are stored in 6 bytes in total. Specifically, it is in BCD format, and the date is a 2-digit year (the lower two digits of the year).
Digit), month 2 digits, day 2 digits, time is 2 digits, minute 2 digits,
It consists of two digits per second. For example, at 3:04:56 on January 2, 1993, "93H, 01H, 02
It is shown by 6 bytes of H, 03H, 04H, 56H ". Finally, there is a checksum c of 1 byte.

In the present embodiment, the date / time information is transmitted using the above format.

FIG. 8 is a list of control codes necessary for establishing the flow control and other communication procedures necessary for communication between the host computer and the HT in the above block format. Eight codes are prepared.

STX is a synchronization code sent from a series of block transfer destinations, and is specifically used to confirm the hardware connection of both transmission and reception.

ENQ is a start code indicating the start of 1-block transfer, and must be transmitted one block before the block described in FIG.

EOT is a transfer end code sent from the receiving side to the transmitting side when it is desired to interrupt the receiving process for some reason during the transfer. Upon receiving this, the sending machine must immediately interrupt the transmission and perform an appropriate closing process.

ESC is a quoting code for avoiding control codes. Unlike the Intel HEX, since the binary format value is sent in the communication format used in the present embodiment, it may be possible to send the data having the same value as the control code. In such a case, such data is sent together with the ESC to be used for distinguishing the data from the control code. Now, assuming that the code of the data to be sent is x, firstly E
After sending 1 byte of SC, 1 byte of (x + 20H) is continuously sent. If ESC appears in the data on the receiving side, reject this value and perform processing such that the value obtained by subtracting 20H from the 1-byte data sent next is treated as true data, and the same value as the control code. I can send and receive the data of. In addition, all the codes of the control codes used in the present embodiment are set to values that do not overflow even if 20H is added.

ACK is a block reception affirmative code and is 1
This is an affirmative code sent from the receiving side to the transmitting side when the block is received and the checksum value calculated by the receiving side becomes equal to the sent checksum value.

NAK is a block reception negative code. This is a code having the opposite meaning of the above-mentioned ACK, and is a negative code sent to the transmitting side when the sent data is incorrect. In actual operation, when a NAK is sent, the sending side must perform error recovery processing such as resending the block.

XON and XOFF are flow control codes. This is a code for instructing suspension / resumption of transmission when the processing on the receiving side cannot catch up with the processing on the transmitting side. This is also well known in the field of general communication technology, and therefore detailed description thereof will be omitted.

FIG. 9 is a flow chart showing an algorithm used when transmitting the above blocks.

Step S01 is a step of sending an ENQ code for instructing the start of transfer prior to transmission of a block. Specifically, the ENQ code is output after checking the RS signal of RS232C to confirm that the CS signal on the receiving side is active.

Next, in step S02, the blocks prepared in the buffer are transferred byte by byte from the beginning. The transfer means is performed by writing to the serial port as described in step S01.

In step S03, 1 byte of the code indicating whether or not the data has been correctly received from the receiving side is received, and in step S04 it is checked whether the code is ACK. The process returns to step S01 to retransmit.

As described above, the block prepared in the host computer can be transmitted.

Next, FIG. 10 shows an algorithm used when receiving the block sent by the algorithm of FIG.

In step S11, a waiting state for the block start code ENQ sent from the transmitting side is set. That is, the CS signal of the SCU 10 is activated and the transmission permission is transmitted to the host computer. If ENQ is sent, the block is received in RAM 2 in step S12.
Expand to the internal buffer. As is apparent from the format of FIG. 4, the size of one block can be determined by receiving the data portion d indicated by the value of the number of data n at the head of the block and the fixed length data portions before and after the data portion d. After receiving all one blocks, the two's complement of the sum from the beginning of the block to the end of the data portion is calculated in step S13, and this value is compared with the checksum present at the end of the block in step S14. As a result, if the two values are equal, ACK is transferred in step S15, and if they are not equal, NAK is transferred in step S16.

The blocks sent as described above can be stored in the buffer prepared in the RAM 2.

FIG. 11 is a flow chart showing a transmission algorithm used when transferring data from the host computer to the HT in this embodiment.

First, at step S21, ST is set to ST.
Send X. The sending and receiving connections are correct,
The HT in the waiting state receives A immediately after receiving STX.
Since CK is returned, in the subsequent step S22, this AC
Wait until K is sent from the receiving side. However, since STX cannot be transmitted when there is no hardware connection such as disconnection of a communication cable or when there is a difference in communication speed, data length, or type of parity bit, AC cannot be transmitted.
K is not returned to the transmitting side, and an endless loop is entered in step S22. Therefore, in actual operation, if the ACK is not returned even after a certain amount of time, the loop must be interrupted and error processing must be performed, but since the technology for that is already known in the field of communication, it is described in this flowchart. Absent.

When the connection between the host computer and the HT is confirmed, the date / time block is transferred in step S23.

Next, in step S24, it is checked whether or not there is data to be transmitted. Originally, this transmission routine is for data transfer, but a branch process is executed here when it is desired to transfer only date / time data. As a matter of course, it goes without saying that the receiving program for this transmitting program is designed so as not to hinder the operation even if the extended address block / data block does not exist.

In step S25, the segment value of the storage address of the data to be sent is transmitted using the extended address block. The extended address block is a block having the value shown in FIG. 6 as the block type and the segment value in the data part, and the block itself is transferred by the algorithm shown in FIG. Next, in step S26, the data block is transferred. Data block size is 64
If it exceeds KB, the process goes from step S27 to step S25 again, a new segment is retransmitted, and data transfer is repeated.

When all the data has been sent, the end block is finally sent in step S28 to notify the receiving side of the end of the transmission.

Next, FIGS. 12 and 13 are flow charts showing an algorithm used when receiving the data sent in FIG.

First, in step S31, it waits for STX which means the start of transmission to be sent. When STX is received, ACK is returned in step S32 to notify the transmitting side that reception is ready. Then step S3
The block sent in 3 is stored in the reception buffer in the RAM 2, and then the analysis is started.

First, in step S34, it is checked whether the transmitted block is an extended address block. Specifically, the judgment is made by checking the value of the block type at the position of +3 from the head of the block. When the block type is the extension block, the storage segment address is set in step S35, and then step S3 is performed again.
At 3, the next block is received.

If it is not an extended address block, it is checked in step S36 if it is a data block.
If it is a data block, the data portion is transferred from the reception buffer to the designated address of the program / data storage directory in step S37. The segment value of the address at this time is the value specified in the previous extended address block, but shows 0000H by default.

If it is not a data block, step S
At 38, it is checked whether it is a date / time block. If the block is a date / time block, the contents of the data portion are set to the real-time clock built in the timer 5 in step S39, and the next block is received again in step S33.

If it is not a date / time block, it is checked in step S40 if it is an end block. In the case of the end block, the device is closed in step S41 and the reception process is completed.

If the block is not any of the above blocks, the process goes to step S42 in FIG. 12 to continue to judge whether the block type is the remaining block type.

In step S42, it is checked whether or not it is a header block, and when it is a header block, a work area in the program / data storage directory is secured, and then again in FIG.
It returns to step S33 of 2.

If it is not a header block, step S
Check whether it is a change directory block at 44,
In that case, the directory for storing the data is changed in step S45, and the process returns to step S33.

If it is not a change directory block, it is finally checked in step S46 if it is a clear directory block. If it is a clear directory block, the directory written in the data section is initialized, and then the process returns to step S33.

If the block is not a change directory block in S46, it does not correspond to any of the defined block types, so that nothing is done and the process returns to step S33 to receive the next block.

As described above, in the present embodiment, the date and time are received together with the data sent from the host computer.
Since the time information can also be received, the time information of the host computer is correctly set in the HT each time data is received from the host computer. Further, as described above, the date / time information can be transmitted / received independently.

In the present embodiment, the file structure on the HT side was not particularly described, but for example, MS-DOS of Microsoft, which is widely used worldwide, is used as the OS.
Assuming that an auxiliary storage medium such as a RAM disk is used, each file in the RAM disk has the date and time of creation as a file attribute (time stamp). Therefore, the clock built into the HT must be set correctly before the file transfer, but in this embodiment, the date and time are sent prior to the file transfer, as is clear from the algorithm of FIG. The present invention is also effective for an HT using an OS having a different time management system.

[Second Embodiment] In the first embodiment, when the program or data is downloaded from the host computer to the HT, the date and time of the built-in clock of the HT are automatically set. However, in actual operation, the data is transferred from the host computer to the HT only when the application program is changed or when the customer management master file is updated, so the opportunity is very small. It was

As described above, if there are few opportunities to set the time from the host computer, in the unlikely event that a malfunction of the processing program causes the clock in the HT to be shifted due to a hardware error, it will take considerable time to correct it. There was a problem that it would take a long time.

On the other hand, a second embodiment of the present invention in which the time information is transferred from the host computer to the HT when the data is uploaded from the HT to the host computer will be described below.

14 and 15 are flowcharts showing the algorithm of communication between the host computer and the HT. First, FIG. 14 shows the processing on the host computer side, and step S51 is a loop for holding STX sent from the HT, and subsequent step S5.
Step 2 is a step of sending an ACK code for permitting block reception to the HT. Incidentally, these steps correspond to steps S31 and S32 of the first embodiment. The next step S53 is a module for block reception, which is also the steps S33, S35, S of the first embodiment.
36, S37, S40, S41,
It is a module that determines and processes extended blocks, data blocks, and end blocks.

When the data transfer from the HT to the host computer is completed, the date / time block is transmitted in the following step S54. This is also the step S in the first embodiment.
It corresponds to 26. Finally, in step S55, the end block is transmitted to the HT to end all communication.

On the other hand, the processing on the HT side is shown in FIG.
First, in step S61, the STX code instructing the start of transmission is transmitted to the host computer. Step S5
The host computer receiving the STX in 1 sends back an ACK in step S52, so that the HT loops until the ACK arrives in step S62. The next step S63 is a module for transferring the data in the HT to the host computer, and is specifically realized by performing the same processing as steps S23, S24, S25 and S27 in the first embodiment.

By the above processing, the host computer transmits the date / time block in the above step S54, and this is received in step S64 corresponding to steps S38 and S39 of the first embodiment, and the date and time block is received by the clock built into the HT. By setting the time, the HT clock can be set correctly. Finally, in step S65, after waiting for the end block, all communication is terminated.

As described above, in this embodiment, at the opportunity of uploading data from the HT to the host computer,
Transfers time information from the host computer to the HT,
It is also possible to set a built-in clock.

[Third Embodiment] Not limited to the HT, there is generally some error with the timepiece. Therefore, for example, it is important in actual operation to periodically reset the time to the correct time. However, for some reason (for example,
The temperature of the place where the HT was left unattended), the time may deviate more than usual. In addition, an error may occur due to a failure of the real-time clock, and in that case, the processing must be performed immediately.

However, such a defect is a phenomenon that rarely occurs normally, and therefore it is not actually performed because it is inefficient for the operator to check it every day. Therefore, if something like this should happen,
The error becomes large without anyone noticing it, which eventually hinders the operation of the system.

Therefore, a system will be described below in which the time is automatically reset and the operator is warned when the error in the HT built-in clock becomes larger than a certain level.

16 and 17 show a host computer and H
7 is a flowchart showing an algorithm for communication with T. First, FIG. 16 shows the processing on the host computer side. Steps S71 to S74 are the steps S51 to S54 in the second embodiment.
Is equivalent to.

After the time of the real time clock of the HT is read by the above processing, it is checked in step S75 whether this value is an appropriate value. Specifically, the time is compared with the time of the real-time clock on the host computer side, and it is determined whether the difference is within a predetermined allowable range (for example, 1 minute).

As a result, when the HT time is deviated, the time on the host computer side is transferred in step S76,
In step S77, the fact that the HT clock has shifted is output to an output device such as a CRT, and an operator is warned. Next, in step S78, the end block is transmitted, and all communication is terminated. If the HT time is not shifted, the process proceeds from step S76 to step S78, and similarly all the processes are finished.

Next, the processing on the HT side is shown in FIG. Steps S81 to S84 correspond to steps S61 to S64 in the second embodiment. This allows the HT to upload data and time information to the host computer.

As described above with reference to FIG. 16, the host computer next transfers the date / time block or end block. Therefore, after receiving one block in step S85, the block type is determined in step S86.
If the block is a date / date / time block, the process proceeds to step S87 to set the time information included in the data portion to the real-time clock in the timer 5. Next, in step S88, the operator is notified that the clock has been set, and finally in step S89, the end block is received and all the processes are ended. If the block is not the time / date block in step S86, the process proceeds to step S89, and similarly all processes are finished.

As described above, by using this embodiment, the correct time can be transferred only when the time of the HT is deviated. In addition, it is possible to detect a defect in the real-time clock of the HT by notifying the operator that there is a deviation.

[Embodiment 4] In all of the above examples, the time of the host computer is directly transferred to the HT. However, since the communication device that actually connects the host computer and the HT uses RS232C that is serial communication, it requires some time for transfer although it is very small. Further, a certain amount of processing time is required to create a date / time block to be transmitted on the host computer side, analyze the block received on the HT side, and write it in the real-time clock. Therefore, no matter how accurate the host computer has the time information, it will be
Although the time set to is a little, it will logically shift. Therefore, in this embodiment, a method of transferring date / time information in consideration of these overheads will be described.

FIG. 18 shows an algorithm of date / time block transmission used in this embodiment, which corresponds to step S23 and the like in the above-described embodiments.

First, in step S91, the current time is acquired from the real-time clock of the host computer.
This is performed using the function prepared in MS-DOS. Next, in step S92, a precalculated offset is added to the time obtained in step S91 in order to correct the time required to transmit the time information and set the real time clock of the HT. For this offset, for example, a negative value of the time required for actual transfer can be used. A date / time block is created in step S93 based on the corrected time, and finally transmitted in step S94.

The above processing is performed in the "date / date
By substituting "transmission of time block", it becomes possible to transmit accurate time in consideration of communication time lag.

Next, a method of correcting the time lag by the algorithm on the receiving side and realizing it will be described. FIG. 19 shows an algorithm of date / time block reception used in the present embodiment, and steps S33 and S of the previous embodiments.
38 and S39. First, step S
The date transferred from the host computer at 101
The time block is received, and the date / time is acquired from the data part in the communication format in step S102. Next, in step S103, a pre-calculated offset is added to the time obtained in step S102 in order to correct the time required for transmission and setting. This offset is
For example, a negative value of the time required for actual transfer can be used. Finally, the date / time corrected in step S104 is set in the HT real time clock.

By replacing the above processing with the "reception / setting of the date / time block" in the first to third embodiments, it is possible to transmit the accurate time in consideration of the communication time lag.

Note that it is not always necessary to use both the transmission / reception algorithms shown in FIGS. 18 and 19, and either of the correction values used in steps S92 and S103 determines the time required for the entire transmission / reception processing. The present embodiment can be realized by only one of the processes as long as it is corrected.

Further, the offset added in steps S92 and S103 is not only for correcting the time required for communication / setting, but for example, when shipping an HT for overseas export from a factory, the offset between Japan and overseas is set. It is also possible to intentionally shift the HT time by adding the time difference as an offset.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0114]

As described above, the information processing system and method according to the present invention have an effect that the time of the built-in clock can always be kept accurate. Further, since the date / time information can be received together with the data sent from the host computer, the time information of the host computer is correctly set in the HT each time the data is received from the host computer. Also, as mentioned above,
It is also possible to send and receive the time information independently. Also,
It is also possible to transfer the time information from the host computer to the HT and set the clock built in the HT at the opportunity of uploading the data from the HT to the host computer. Also, the correct time can be transferred only when the HT time is deviated. In addition, it is possible to detect a defect in the real-time clock of the HT by notifying the operator that there is a deviation. Further, it becomes possible to accurately transmit the time in consideration of the communication time lag.

[0115]

[Brief description of drawings]

FIG. 1 is a block diagram of an HT system according to an embodiment.

FIG. 2 is a block diagram of an HT according to an embodiment.

FIG. 3 is an external view of an HT of an example.

FIG. 4 is a diagram of a communication cable for connecting an HT host computer.

FIG. 5 is a diagram showing a format of a block.

FIG. 6 is a diagram showing a list of block types.

FIG. 7 is a diagram showing a format of a date / time block.

FIG. 8 is a diagram showing a list of codes.

FIG. 9 is a flowchart showing a block data transmission algorithm.

FIG. 10 is a flowchart showing a block data reception algorithm.

FIG. 11 is a flowchart (host computer side) showing a data transmission algorithm of the first embodiment.

FIG. 12 is a flowchart (HT side) showing a data reception algorithm of the first embodiment.

FIG. 13 is a flowchart (HT side) showing the data reception algorithm of the first embodiment.

FIG. 14 is a flowchart (host computer side) showing a data reception algorithm of the second embodiment.

FIG. 15 is a flowchart (HT side) showing the data transmission algorithm of the second embodiment.

FIG. 16 is a flowchart (on the side of the host computer) showing the data reception algorithm of the third embodiment.

FIG. 17 is a flowchart (HT side) showing the data transmission algorithm of the third embodiment.

FIG. 18 is a flowchart (on the side of the host computer) showing the date / time block transmission algorithm of the fourth embodiment.

FIG. 19 is a flowchart (HT side) showing a date / time block reception algorithm of the fourth embodiment.

[Explanation of symbols]

 1 ROM 2 RAM 5 Timer 6 CPU 10 SCU 12 Connector 13 I / O 14 HT-Host Cable 100 Clock 120 First Information Processing Device 130 Second Information Processing Device

Claims (18)

[Claims] 1. A first clocking means for clocking the date and time, a first communication means for communicating with an external device, and a transmitting means for transmitting the date and time clocked by the first clocking means by the communication means. A first information processing device having; a second timing unit for timing the date and time; a second communication unit for communicating with an external device; a receiving unit for receiving the date and time transmitted by the transmitting unit; And a second information processing device having setting means for setting the date and time received by the second time measuring means as the current time measured by the second time measuring means. 2. The information processing system according to claim 1, wherein the transmitting unit corrects a delay time of the communication unit and transmits the date and time. 3. The information processing system according to claim 1, wherein the receiving unit corrects the delay time of the communication unit with respect to the date and time of reception. 4. A first time measuring means for measuring a date and time, a first communication means for communicating with an external device, a first transmitting means for transmitting stored data by the communication means, and a first time measuring means. A first information processing apparatus having a setting means for setting the current date and time, a second timing means for timing the date and time, a second communication means for communicating with an external device, and the transmission means. A receiving means for receiving the data, and a second transmitting means for transmitting the date and time measured by the second timing means to the first information processing device by the communication means when the data is received by the receiving means. An information processing system, comprising: a second information processing device having; wherein the setting unit sets the date and time received by the communication unit as the current time in the first time counting unit. 5. The information processing system according to claim 4, wherein the second transmitting unit corrects the delay time of the communication unit and transmits the date and time. 6. The information processing system according to claim 4, wherein the setting unit sets the current date and time after correcting the delay time by the communication unit with respect to the date and time received by the first communication unit. . 7. A first timing unit for timing the date and time, a first communication unit for communicating with an external device, a first transmission unit for transmitting the date and time by the timing unit by the communication unit, and the first unit. A first information processing device having setting means for setting the current date and time to the clocking means, second clocking means for clocking the date and time, second communication means for communicating with an external device, and the first transmission Receiving means for receiving the date and time sent by the means, comparing means for comparing the difference between the date and time received by the receiving means and the date and time by the second clock means, and the result of the comparison by the comparing means, When the difference is equal to or more than a predetermined value, the second information processing including a second transmission unit that transmits the date and time measured by the second timing unit to the first information processing apparatus by the communication unit. Device,
The information processing system according to claim 1, wherein the setting unit sets the date and time received by the communication unit as a current time in the first clocking unit. 8. The information processing system according to claim 7, wherein the second transmitting unit corrects the delay time of the communication unit and transmits the date and time. 9. The information processing system according to claim 7, wherein the setting unit sets the current date and time after correcting the delay time by the communication unit with respect to the date and time received by the first communication unit. . 10. An information processing method in a system in which a host computer and a terminal device are connected by a communication line, the method comprising: a reading step for reading the date and time from a reference clock of the host computer; and a date and time read by the reading step. An information processing method comprising: a transmitting step of transmitting to the terminal device via a communication line; and a setting step of setting the date and time transmitted by the transmitting step in a clock of the terminal device. 11. An information processing method in a system in which a host computer and a terminal device are connected by a communication line, comprising a data transmitting step of transmitting data possessed by the terminal device to the host computer, and transmitting by the data transmitting step. When the data is received, the reading step of reading the date and time from the reference clock of the host computer, the transmitting step of transmitting the date and time read by the reading step to the terminal device through a communication line, and the transmitting step A setting step of setting the transmitted date and time in a clock of the terminal device. 12. A method of processing information in a system in which a host computer and a terminal device are connected by a communication line, the data transmitting step of transmitting the current time of a clock of the terminal device to the host computer, and the data transmission. When the date and time transmitted by the step is received, a reading step of reading the date and time from the reference clock of the host computer, a comparing step of comparing the date and time read by the reading step with the received date and time, and a comparing step of the comparing step. As a result of the comparison, if there is a difference of not less than a predetermined value, the step of transmitting the read date and time to the terminal device via a communication line, and the date and time transmitted by the transmitting step are stored in a clock of the terminal device. An information processing method comprising: a setting step of setting. 13. A first time measuring device having a correct date and time, a first information processing device having the first time measuring device, and a second time measuring device capable of arbitrarily setting time. A second information processing apparatus having the second clocking apparatus, a communication apparatus capable of communicating between the first information processing apparatus and the second information processing apparatus, and a program using the communication apparatus. A program / data transmission device capable of transmitting data, and a time information transmission device capable of transmitting time information using the communication device, wherein a program / data transmission device using the program / data transmission device is provided.
When transmitting data, the first information processing device also transmits the information of the first clock device using the time information transmission device, and the second information processing device transmits the transmitted time information to the second clock device. An information processing system characterized by setting to. 14. When the program / data transmission device transmits the program / data of the second information processing device to the first information processing device, the time information of the first clock device is used by using the time information transmission device. 14. The information processing apparatus according to claim 13, wherein the information is transmitted to the second information processing apparatus. 15. The time information of the first timekeeping device and the second time information of the first timekeeping device.
The time information of the first time measuring device is transmitted to the second information processing device by using the time information transmitting device when the time information of the second time measuring device is compared and a difference of a certain degree or more occurs. The information processing apparatus according to claim 13, 16. The first information processing device transmits a value obtained by correcting the time information of the first clock device to the second information processing device by using the time information transmission device. The information processing device according to claim 13. 17. The information processing apparatus according to claim 13, wherein the second information processing apparatus sets a value obtained by correcting the transmitted time information in the second time measuring apparatus. 18. The information processing apparatus according to claim 13, wherein when there is no information to be transmitted by the program / data transmission device, only the information of the first clock device is transmitted.