JPH07319693A - Pipeline processing method - Google Patents

Abstract

(57) [Abstract] [Purpose] In a pipeline processing device that pipelines an instruction, if a load instruction and an instruction to be executed next to the load instruction have a data dependency relationship, the operation of the next instruction is performed. Reduce waiting time. [Structure] Before the cache hit judgment of the load instruction is known, the data from the cache is sent to the instruction to be executed next to the load instruction to execute the operation in advance. When the load instruction causes a cache miss, the next instruction is returned to the stage before the operation stage. The operation of returning the next instruction to the stage before the operation stage is performed during the block transfer generated by the cache miss of the load instruction. According to the present invention, since the operation waiting time of the instruction following the load instruction is shortened, the processing speed of the pipeline processing device can be improved. Further, even when the data read stage and the stage where the hit judgment is known are separated, the penalty does not increase and the processing speed can be prevented from decreasing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention, in a pipeline processing apparatus for dividing each instruction into a plurality of stages and performing pipeline processing, passes data read by a load instruction to other instructions at high speed for processing. The present invention relates to a pipeline processing device.

[0002]

2. Description of the Related Art In a conventional pipeline processing apparatus, each instruction has an instruction read stage (IF stage), an instruction decode stage (D stage), and an instruction operation stage (E).
Stage), memory access stage (A stage),
The processing is divided into six stages, that is, an instruction cancel stage (N stage) and a write stage (W stage).

FIG. 8 shows a block diagram of a conventional pipeline processing apparatus.

Each stage has a holding circuit 2, 3, 4, for holding the address, data and instruction of each stage.
5, 6, 7, 14, 16, 19, 10, 26, and I
The F stage is provided with a program counter 8 for counting a program, the D stage is provided with a detection circuit 24 for detecting a data dependency relationship with a preceding instruction, and the E stage is provided with an arithmetic unit 15 for performing instruction arithmetic. The determination circuit 2 for determining the hit of the data cache 17 in the N stage
It has 0. The instruction is read from the instruction cache memory 9 in the IF stage, and the data is read from the data cache memory 17 in the A stage.
Further, reading from the register file 21 is performed at the D stage, and writing to the register file 21 is performed at the W stage. Further, a bypass 119 for sending the data read from the data cache 17 is provided between the N stage and the D stage.

In the instruction sequence shown in FIG. 2, first, a load instruction, which is the first instruction, adds the data in register x and the data in register b, and the addition result is used as the read address of the data cache to register the data at that address. Then, the second instruction, that is, the add instruction, is read to the register r1.
And the data in the register r2 are added, and the addition result is written in the register t.
Here, the first instruction and the second instruction have a data dependency relationship via the register r1.

FIG. 9 shows a time chart in the case where the load instruction which is the first instruction causes a cache hit when the instruction sequence of FIG. 2 is processed in the pipeline processing apparatus according to the prior art, and FIG. Shows a time chart when the load instruction which is the first instruction causes a cache miss.

The concrete operation of the conventional pipeline processing apparatus will be described below with reference to the drawings by taking the instruction sequence of FIG. 2 as an example.

First, the load instruction which is the first instruction is read from the instruction cache 9 in the IF stage. Then the first
In the D stage, the load instruction, which is the instruction of, reads out the data of the register x and the data of the register b from the register file 21 to the data lines 131 and 110, respectively, and selects the data lines 131 and 110 by the selection circuits 12 and 13, respectively. Output to 111 and 112. At this time, the add instruction which is the second instruction is read from the instruction cache 9 in the IF stage. The load instruction, which is the first instruction, performs addition in the arithmetic unit 15 using the data 111 and 112 at the E stage, and the read address 11 of the data cache.
5 is output. At this time, the addition instruction which is the second instruction is D
At the stage, the data of the register r1 and the data of the register r2 are respectively transferred from the register file 21 to the data line 13
1, 110 are read. Here, as shown in FIG. 2, since there is a data dependency relationship between the load instruction which is the first instruction and the addition instruction which is the second instruction via the register r1, the data dependency relationship is detected in the detection circuit 24. Is detected. When it is detected that there is a dependency, the add instruction which is the second instruction reads the data in the register r1 because the register r1 has not been updated by the load instruction which is the first instruction at this point. Since the old data has been output to the data line 131 that is in operation, the data is not sent to the E stage, which is the instruction operation stage, and is held by the stage lock signal 129 at the immediately preceding D stage. The load instruction, which is the first instruction, is continuously processed regardless of the presence or absence of data dependency, and the output result 115 from the E stage is used in the A stage to read the data 117 from the data cache 17 as the data cache read address 116. The selection circuit 27 selects the data 117 and sends it to the N stage data holding circuit 19, and reads the physical addresses 118 and 133 from the data address tag 18 and the data TLB 28, respectively.
It is sent to the hit determination circuit 20 which determines the cache hit of the load instruction which is the first instruction.

Here, when the load instruction which is the first instruction is found to be a cache hit by the hit determination circuit 20 in the N stage, the stage lock signal 129 is released, and the cache memory 17 is valid for the N stage. The data has been read. The first instruction, the load instruction, immediately sends the valid data from the N stage to the D stage through the bypass 119. The load instruction also writes the valid data 119 to the register r1 at the W stage. When the valid data 119 corresponding to the register r1 is sent from the N stage, the add instruction which is the second instruction selects the sent data 119 by the selection circuit 12 and outputs it to the data line 111. , The data 110 of the register r2 already read from the register file 21 at the D stage is selected by the selection circuit 13 and output to the data line 112. The add instruction, which is the second instruction, is the E stage and the output data 11 from the D stage.
The arithmetic unit 15 performs addition using 1 and 112, and outputs the addition result 115. Then, at the N stage, the data 116 as the addition result is selected by the selection circuit 27, and at the W stage, the addition result is written in the register t.

When a load instruction which is the first instruction causes a cache hit in the pipeline processing device according to the conventional technique, the addition instruction which is the second instruction has a penalty of two cycles.

On the other hand, when the load instruction, which is the first instruction, is found to be a cache miss in the N stage, invalid data is read from the cache memory 17 in the N stage, so the load instruction is valid. Block transfer is performed to read data to the N stage, and the block is held in the N stage by the stage lock signal 126 during the block transfer. The add instruction, which is the second instruction, is continuously held in the D stage by the stage lock signal 129 until valid data is read to the N stage by the block transfer. When the block transfer is completed after a plurality of cycles after the cache miss is found, the stage lock signals 126 and 129 are released, and valid data is read out to the N stage where the load instruction which is the first instruction exists. ing. The first instruction, the load instruction, sends valid data from the N stage to the D stage through the bypass 119 when valid data is read to the N stage. The load instruction writes valid data 119 in the register r1 at the W stage. When the valid data 119 is sent from the N stage to the D stage, the add instruction, which is the second instruction, selects the sent data 119 by the selection circuit 12 and outputs it to the data line 111. The selection circuit 13 selects the data 110 of the register r2 read from the register file 21 in the D stage and outputs it to the data line 112. The second addition instruction is E
In the stage, output data 111, 11 from the D stage
2 is used to perform addition in the arithmetic unit 15, and the addition result 11
5 is output. Then, at the N stage, the data 116 as the addition result is selected by the selection circuit 27, and at the W stage, the addition result is written in the register t.

When a load instruction which is the first instruction causes a cache miss in the pipeline processing apparatus according to the prior art, the addition instruction which is the second instruction has a penalty of 2 cycles + block transfer cycle.

Generally, in the data read of the data cache and the hit judgment of the data cache, the hit judgment of the data cache is slower. For example, in the direct map data cache 17, at the same time as reading the data 117, the address 118 where the data 117 existed is read from the data address tag 18 and the hit determination is performed using the address 118. Since it takes a long time to output the hit determination result 123 in the hit determination circuit 20 that performs the hit determination, the data read 117 of the data cache 17 and the hit determination 123 of the data cache 17 are better in the hit determination 123 of the data cache 17. Become slow.

The above-mentioned conventional example shows a case where the hit determination is one cycle later than the data reading.

However, in recent years, there has been a demand for a pipeline processing device which has a higher speed. If the pipeline processing device is speeded up, the time for one cycle is shortened, the delay of the hit determination circuit for performing the hit determination becomes more severe, and the hit determination result cannot be output in one cycle. It may be delayed by two cycles or more until the hit determination result is known. Here, if the hit determination is two cycles later than the data read, the penalty of the addition instruction, which is the second instruction, is 1
Cycle increase.

FIG. 13 shows a time chart at the time of a cache hit in the pipeline processor according to the prior art when the hit determination is delayed by two cycles from the data read. As shown in FIG. 13, the add instruction, which is the second instruction at this time, has a 3-cycle penalty. FIG. 14 shows a time chart at the time of a cache miss. As shown in FIG. 14, the addition instruction at this time is 3 cycles + block transfer cycle penalty.

[0017]

The penalty at the time of a cache hit of an instruction string as shown in FIG. 2 is the most important in terms of performance. In the above-mentioned conventional example, the penalty at the time of a cache hit is a 2-cycle penalty, but it is necessary to further reduce this penalty.

Further, in the above-mentioned conventional example, if the stage for reading the data from the data cache and the stage for making the hit determination are separated from each other due to speeding up of the processing, the penalty at the time of cache hit increases and the performance deteriorates.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a pipeline processing device that eliminates excessive holding of a second instruction.

[0020]

The invention according to claim 1 is the first
If there is a data dependency between the load instruction that is the first instruction and the second instruction that is to be executed next, the data read from the data cache by the load instruction that is the first instruction is This instruction is sent from the stage prior to the stage where the cache hit determination of the load instruction is clear to the stage before the operation stage. Specifically, a bypass that sends the data read by the load instruction, which is the first instruction, to the stage before the operation stage before the hit judgment of the cache becomes clear, and the data sent through the bypass to the operation stage. And a control means for controlling so as to perform a feed calculation.

According to the second aspect of the present invention, when the load instruction which is the first instruction is found to be a cache miss, the load instruction which is the first instruction sends data to the second instruction through the bypass in advance. The second instruction sent up to and after the operation stage is re-executed from the stage before the operation stage. Specifically, in the configuration of claim 1, when the load instruction which is the first instruction causes a cache miss, a path for returning the second instruction to the stage before the operation stage and a path for sending the second instruction are sent through the path. And a control means for controlling the second instruction to be re-executed.

According to the third aspect of the invention, the second instruction is returned to the stage prior to the operation stage during the block transfer generated by the cache miss of the load instruction which is the first instruction, and the second instruction is returned to the stage before the operation stage. The configuration is such that the second instruction immediately receives the read valid data when the block transfer is completed, and the operation is ready to be executed.

[0023]

According to the structure of the first aspect of the present invention, when there is a data dependency relationship between the load instruction which is the first instruction and the second instruction, the data read from the cache is judged as a cache hit. Since it is sent before the operation stage before it is known, the second instruction can execute the operation in advance, and the excessive holding of the second instruction at the time of cache hit is eliminated.

According to the configuration of the second aspect of the present invention, when the load instruction which is the first instruction causes a cache miss, it is possible to re-execute the second instruction that has been sent up to and after the operation stage, and the normal operation is performed. Operation is guaranteed.

According to the invention of claim 3, the operation of returning the second instruction to the stage before the operation stage and holding it in the stage before the operation stage is during the block transfer of the load instruction which is the first instruction. When the block transfer is completed, the operation of the second instruction is immediately executed, so that the operation of claim 2 does not result in an increase in penalty.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 shows the configuration of a pipeline processing apparatus according to the first and second aspects of the present invention as a first embodiment.

In the pipeline processing apparatus according to the first embodiment, each stage has an address of each stage,
Holding circuits 2, 3, 4, 5, 6, for holding data and instructions,
7, 14, 16, 19, 10, 26, the IF stage is provided with a program counter 8 for counting a program, the D stage is provided with a detection circuit 24 for detecting a data dependency relationship with a preceding instruction, and E is provided. The stage is provided with an arithmetic unit 15 for performing an instruction operation, and the N stage is provided with a determination circuit 20 for performing a data cache hit determination. The instruction is read from the instruction cache memory 9 in the IF stage, and the data is read from the data cache memory 17 in the A stage. Further, reading from the register file 21 is performed at the D stage, and writing to the register file 21 is performed at the W stage. Further, the N-stage to D-stage and the A-stage to D-stage are provided with bypasses 119 and 117 for sending the data read from the data cache 17, respectively, and the E-stage to the IF stage are provided with a path 104 for sending an address. There is.

FIG. 6 shows a time chart in the case where the load instruction which is the first instruction causes a cache hit in the pipeline processing device of the first embodiment when the instruction sequence of FIG. 2 is processed. FIG. 7 shows a time chart in the case where the load instruction which is the first instruction causes a cache miss.

The specific operation of the pipeline processing apparatus of the first embodiment will be described below by taking the instruction sequence of FIG. 2 as an example.

First, the load instruction which is the first instruction is read from the instruction cache 9 at the IF stage. Then the first
In the D stage, the load instruction, which is the instruction of, reads out the data of the register x and the data of the register b from the register file 21 to the data lines 131 and 110, respectively, and selects the data lines 131 and 110 by the selection circuits 12 and 13, respectively. Output to 111 and 112. At this time, the add instruction which is the second instruction is read from the instruction cache 9 in the IF stage. The load instruction, which is the first instruction, performs addition in the arithmetic unit 15 using the data 111 and 112 at the E stage, and the read address 11 of the data cache.
5 is output. At this time, the addition instruction which is the second instruction is D
At the stage, the data of the register r1 and the data of the register r2 are respectively transferred from the register file 21 to the data line 13
1, 110 are read. Here, as shown in FIG. 2, since there is a data dependency relationship between the load instruction which is the first instruction and the addition instruction which is the second instruction via the register r1, the data dependency relationship is detected in the detection circuit 24. Is detected. When it is detected that there is a dependency relationship, the addition instruction, which is the second instruction, means that old data is output to the data line 131 from which the data of the register r1 is read, and therefore the instruction operation stage Is not sent to the E stage, which is held by the stage lock signal 129 at the immediately preceding D stage. The load instruction, which is the first instruction, is continuously processed regardless of the presence or absence of data dependency, and the output result 115 from the E stage is used in the A stage to read the data 117 from the data cache 17 as the data cache read address 116. The data read in the A stage is sent to the D stage through the bypass 117, and the stage lock signal 129 holding the addition instruction which is the second instruction is released here. When the data 117 corresponding to the register r1 is sent from the A stage, the addition instruction, which is the second instruction, selects the sent data 117 by the selection circuit 12 and outputs it to the data line 111. Register r2 read from register file 21 in D stage
Data 110 is selected by the selection circuit 13 and the data line 112 is selected.
Output to. The addition instruction which is the second instruction is preceded by the E stage before the hit judgment of the cache of the load instruction which is the first instruction is determined by the arithmetic unit 15 using the output data 111 and 112 from the D stage. Then, the addition is performed and the addition result 115 is output. The load instruction, which is the first instruction, selects the data 117 at the A stage by the selection circuit 27 and sends it to the N stage data holding circuit 29. Also, the data cache read address 116 physically causes the data address tag 18 and the data TLB 28 to be used. The addresses 118 and 133 are read and sent to the hit determination circuit 20 which determines the cache hit of the load instruction which is the first instruction.

First, when the load instruction which is the first instruction is identified as a cache hit by the hit determination circuit 20 in the N stage, the data 117 read in the A stage of the first instruction is valid data. Therefore, the load instruction which is the first instruction writes the valid data 119 sent from the A stage and output to the N stage to the register r1 in the W stage. Further, since the preceding operation of the addition instruction which is the second instruction is also effective, the addition instruction continues to be processed, and in the N stage, the selection circuit 27 selects the addition result 116 of the addition instruction which is the second instruction, At the W stage, the addition result is written in the register t.

In the pipeline processing device of the first embodiment, when the load instruction which is the first instruction causes a cache hit, the addition instruction which is the second instruction has a one-cycle penalty.

On the other hand, when the load instruction, which is the first instruction, is found to be a cache miss in the N stage, the data read in the A stage of the first instruction is invalid data. Block transfer is performed to read valid data, and the block is held in the N stage by the stage lock signal 126 during the block transfer. Further, the add instruction which is the second instruction is also held in the E stage by the stage lock signal 126 during the block transfer. When the block transfer ends after a plurality of cycles from the occurrence of the cache miss, the stage lock signal 126 is released, and valid data is read to the N stage where the load instruction which is the first instruction exists. The load instruction, which is the first instruction, writes the valid data 119 to the register r1 at the W stage. However, the addition instruction which is the second instruction has already completed the addition operation when the block transfer is finished, but the data 117 sent from the A stage to the D stage by the load instruction which is the first instruction is invalid. Since it is data, the addition operation is an invalid operation, and the addition instruction needs to be executed again. The add instruction which is the second instruction exists in the E stage when the block transfer of the load instruction which is the first instruction is completed. Therefore, the address of the add instruction in the E stage is returned to the previous stage through the path 104 and selected. The address 104 is selected by the circuit 1 and returned to the IF stage. The instruction cache 9 at the returned address 102
From the second instruction, the addition instruction which is the second instruction is read again. Here, the process of returning the instruction to the stage before the operation stage and re-executing it is called a retry. When the add instruction which is the second instruction is processed up to the D stage, the data read by the load instruction which is the first instruction is already written in the register r1. The add instruction which is the second instruction is executed from the register file 21 to the register r in the D stage.
The data of 1 and the data of the register r2 are read to the data lines 131 and 110, respectively, and the selection circuits 12 and 13 select the data 131 and 110, respectively.
Output to 12. The addition instruction which is the second instruction is the E stage, the addition is performed again in the arithmetic unit 15 using the output data 111 and 112 from the D stage, and the addition circuit 116 is selected by the selection circuit 27 at the A stage. Then, in the W stage, the addition result is written in the register t.

In the pipeline processing device of the first embodiment, when the load instruction which is the first instruction causes a cache miss, the addition instruction which is the second instruction becomes 2 cycles + block transfer cycle + retry processing cycle penalty. .

The second embodiment has a configuration in which the invention of claim 3 is added to the pipeline processing apparatus of the first embodiment.

FIG. 1 shows the configuration of the second embodiment.

FIG. 3 shows a time chart in the case where the load instruction which is the first instruction causes a cache hit when the instruction sequence of FIG. 2 is processed in the pipeline processing device of the second embodiment. FIG. 4 shows a time chart when the first instruction, the load instruction, causes a cache miss.

The specific operation of the second embodiment will be described below with reference to the drawings.

First, the load instruction which is the first instruction is read from the instruction cache 9 in the IF stage. Then the first
In the D stage, the load instruction, which is the instruction of, reads out the data of the register x and the data of the register b from the register file 21 to the data lines 131 and 110, respectively, and selects the data lines 131 and 110 by the selection circuits 12 and 13, respectively. Output to 111 and 112. At this time, the add instruction which is the second instruction is read from the instruction cache 9 in the IF stage. The load instruction, which is the first instruction, performs addition in the arithmetic unit 15 using the data 111 and 112 at the E stage, and the read address 11 of the data cache.
5 is output. At this time, the addition instruction which is the second instruction is D
At the stage, the data of the register r1 and the data of the register r2 are respectively transferred from the register file 21 to the data line 13
1, 110 are read. Here, as shown in FIG. 2, since there is a data dependency relationship between the load instruction which is the first instruction and the addition instruction which is the second instruction via the register r1, the data dependency relationship is detected in the detection circuit 24. Is detected. When it is detected that there is a dependency relationship, the addition instruction, which is the second instruction, means that old data is output to the data line 131 from which the data of the register r1 is read, and therefore the instruction operation stage Is not sent to the E stage, which is held by the stage lock signal 129 at the immediately preceding D stage. The load instruction, which is the first instruction, is continuously processed regardless of the presence or absence of data dependency, and the output result 115 from the E stage is used in the A stage to read the data 117 from the data cache 17 as the data cache read address 116. The data read in the A stage is sent to the D stage through the bypass 117, and the stage lock signal 129 holding the addition instruction which is the second instruction is released here. When the data 117 corresponding to the register r1 is sent from the A stage, the addition instruction, which is the second instruction, selects the sent data 117 by the selection circuit 12 and outputs it to the data line 111. Register r2 read from register file 21 in D stage
Data 110 is selected by the selection circuit 13 and the data line 112 is selected.
Output to. The addition instruction which is the second instruction is preceded by the E stage before the hit judgment of the cache of the load instruction which is the first instruction is determined by the arithmetic unit 15 using the output data 111 and 112 from the D stage. Then, the addition is performed and the addition result 115 is output. The load instruction, which is the first instruction, selects the data 117 at the A stage by the selection circuit 27 and sends it to the N stage data holding circuit 29. Also, the data cache read address 116 physically causes the data address tag 18 and the data TLB 28 to be used. The addresses 118 and 133 are read and sent to the hit determination circuit 20 which determines the cache hit of the load instruction which is the first instruction.

First, in the case where the load instruction which is the first instruction is found to be a cache hit by the hit determination circuit 20 in the N stage, the data 117 read in the A stage of the first instruction is valid data. Therefore, the load instruction which is the first instruction writes the valid data 119 sent from the A stage and output to the N stage to the register r1 in the W stage. Further, since the preceding operation of the addition instruction which is the second instruction is also effective, the addition instruction continues to be processed, and in the N stage, the selection circuit 27 selects the addition result 116 of the addition instruction which is the second instruction, At the W stage, the addition result is written in the register t.

When the load instruction which is the first instruction causes a cache hit in the pipeline processing device of the second embodiment, the same operation as in the first embodiment is performed, and the addition instruction which is the second instruction is executed. There is a one-cycle penalty.

On the other hand, when the load instruction, which is the first instruction, is found to be a cache miss in the N stage, the data read in the A stage of the first instruction is invalid data. Block transfer is performed to read valid data, and the block is held in the N stage by the stage lock signal 126 during the block transfer. Further, since the preceding operation of the add instruction which is the second instruction uses invalid data, the preceding operation becomes an invalid operation, so that the add instruction needs to be executed again. The add instruction, which is the second instruction, exists in the E stage when the load instruction, which is the first instruction, is found to be a cache miss.
The address of the add instruction in the E stage is returned to the previous stage through the path 104, and the address 104 is selected by the selection circuit 1 and returned to the IF stage. The returned address 102
Then, the add instruction which is the second instruction is read again from the instruction cache 9 and the valid data is sent by block transfer of the load instruction which is the first instruction in the D stage which is the stage before the E stage. The add instruction, which is the instruction of 2, is held again by the stage lock signal 128. Here, in the first embodiment, the retry processing of the second instruction is executed after the block transfer of the first instruction, but in the second embodiment, the retry processing of the second instruction is executed during the block transfer, The retry process is completed before the block transfer is completed. When the block transfer ends after a plurality of cycles from the occurrence of the cache miss, the stage lock signals 126 and 128 are released, and valid data is read out to the N stage where the load instruction which is the first instruction exists. The load instruction, which is the first instruction, sends valid data equivalent to the register r1 read to the N stage from the N stage to the D stage through the bypass 119. The load instruction writes valid data 119 in the register r1 at the W stage. When the valid data 119 is sent from the N stage to the D stage, the add instruction, which is the second instruction, selects the sent data 119 by the selection circuit 12 and outputs it to the data line 111. The data 110 of the register r2 read from the register file 21 at the stage is selected by the selection circuit 13 and output to the data line 112. The add instruction, which is the second instruction, is the E stage and the output data 11 from the D stage.
The addition is performed again by the arithmetic unit 15 using 1, 112,
The addition result 115 is output. Then, at the N stage, the data 116 as the addition result is selected by the selection circuit 27, and at the W stage, the addition result is written in the register t.

In the pipeline processing device of the second embodiment, when the load instruction which is the first instruction causes a cache miss, the addition instruction which is the second instruction has a penalty of 2 cycles + block transfer cycle.

The above-described first and second embodiments show the case where the hit judgment of the data cache is one cycle later than the data read of the data cache.

The number of pipeline stages in the second embodiment is not limited to six in the third embodiment.

FIG. 11 shows a time chart at the time of a cache hit in the pipeline processing apparatus of the third embodiment when the hit determination is delayed by 2 cycles from the data reading due to the speedup of the processing. As shown in FIG. 11, the addition instruction, which is the second instruction at this time, has a one-cycle penalty. FIG. 12 shows a time chart at the time of a cache miss. As shown in FIG. 12, the addition instruction at this time is 3 cycles + block transfer cycle penalty.

In the fourth embodiment, the data returned by the retry process of the second instruction in the third embodiment is not limited to the address.

In the fifth embodiment, the return destination of the retry processing of the second instruction in the fourth embodiment is not limited to the IF stage as long as it is the stage before the operation stage.

[0050]

As described above, according to the first aspect of the present invention, when there is a data dependency between the load instruction which is the first instruction and the second instruction, the data is read from the cache. Since the data is sent before the operation stage before the cache hit decision is known, the second instruction can perform the operation in advance, and excessive holding is eliminated at the time of cache hit. Since the penalty is reduced, the processing speed of the pipeline processing device can be improved. Further, even if the stage for reading data from the data cache and the stage for determining the hit determination of the cache are separated from each other, since the preceding operation of the second instruction is possible, excessive holding at the time of cache hit is eliminated, and at the time of cache hit. Therefore, the processing speed of the pipeline processing device can be prevented from decreasing.

According to the configuration of the second aspect of the present invention, even if the load instruction which is the first instruction causes a cache miss, the second instruction that has been sent up to and after the operation stage can be executed again, and the normal operation is performed. Guaranteed.

According to the invention of claim 3, the operation of returning the second instruction to the stage before the operation stage and holding it in the stage before the operation stage is during the block transfer of the load instruction which is the first instruction. When the block transfer is completed, the second instruction can immediately receive the read valid data and execute the operation. Therefore, the operation of claim 2 does not increase the penalty, and the pipeline processing is performed. It is possible to prevent the processing speed of the device from decreasing.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a second embodiment of a pipeline processing device according to the present invention.

FIG. 2 is an instruction sequence having a data dependency relationship.

FIG. 3 is a time chart at the time of a cache hit in the second embodiment.

FIG. 4 is a time chart when a cache miss occurs in the second embodiment.

FIG. 5 is a configuration diagram of a first embodiment of a pipeline processing device according to the present invention.

FIG. 6 is a time chart when a cache hit occurs in the first embodiment.

FIG. 7 is a time chart when a cache miss occurs in the first embodiment.

FIG. 8 is a configuration diagram of a pipeline processing device according to a conventional technique.

FIG. 9 is a time chart when a cache hit occurs in the conventional technique.

FIG. 10 is a time chart when a cache miss occurs in the conventional technique.

FIG. 11 is a time chart when a cache hit occurs when data read and cache hit determination are separated by two cycles in the second embodiment.

FIG. 12 is a time chart when a cache miss occurs when data read and cache hit determination are separated by two cycles in the second embodiment.

FIG. 13 is a time chart when a cache hit occurs when data read and cache hit determination are separated by two cycles in the prior art.

FIG. 14 is a time chart when a cache miss occurs when data read and cache hit determination are separated by two cycles in the prior art.

[Explanation of symbols]

1, 12, 13, 27 ... Selection circuit, 2, 3, 4, 5, 6, 7, 10, 14, 16, 19, 2
6 ... Stage holding circuit, 8 ... Program counter, 9 ... Instruction cache memory, 11 ... Register selection circuit, 15 ... Arithmetic unit, 17 ... Data cache memory, 18 ... Data address tag, 20 ... Hit determination circuit, 21 ... Register file 22 ... Re-execution control device, 23 ... Control device, 24 ... Dependency detection circuit, 25 ... Preceding operation control device, 28 ... Data TLB.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenji Matsubara, 1 Horiyamashita, Horiyamashita, Hadano, Kanagawa Prefecture

Claims (3)

[Claims] 1. A pipeline processing device that divides a first instruction and a second instruction to be executed after the first instruction into a plurality of stages to perform pipeline processing, wherein the first instruction is loaded. When the second instruction is an instruction and uses the data read by the load instruction which is the first instruction, the operation of the second instruction is performed before the cache hit determination of the load instruction is determined. A pipeline processing device comprising: a bypass for sending read data to a computing means of a stage to be executed; and a control means for controlling the sending of the read data to the computing means by using the bypass. 2. The pipeline processing device according to claim 1, wherein the second instruction is an instruction that uses data read by a load instruction that is the first instruction, and the load instruction that is the first instruction is a cache miss. When you wake up
A path for returning the second instruction from the stage after the operation stage to the stage before the operation stage and a second path using the path
And a control means for controlling so that the second instruction is returned to the stage before the operation stage and the second instruction is re-executed. 3. The pipeline processing apparatus according to claim 2, wherein the second instruction is returned to a stage prior to the operation stage during block transfer caused by a cache miss of the load instruction which is the first instruction. Pipeline processing, characterized in that it has control means for holding the data in the stage prior to the above, and when the block transfer is completed, the second instruction immediately receives the valid data read and executes the operation. apparatus.