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JPH07312456A - Quantum wire fabrication method - Google Patents

Quantum wire fabrication method

Info

Publication number
JPH07312456A
JPH07312456A JP10357594A JP10357594A JPH07312456A JP H07312456 A JPH07312456 A JP H07312456A JP 10357594 A JP10357594 A JP 10357594A JP 10357594 A JP10357594 A JP 10357594A JP H07312456 A JPH07312456 A JP H07312456A
Authority
JP
Japan
Prior art keywords
plane
mask
semiconductor substrate
quantum
quantum wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10357594A
Other languages
Japanese (ja)
Inventor
Satoshi Igawa
聖史 井川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kubota Corp
Original Assignee
Kubota Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kubota Corp filed Critical Kubota Corp
Priority to JP10357594A priority Critical patent/JPH07312456A/en
Publication of JPH07312456A publication Critical patent/JPH07312456A/en
Pending legal-status Critical Current

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Abstract

(57)【要約】 【目的】 量子細線の作製歩留りを向上できる量子細線
の作製方法を提供する。 【構成】 量子細線の作製方法において、多層膜からな
る量子井戸構造を形成した半導体基板の表面に{10
0}面と{111}面とを互いに隣接する状態に形成
し、その{100}面及び{111}面の両方を含む状
態で同時にドライエッチングする。又、上記量子細線の
作製方法において、表面が{100}面となる状態で量
子井戸構造を形成した半導体基板の表面に端面がすそ広
がりとなるテーパ状のマスクを形成し、ドライエッチン
グ処理を施して、半導体基板の表面に{100}面と
{111}面とを互いに隣接する状態に形成する。又、
上記量子細線の作製方法において、表面が{100}面
となる状態で量子井戸構造を形成した半導体基板の表面
にマスクを形成し、ウェットエッチング処理を施して、
半導体基板の表面に{100}面と{111}面とを互
いに隣接する状態に形成する。
(57) [Summary] [Objective] To provide a method for producing a quantum wire, which can improve the yield in producing a quantum wire. According to a method of manufacturing a quantum wire, {10 is formed on a surface of a semiconductor substrate having a quantum well structure formed of a multilayer film.
A 0} plane and a {111} plane are formed adjacent to each other, and dry etching is performed simultaneously in a state including both the {100} plane and the {111} plane. Further, in the above-mentioned method for producing a quantum wire, a taper-shaped mask having an end face that widens at the end is formed on the surface of a semiconductor substrate on which a quantum well structure is formed with the surface being a {100} plane, and dry etching is performed. Then, the {100} plane and the {111} plane are formed adjacent to each other on the surface of the semiconductor substrate. or,
In the above method for producing a quantum wire, a mask is formed on the surface of a semiconductor substrate on which a quantum well structure is formed in a state where the surface is a {100} plane, and wet etching treatment is performed,
A {100} plane and a {111} plane are formed adjacent to each other on the surface of the semiconductor substrate.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、量子細線の作製方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing quantum wires.

【0002】[0002]

【従来の技術】かかる量子細線の作製方法は、従来、半
導体基板に断面がV字状の溝を形成し、その上に多層膜
からなる量子井戸構造を形成する半導体レーザ素子の作
製方法に適用したものがあった。このように断面がV字
状の溝を有する半導体基板上に多層膜を積層すると、積
層した多層膜におけるV字状の溝の先端部の上方側箇所
で、多層膜の層厚が変化しており、この層厚の変化及び
多層膜がV字状の溝形状に応じて屈曲していること等か
ら、上記の如く作製した半導体レーザ素子は積層面に平
行な方向においても量子効果を有する程に極めて狭い領
域に光が閉じ込められ、いわゆる量子細線を構成する。
2. Description of the Related Art A method of manufacturing such a quantum wire is conventionally applied to a method of manufacturing a semiconductor laser device in which a groove having a V-shaped cross section is formed in a semiconductor substrate and a quantum well structure made of a multilayer film is formed on the groove. There was something I did. When a multilayer film is laminated on a semiconductor substrate having a groove having a V-shaped cross section in this way, the layer thickness of the multilayer film changes at a position above the tip of the V-shaped groove in the laminated multilayer film. However, because of the change in the layer thickness and the multilayer film being bent according to the V-shaped groove shape, the semiconductor laser device manufactured as described above has a quantum effect even in the direction parallel to the stacking plane. The light is confined in an extremely narrow area, forming a so-called quantum wire.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、上記従
来構成では、多層膜におけるV字状の溝の先端部の上方
側箇所の層厚のばらつきが量子細線の特性に大きく影響
するので、多層膜の積層層厚のばらつきを抑制する必要
があるが、量子細線の特性ばらつきを十分抑制できる程
の精度で制御するのは困難で、量子細線の作製歩留りを
低下させていた。本発明は、上記実情に鑑みてなされた
ものであって、その第1の目的は、量子細線の作製歩留
りを向上できる量子細線の作製方法を提供することにあ
る。第2の目的は、量子細線の作製方法を簡単化しなが
ら、上記第1の目的を達することにある。
However, in the above-mentioned conventional structure, since the variation in the layer thickness at the upper side of the tip of the V-shaped groove in the multilayer film has a great influence on the characteristics of the quantum wire, the multilayer film has Although it is necessary to suppress the variation in the laminated layer thickness, it is difficult to control with sufficient accuracy to suppress the variation in the characteristics of the quantum wires, and the production yield of the quantum wires is reduced. The present invention has been made in view of the above circumstances, and a first object of the present invention is to provide a method for manufacturing quantum wires, which can improve the manufacturing yield of quantum wires. The second purpose is to achieve the above-mentioned first purpose while simplifying the method for producing quantum wires.

【0004】[0004]

【課題を解決するための手段】本発明の量子細線の作製
方法の第1特徴は、多層膜からなる量子井戸構造を形成
した半導体基板の表面に{100}面と{111}面と
を互いに隣接する状態に形成し、その{100}面及び
{111}面の両方を含む状態で同時にドライエッチン
グする点にある。第2特徴は、上記第1特徴において、
表面が{100}面となる状態で多層膜からなる量子井
戸構造を形成した半導体基板の表面に端面がすそ広がり
となるテーパ状のマスクを形成し、ドライエッチング処
理を施した後に、前記マスクを除去して、半導体基板の
表面に{100}面と{111}面とを互いに隣接する
状態に形成する点にある。第3特徴は、上記第1特徴に
おいて、表面が{100}面となる状態で多層膜からな
る量子井戸構造を形成した半導体基板の表面にマスクを
形成し、ウェットエッチング処理を施した後に、前記マ
スクを除去して、半導体基板の表面に{100}面と
{111}面とを互いに隣接する状態に形成する点にあ
る。
The first feature of the method for producing a quantum wire of the present invention is that the {100} plane and the {111} plane are formed on the surface of a semiconductor substrate having a quantum well structure formed of a multilayer film. The point is that they are formed adjacent to each other and are simultaneously dry-etched in a state including both the {100} plane and the {111} plane. The second feature is the above first feature,
A taper-shaped mask whose end face is widened is formed on the surface of a semiconductor substrate having a quantum well structure formed of a multilayer film in a state where the surface is a {100} surface, and the mask is applied after dry etching treatment. The point is that the {100} plane and the {111} plane are formed adjacent to each other on the surface of the semiconductor substrate after removal. The third feature is that in the first feature, the mask is formed on the surface of the semiconductor substrate having the quantum well structure formed of the multilayer film in the state where the surface is the {100} plane, and the wet etching treatment is performed. The point is that the mask is removed and the {100} plane and the {111} plane are formed adjacent to each other on the surface of the semiconductor substrate.

【0005】[0005]

【作用】本発明の第1特徴によれば、半導体基板の表面
に隣接して形成されている{100}面と{111}面
とを同時にドライエッチングすると、{100}面のエ
ッチングレートは、{111}面のエッチングレートよ
りも大きいことから、表面が{100}面の部分は速や
かにエッチング除去されるが、表面が{111}面の部
分は{100}面の部分に較べてゆっくりとエッチング
除去される。この結果、{100}面と{111}面と
の境界部分では、相対的に、{111}面側が残って、
{100}面が下方に向かって除去されることになり、
{100}面と{111}面との境界線に沿って、断面
視においてくさび状の突起が形成される。この突起の先
端近傍の幅狭の部分には、先に半導体基板に形成した量
子井戸構造が残っており、その量子井戸構造は、それを
構成する多層膜の積層面に平行な方向が幅狭となる量子
細線となる。このくさび状の突起の部分は、{100}
面と{111}面とのエッチングレートの差を利用して
形成するので、エッチング形状を精度良く制御できる。
According to the first feature of the present invention, when the {100} plane and the {111} plane formed adjacent to the surface of the semiconductor substrate are simultaneously dry-etched, the etching rate of the {100} plane becomes Since the etching rate of the {111} plane is higher than that of the {111} plane, the surface of the {100} plane is rapidly removed by etching, but the surface of the {111} plane is slower than the {100} plane. It is removed by etching. As a result, in the boundary portion between the {100} plane and the {111} plane, the {111} plane side remains relatively,
The {100} plane will be removed downward,
A wedge-shaped protrusion in a cross-sectional view is formed along the boundary line between the {100} plane and the {111} plane. The quantum well structure previously formed on the semiconductor substrate remains in the narrow portion near the tip of the protrusion, and the quantum well structure has a narrow width in the direction parallel to the stacking surface of the multilayer film forming the quantum well structure. It becomes a quantum wire. This wedge-shaped protrusion is {100}
Since it is formed by utilizing the difference in etching rate between the {111} plane and the {111} plane, the etching shape can be controlled with high accuracy.

【0006】本発明の第2特徴によれば、{100}面
上に端面がすそ広がりとなるテーパ状のマスクを形成し
てドライエッチング処理をすると、マスク自体も少しず
つエッチング除去されることから、エッチング処理の途
中において、マスクの端面が徐々に後退することにな
る。このマスクが後退した部分にはエッチング途中にお
いて{111}面が現れ、{111}面のエッチングレ
ートが小さいことから、一旦{111}面が現れるとエ
ッチング処理を継続しても、現れた{111}面が保存
される。このエッチング処理後にマスクを除去すると、
半導体基板の表面に{100}面と{111}面とを互
いに隣接する状態で形成される。従って、{100}面
と{111}面とのエッチングレートの差を利用してい
るので、制御性良く{100}面と{111}面とが互
いに隣接する状態とすることができるのである。
According to the second feature of the present invention, when a dry etching process is performed by forming a tapered mask whose end face is wide on the {100} face, the mask itself is gradually removed by etching. During the etching process, the end face of the mask gradually recedes. A {111} plane appears in the recessed portion of the mask during etching, and since the etching rate of the {111} plane is small, once the {111} plane appears, it appears even if the etching process is continued. } The face is saved. If the mask is removed after this etching process,
A {100} plane and a {111} plane are formed adjacent to each other on the surface of the semiconductor substrate. Therefore, since the difference in etching rate between the {100} plane and the {111} plane is utilized, the {100} plane and the {111} plane can be in a state of being adjacent to each other with good controllability.

【0007】本発明の第3特徴によれば、{100}面
上にマスクを形成してウェットエッチング処理をする
と、ウェットエッチング処理の等方性エッチング特性に
よって、半導体基板におけるマスクの端部の下方側に位
置する部分がエッチング除去されるいわゆるサイドエッ
チングが生じる。この結果、そのサイドエッチングが生
じた箇所に{111}面が形成され、ウェットエッチン
グ処理後マスクを除去すると、半導体基板の表面に{1
00}面と{111}面とを互いに隣接する状態で形成
される。上記のマスクは特殊な形状に加工する必要がな
いので、{100}面上にマスクを形成してウェットエ
ッチング処理をするだけの簡単な処理で、{100}面
と{111}面とが互いに隣接する状態とすることがで
きるのである。
According to the third feature of the present invention, when a mask is formed on the {100} plane and wet etching is performed, the isotropic etching characteristic of the wet etching causes the lower portion of the edge of the mask on the semiconductor substrate to be removed. So-called side etching occurs in which the portion located on the side is removed by etching. As a result, a {111} plane is formed at the portion where the side etching occurs, and when the mask is removed after the wet etching treatment, {1} is formed on the surface of the semiconductor substrate.
The {00} plane and the {111} plane are formed adjacent to each other. Since the above mask does not need to be processed into a special shape, a simple process of forming a mask on the {100} plane and performing a wet etching process makes the {100} plane and the {111} plane mutually It can be in an adjacent state.

【0008】[0008]

【発明の効果】上記第1特徴によれば、量子細線の特性
に影響を与えるエッチング形状を精度良く制御できて、
量子細線の特性のばらつきを抑制できるので、量子細線
の作製歩留りを向上できる量子細線の作製方法を提供す
るに至った。上記第2特徴によれば、制御性良く{10
0}面と{111}面とが互いに隣接する状態とするこ
とができるので、更に量子細線の作製歩留りを向上でき
る量子細線の作製方法を提供するに至った。上記第3特
徴によれば、{100}面上にマスクを形成してウェッ
トエッチング処理をするだけの簡単な処理で、{10
0}面と{111}面とが互いに隣接する状態とするこ
とができるので、量子細線の作製方法を簡単化しなが
ら、上記第1特徴構成による効果を奏することができ
る。
According to the first feature described above, the etching shape affecting the characteristics of the quantum wire can be controlled with high precision,
Since it is possible to suppress the variation in the characteristics of the quantum wires, it has been possible to provide a method for manufacturing the quantum wires that can improve the production yield of the quantum wires. According to the second feature, {10
Since the 0} plane and the {111} plane can be in a state of being adjacent to each other, the present invention has provided a method for producing a quantum thin wire that can further improve the yield of quantum wire production. According to the third feature described above, a simple process of forming a mask on the {100} plane and performing a wet etching process can produce {10
Since the 0} plane and the {111} plane can be adjacent to each other, the effect of the first characteristic configuration can be obtained while simplifying the method of manufacturing the quantum wire.

【0009】[0009]

【実施例】以下、本発明を半導体レーザ素子の製造工程
に適用した実施例を、図面に基づいて説明する。本発明
の量子細線の作製方法を適用して作製した半導体レーザ
素子Lの共振器方向に垂直な面における断面図を図1に
示す。半導体レーザ素子Lは、n型GaAs基板1上に
n型AlGaAs層2及びアンドープのGaAs層とア
ンドープのAlGaAs層との多層膜からなる量子井戸
構造を有する量子井戸層3が断面視において略凸形状に
形成されて、その突出部分の両側脇にp型AlGaAs
埋め込み層4及びn型GaAs埋め込み層5が形成さ
れ、更に、それらの上方側にp型AlGaAs層6及び
p型GaAs層7が形成されている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment in which the present invention is applied to a manufacturing process of a semiconductor laser device will be described below with reference to the drawings. FIG. 1 shows a cross-sectional view of a semiconductor laser element L manufactured by applying the method for manufacturing a quantum wire of the present invention, taken along a plane perpendicular to the cavity direction. In the semiconductor laser device L, a quantum well layer 3 having a quantum well structure including an n-type AlGaAs layer 2 and a multilayer film of an undoped GaAs layer and an undoped AlGaAs layer on an n-type GaAs substrate 1 has a substantially convex shape in cross section. Are formed on both sides of the protruding portion, and p-type AlGaAs
A buried layer 4 and an n-type GaAs buried layer 5 are formed, and a p-type AlGaAs layer 6 and a p-type GaAs layer 7 are formed on the upper side thereof.

【0010】この半導体レーザ素子Lは、図示しない電
極から電流が注入されると、量子井戸層3においてレー
ザ発振して、レーザ光を放出する。つまり、図1に示す
構造では2本のビームを放出する。量子井戸層3は、n
型AlGaAs層2上に断面視でくさび状に形成され、
幅狭となっているので、いわゆる量子細線を構成してい
る。
When a current is injected from an electrode (not shown), the semiconductor laser device L oscillates in the quantum well layer 3 to emit laser light. That is, the structure shown in FIG. 1 emits two beams. The quantum well layer 3 is n
Formed on the AlGaAs layer 2 in a wedge shape in cross section,
Since it is narrow, it forms a so-called quantum wire.

【0011】以下、上記構成の半導体レーザ素子Lの製
造工程を説明する。先ず、図2に示すように、ウェハ状
のn型GaAs基板1の{100}面上に、n型AlG
aAs層2を積層し、更に、アンドープのAlGaAs
層3aとアンドープのGaAs層3bとが交互に位置す
る量子井戸層3を積層する。この積層は、MBE,MO
MBE又はMOCVD等の気相成長法にて積層する。次
に、量子井戸層3まで積層し、表面が{100}面とな
っている半導体基板Sの表面に、図3(イ)の平面図及
び図3(ロ)の断面図に示すように、長手方向が〈0 -1
1〉(ここで、「-1」はミラー指数における1バーを表
すものとする)に延びるストライプ状のSiO2 のマス
ク8を、端面がすそ広がりのテーパ状となるようにフォ
トリソグラフィとウェットエッチングにて形成する。図
3(ロ)に示すように、マスク8は共振器方向に垂直な
断面視における一素子幅分つき一本存在し、図3(イ)
に示すように、共振器方向に垂直な断面視における一素
子幅と同ピッチで配列させてある。
The manufacturing process of the semiconductor laser device L having the above structure will be described below. First, as shown in FIG. 2, n-type AlG is formed on the {100} plane of a wafer-shaped n-type GaAs substrate 1.
The aAs layer 2 is laminated, and further, undoped AlGaAs
The quantum well layers 3 in which the layers 3a and the undoped GaAs layers 3b are alternately located are stacked. This stack is MBE, MO
The layers are stacked by a vapor phase growth method such as MBE or MOCVD. Next, as shown in the plan view of FIG. 3A and the cross-sectional view of FIG. 3B, on the surface of the semiconductor substrate S in which the quantum well layer 3 is laminated and the surface is the {100} plane, Longitudinal direction is <0 -1
1> (here, “−1” represents 1 bar in the Miller index), the stripe-shaped SiO 2 mask 8 is subjected to photolithography and wet etching so that the end face becomes a tapered shape with a skirt extending. To form. As shown in FIG. 3B, there is one mask 8 with one element width in a sectional view perpendicular to the resonator direction.
As shown in FIG. 3, the elements are arranged at the same pitch as the width of one element in a sectional view perpendicular to the resonator direction.

【0012】図3に示すようにマスク8を形成したもの
をドライエッチング装置によってマスク8上からドライ
エッチング処理を行うと、図4に示す断面図のように、
矢印A方向へのマスク8の後退と、{100}面と{1
11}面とのエッチングレートの差から、マスク8の両
脇に{111}面の斜面Bが現れる。図4に示す状態か
ら更にマスク8が消失するまでドライエッチング処理を
継続すると、図5に示すように、マスク8を除去した位
置から{100}面の上面部Cが現れ、半導体基板Sの
表面に{100}面と{111}面とが互いに隣接する
状態となる。
When the mask 8 formed as shown in FIG. 3 is dry-etched on the mask 8 by a dry etching apparatus, a cross-sectional view shown in FIG. 4 is obtained.
The retreat of the mask 8 in the direction of arrow A and the {100} plane and {1}
Due to the difference in etching rate from the 11} plane, the slopes B of the {111} plane appear on both sides of the mask 8. When the dry etching process is continued from the state shown in FIG. 4 until the mask 8 disappears, as shown in FIG. 5, the upper surface portion C of the {100} plane appears from the position where the mask 8 is removed, and the surface of the semiconductor substrate S is exposed. The {100} plane and the {111} plane are adjacent to each other.

【0013】図5に示すマスク8が消失した状態から更
にドライエッチング処理を継続すると、{100}面と
{111}面とのエッチングレートの差により、{10
0}面は急速にエッチングされ、{111}面は相対的
に緩やかにエッチングされて、その結果、図6の示すよ
うに、量子井戸層3が断面視でくさび状に形成される。
すなわち、マスク8をドライエッチング処理にて除去す
ることで、図3に示すマスク8を形成した時点から図6
の示す量子井戸層3をくさび状に形成する時点までドラ
イエッチング装置から取り出すことなく、一挙にエッチ
ング処理できるのである。これにより量子細線の製造工
程の簡単化を図れると共に、ドライエッチング装置外で
の処理でウェハを損傷することもない。
When the dry etching process is further continued from the state where the mask 8 shown in FIG. 5 has disappeared, the difference in etching rate between the {100} plane and the {111} plane causes {10}.
The 0} plane is rapidly etched, and the {111} plane is relatively gently etched, and as a result, the quantum well layer 3 is formed in a wedge shape in cross section as shown in FIG.
That is, the mask 8 is removed by a dry etching process so that the mask 8 shown in FIG.
That is, the etching process can be performed all at once without taking out from the dry etching apparatus until the time point when the quantum well layer 3 is formed into a wedge shape. As a result, the manufacturing process of the quantum wire can be simplified, and the wafer is not damaged by the processing outside the dry etching apparatus.

【0014】図6に示す状態から、液相成長にて、p型
AlGaAs埋め込み層4及びn型GaAs埋め込み層
5を、量子井戸層3の頂部と一致する高さまで積層し、
更にその上に、p型AlGaAs層6及びp型GaAs
層7を積層する。この後、電極を形成し、ウェハ状態か
ら一素子毎に素子分離して、半導体レーザ素子Lとす
る。
From the state shown in FIG. 6, the p-type AlGaAs burying layer 4 and the n-type GaAs burying layer 5 are laminated by liquid phase growth to a height corresponding to the top of the quantum well layer 3,
Further thereon, a p-type AlGaAs layer 6 and a p-type GaAs are formed.
Layer 7 is laminated. After that, electrodes are formed, and each element is separated from the wafer state to obtain a semiconductor laser element L.

【0015】〔別実施例〕以下、別実施例を列記する。 上記実施例では、SiO2 のマスク8を端面がすそ
広がりとなるテーパ状に形成してドライエッチング処理
を施すことにより{100}面と{111}面とを隣接
する状態としているが、図7に示すように、量子井戸層
3上にSiO2 のマスク20を図3(イ)に示すものと
同様なストライプ状に形成し、ウェットエッチング処理
を施して、図8に示す、半導体基板Sの表面にマスク2
0の下側の{100}面と{111}面とが互いに隣接
する状態としても良い。この場合、ウェットエッチング
処理の等方性エッチング特性を利用するので、マスク2
0の端面の形状はテーパ状とする必要はなく、マスク2
0の形成を簡単に行える。
[Other Embodiments] Other embodiments will be listed below. In the above-described embodiment, the SiO 2 mask 8 is formed in a taper shape with the end face widened and a dry etching process is performed so that the {100} face and the {111} face are adjacent to each other. As shown in FIG. 8, a mask 20 of SiO 2 is formed on the quantum well layer 3 in a stripe shape similar to that shown in FIG. 3A, and a wet etching process is applied to the mask 20 of the semiconductor substrate S shown in FIG. Mask 2 on the surface
The lower {100} plane and the {111} plane of 0 may be adjacent to each other. In this case, since the isotropic etching characteristic of the wet etching process is used, the mask 2
The shape of the end face of 0 does not need to be tapered, and the mask 2
It is easy to form 0.

【0016】 上記実施例では、本発明を半導体レー
ザ素子の製造工程に適用した場合を例示しているが、光
集積回路の製造工程等、種々の半導体デバイスの製造工
程に適用できる。
In the above embodiment, the case where the present invention is applied to the manufacturing process of the semiconductor laser device is illustrated, but it can be applied to the manufacturing process of various semiconductor devices such as the manufacturing process of the optical integrated circuit.

【0017】 上記実施例では、図3に示すSiO2
のマスク8を形成した状態から、図6に示す状態まで、
一挙にドライエッチング処理を施しているが、図4に示
すマスク8が残っている状態でドライエッチング装置か
ら取り出して、マスク8をエッチング除去した後、ドラ
イエッチング装置に戻してドライエッチングを継続する
ようにしても良い。
In the above embodiment, SiO 2 shown in FIG.
From the state in which the mask 8 is formed to the state shown in FIG.
Although the dry etching process is performed all at once, the mask 8 shown in FIG. 4 is taken out from the dry etching apparatus, the mask 8 is removed by etching, and then the mask 8 is returned to the dry etching apparatus to continue the dry etching. You can

【0018】 上記実施例では、量子細線を2本形成
しているが、図3に示すストライプ状のマスク8の片側
の端面のみをテーパ状に形成して、その後上記と同様の
処理を行い、1本の量子細線を形成するようにしても良
い。又、図5に示す状態から、二つの斜面Bのうち一方
をエッチング除去した後、ドライエッチングを施して、
一本の量子細線を形成するようにしても良い。
Although two quantum wires are formed in the above embodiment, only one end face of the striped mask 8 shown in FIG. 3 is formed in a tapered shape, and then the same treatment as above is performed. You may make it form one quantum wire. From the state shown in FIG. 5, one of the two slopes B is removed by etching, and then dry etching is performed.
You may make it form one quantum wire.

【0019】 上記実施例では、本発明をAlGaA
s系の材料の半導体に適用した場合を例示しているが、
InGaAsP系又はInGaAlP系の材料等の種々
の半導体材料に適用できる。
In the above embodiment, the present invention is applied to AlGaA.
The case where it is applied to a semiconductor of an s-based material is illustrated, but
It can be applied to various semiconductor materials such as InGaAsP-based or InGaAlP-based materials.

【0020】尚、特許請求の範囲の項に図面との対照を
便利にするために符号を記すが、該記入により本発明は
添付図面の構造に限定されるものではない。
It should be noted that reference numerals are given in the claims for convenience of comparison with the drawings, but the present invention is not limited to the structure of the accompanying drawings by the entry.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明を適用した実施例にかかる素子断面図FIG. 1 is a sectional view of an element according to an embodiment of the present invention.

【図2】本発明の実施例にかかる製造工程を示す図FIG. 2 is a diagram showing a manufacturing process according to an embodiment of the present invention.

【図3】本発明の実施例にかかる製造工程を示す図FIG. 3 is a diagram showing a manufacturing process according to an embodiment of the present invention.

【図4】本発明の実施例にかかる製造工程を示す図FIG. 4 is a diagram showing a manufacturing process according to an embodiment of the present invention.

【図5】本発明の実施例にかかる製造工程を示す図FIG. 5 is a diagram showing a manufacturing process according to an embodiment of the present invention.

【図6】本発明の実施例にかかる製造工程を示す図FIG. 6 is a diagram showing a manufacturing process according to an embodiment of the present invention.

【図7】本発明の別実施例にかかる製造工程を示す図FIG. 7 is a diagram showing a manufacturing process according to another embodiment of the present invention.

【図8】本発明の別実施例にかかる製造工程を示す図FIG. 8 is a diagram showing a manufacturing process according to another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

8 マスク 20 マスク S 半導体基板 8 mask 20 mask S semiconductor substrate

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 多層膜からなる量子井戸構造を形成した
半導体基板(S)の表面に{100}面と{111}面
とを互いに隣接する状態に形成し、その{100}面及
び{111}面の両方を含む状態で同時にドライエッチ
ングする量子細線の作製方法。
1. A {100} plane and a {111} plane are formed adjacent to each other on the surface of a semiconductor substrate (S) having a quantum well structure formed of a multilayer film, and the {100} plane and the {111} plane are formed. } A method of manufacturing a quantum wire in which dry etching is performed at the same time in a state including both surfaces.
【請求項2】 表面が{100}面となる状態で多層膜
からなる量子井戸構造を形成した半導体基板(S)の表
面に端面がすそ広がりとなるテーパ状のマスク(8)を
形成し、ドライエッチング処理を施した後に、前記マス
ク(8)を除去して、半導体基板(S)の表面に{10
0}面と{111}面とを互いに隣接する状態に形成す
る請求項1記載の量子細線の作製方法。
2. A taper-shaped mask (8) whose end face is flared is formed on the surface of a semiconductor substrate (S) having a quantum well structure formed of a multilayer film with the surface being a {100} plane. After performing the dry etching treatment, the mask (8) is removed, and the surface of the semiconductor substrate (S) is {10
The method for producing a quantum wire according to claim 1, wherein the 0} plane and the {111} plane are formed adjacent to each other.
【請求項3】 表面が{100}面となる状態で多層膜
からなる量子井戸構造を形成した半導体基板(S)の表
面にマスク(20)を形成し、ウェットエッチング処理
を施した後に、前記マスク(20)を除去して、半導体
基板(S)の表面に{100}面と{111}面とを互
いに隣接する状態に形成する請求項1記載の量子細線の
作製方法。
3. A mask (20) is formed on the surface of a semiconductor substrate (S) having a quantum well structure formed of a multilayer film in a state where the surface is a {100} plane, and a wet etching treatment is carried out. The method for producing a quantum wire according to claim 1, wherein the mask (20) is removed, and the {100} plane and the {111} plane are formed adjacent to each other on the surface of the semiconductor substrate (S).
JP10357594A 1994-05-18 1994-05-18 Quantum wire fabrication method Pending JPH07312456A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10357594A JPH07312456A (en) 1994-05-18 1994-05-18 Quantum wire fabrication method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10357594A JPH07312456A (en) 1994-05-18 1994-05-18 Quantum wire fabrication method

Publications (1)

Publication Number Publication Date
JPH07312456A true JPH07312456A (en) 1995-11-28

Family

ID=14357593

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10357594A Pending JPH07312456A (en) 1994-05-18 1994-05-18 Quantum wire fabrication method

Country Status (1)

Country Link
JP (1) JPH07312456A (en)

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