JPH07302943A - Drive circuit - Google Patents

Abstract

PURPOSE:To set a drive circuit which drives a DC load composed of resistors or diodes capable of operating at a high speed by a method wherein a characteristics deterioration of the drive circuit due to that a modulation current is leaked into a bias current supply circuit in a high-frequency range is compensated or lessened. CONSTITUTION:A drive circuit is equipped with a voltage/current converting circuit, a DC load, and a bias current supply circuit which feeds a bias current to the DC load, wherein an inductor is connected to the base of a transistor used in the bias current supply circuit. FETs are used in the above voltage/ current converting circuit, and provided that the threshold value and gate width of a FET J3 whose drain is connected to the DC load are represented by Vth3 and W3 respectively, and the threshold value and gate width of another FET J4 are represented by Vth4 and W. respectively, Vth3, Vth4, W3 and W4 are so set as to satisfy formulas, Vth4>Vth3 and W4>W3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit, and more particularly to a high frequency drive circuit used for optical communication and the like.

[0002]

2. Description of the Related Art A circuit for driving a semiconductor laser (LD) is an example of a drive circuit that needs to apply a DC current as a bias current and a high-frequency AC current as a signal current to a DC load. The semiconductor laser applies a DC bias current to near the threshold current value at which light emission starts, and the signal H
It operates by the signal current of the voltage-current conversion circuit as a modulation circuit that determines the IGH level and the LOW level.

FIG. 26 shows a conventional semiconductor laser drive circuit. JB, JC, and JD field-effect transistors (hereinafter F
(Hereinafter referred to as ET) constitutes a differential amplifier, which is a voltage-current conversion circuit that determines the HIGH level and the LOW level of a signal. Further, the FET of JA constitutes a DC bias current supply circuit for supplying a DC bias current to the semiconductor laser LD. A constant potential voltage Vdc is applied to the gate electrode of the FET JA, and a DC bias current is applied to the semiconductor laser LD up to near the threshold current at which light emission starts. The HIGH level and LOW level of the signal are FE
Input signals Vin and V'in to the gates of TJC and FETJD
(However, V'in represents an inverted signal of Vin)
When in is HIGH level, FET is connected via FETJC
A current flows from JB into the semiconductor laser LD, and when the bias current and the threshold current value of the semiconductor laser LD are exceeded, the semiconductor laser LD emits light. Note that R2, R3, and R4 are protective resistances, and R5 is a terminating resistance required when connecting the semiconductor laser LD via a transmission line.

[0004]

In the drive circuit as described above, when the modulation current amount actually supplied to the semiconductor laser LD is I, then I = IM.ZB / (ZL + ZB) (1) IM: Amount of modulation current supplied by the voltage-current conversion circuit ZL: Sum of impedance of terminating resistor R5 and semiconductor laser ZB: Impedance of DC bias current supply circuit The impedance ZB of the DC bias current supply circuit is: ZB = 1 / (1 / Rd1 + jω · Cgd1) (2) Rd1: JA drain resistance Cgd1: JA gate-drain capacitance ω: voltage-current conversion circuit It is represented by the modulation frequency of. The current supplied to the semiconductor laser LD may reach a maximum of 100 mA or more in total for the modulation current and the DC bias current, and the gate width of the FET JA constituting the DC bias current supply circuit needs to be large, about several hundreds of μm. In this case, Cgd1 becomes very large. Also,
In recent years, a high-speed switching with a modulation frequency exceeding 10 gigabits / second has been required, but as can be seen from the equation (2), the impedance ZB decreases as Cgd1 and the modulation frequency ω increase.

Therefore, as can be seen from the equation (1), when the impedance ZB of the DC bias current supply circuit decreases, a part of the modulation current leaks to the DC bias supply circuit and the modulation current actually supplied to the semiconductor laser LD. Quantity I
However, there is a problem that the high frequency characteristics of the drive circuit are deteriorated.

FE constituting a DC bias current supply circuit
Impedance Z is reduced by reducing the gate width of TJA and decreasing the gate-drain capacitance Cgd1 of FETJA.
There is also a method of increasing B, but this method causes a problem that the maximum value of the DC bias current that can be supplied from the DC bias current supply circuit is reduced and the maximum emission level of the semiconductor laser LD is lowered.

There is also a method of increasing the impedance ZB of the DC bias current supply circuit in the high frequency region by connecting an inductor to the drain electrode of the FETJA. In this method, the drain-gate capacitance Cgd1 of the inductor and FETJA is used. However, there is a problem that the impedance of the bias current supply circuit is significantly reduced at the frequency at which the series resonance occurs and the output signal waveform in the high frequency band is greatly deteriorated.

The present invention has been made in view of the above-mentioned problems, and it is possible to stably supply a high gain modulation signal to a DC load of a semiconductor laser or the like even in a high frequency band to improve high frequency characteristics and to operate at high speed. An object is to provide a driving circuit.

[0009]

To achieve the above object, a drive circuit according to a first aspect of the present invention is a voltage-current conversion circuit for converting a voltage signal into a current signal, and an output of this voltage-current conversion circuit. In a drive circuit including a DC load that operates according to a current signal and a bias current supply circuit that supplies a bias current to the DC load, in the bias current supply circuit, one of a collector electrode and an emitter electrode is the electrode. A transistor connected to a DC load, the other electrode of the collector electrode or the emitter electrode of the transistor is connected to the DC power source, and the base electrode of the transistor is connected to the inductor. Is.

Further, a drive circuit according to a second aspect of the present invention is a voltage-current conversion circuit composed of a differential amplifier composed of field effect transistors, and a DC circuit which operates according to an output current signal of the voltage-current conversion circuit. In a drive circuit including a load and a bias current supply circuit that supplies a bias current to the DC load, the voltage-current conversion circuit includes a first electrode in which one of a drain electrode and a source electrode is connected to the DC load. And a second field effect transistor having one of a drain electrode and a source electrode connected to the other electrode of the drain electrode and the source electrode of the first field effect transistor. The threshold value of the first field effect transistor is smaller than the threshold value of the second field effect transistor. It is.

Further, a drive circuit according to a third aspect of the present invention is a voltage-current conversion circuit composed of a differential amplifier composed of field effect transistors, and a DC circuit which operates according to an output current signal of the voltage-current conversion circuit. In a drive circuit including a load and a bias current supply circuit that supplies a bias current to the DC load, the voltage-current conversion circuit includes a first electrode in which one of a drain electrode and a source electrode is connected to the DC load. And a second field effect transistor having one of a drain electrode and a source electrode connected to the other electrode of the drain electrode and the source electrode of the first field effect transistor. The gate width of the first electric field transistor is equal to the second width.
It is characterized in that it is smaller than the gate width of the electric field transistor.

A drive circuit according to a fourth aspect of the present invention is a voltage-current conversion circuit including a differential amplifier composed of field effect transistors, and a DC circuit which operates according to an output current signal of the voltage-current conversion circuit. In a drive circuit including a load and a bias current supply circuit that supplies a bias current to the DC load, in the bias current supply circuit, one electrode of a collector electrode or an emitter electrode is the DC
The voltage-current conversion circuit includes a transistor connected to a load, and the voltage-current conversion circuit includes a first field effect transistor having one of a drain electrode and a source electrode connected to the DC load, and one of a drain electrode and a source electrode. An electrode having a second field effect transistor connected to the other electrode of the drain electrode or the source electrode of the first field effect transistor, wherein the other of the drain electrode and the source electrode of the second field effect transistor is provided. An inductor is connected to the electrode, a base electrode of the transistor forming the bias current supply circuit is connected to the other electrode of the drain electrode and the source electrode of the second field effect transistor via a capacitor, and the bias is provided. The base electrode of the transistor that constitutes the current circuit is electrically charged through a resistor. It is characterized in that it but is applied.

Further, a drive circuit according to a fifth aspect of the present invention is a voltage-current conversion circuit comprising a differential amplifier composed of field effect transistors, and a DC which operates according to an output current signal of this voltage-current conversion circuit. In a drive circuit including a load and a bias current supply circuit that supplies a bias current to the DC load, the voltage-current conversion circuit includes a first electrode in which one of a drain electrode and a source electrode is connected to the DC load. Field effect transistor, a second field effect transistor in which one electrode of the drain electrode or the source electrode is connected to the other electrode of the drain electrode or the source electrode of the first field effect transistor, and the drain electrode or the source electrode One electrode is the other electrode of the drain electrode or the source electrode of the first field effect transistor and the front electrode. A third field effect transistor connected to one of a drain electrode and a source electrode of the second field effect transistor, and the other electrode of the drain electrode and the source electrode of the second field effect transistor is an inductor. And a gate electrode of the third field effect transistor is connected to the other electrode of the drain electrode or the source electrode of the second field effect transistor via a capacitor, and the gate electrode of the third field effect transistor of The gate electrode is characterized in that a voltage is applied through a resistor.

FIG. 1 is a circuit diagram of a drive circuit according to a first aspect (claim 1) of the present invention. A field effect transistor is used as a transistor that is a constant current source of the DC bias current supply circuit. The transistor used in the present invention may be another transistor such as a bipolar transistor other than the field effect transistor.

In FIG. 1, the gate (base) of FET J1 which is a field effect transistor is connected in series with an inductor L1. Z is a DC load, Vdc is a constant potential, V
ss indicates a negative power supply voltage. In this drive circuit, DC
When the impedance ZB of the bias current supply circuit is approximated by the equivalent circuit of FIG. 2, ZB = {1-ω ² · L1 (Cdg + Cgs)} / {jω · Cdg (1 + jω · gm 1 · L1-ω ² · Cgs · L1) } (3) gm1: mutual conductance of FETJ1 Cdg: capacitance between drain (collector) and gate (base) of FETJ1 Cgs: capacitance between gate (base) and source (emitter) of FETJ1 L1: value of inductor L1 and Represented. Since ZB shows a negative resistance when L1> 0 from the equation (3), the value of the current I supplied to the load is −∞ <ZB <−ZL from the equation (1) (in this case, ZL is the DC load Z In the region of I.), I (the amount of modulation current supplied to the DC load)> IM (the amount of modulation current supplied by the voltage-current conversion circuit).

Therefore, in the frequency band where the amount of modulation current applied to the DC load of the drive circuit decreases, the drive circuit can be peaked by making the value of the impedance ZB of the DC bias current supply circuit approach -ZL. Therefore, it is possible to prevent the modulation current amount applied to the DC load from decreasing. That is, the gist of the present invention is to make the impedance of the DC bias current supply circuit negative resistance by using the inductor L1 and prevent the decrease of the modulation current amount applied to the DC load.

In the present invention, it is desirable that the relationship between the frequency f (Hz) of the signal input to the voltage-current conversion circuit and the inductor L1 be as follows. When the signal input to the voltage-current conversion circuit is X (bits / second), X
The frequency of the signal of 101010 ... (Bit / second) is X / 2 (Hz). Therefore, when the drive circuit according to the present invention is used with an X (bit / sec) signal, the frequency characteristic of the modulated current signal must be flat at least within the range of f (Hz) ≤ X / 2 (Hz). Therefore, when ω = πX (= 2πX / 2) is substituted into the equation (3), the inductor L is set so that the value of ZB satisfies -∞ <ZB <-ZL.
A value of 1 may be set.

FIG. 3 is a diagram showing frequency characteristics of the amount of modulation current applied to the DC load of the drive circuit of the present invention. The characteristic indicated by A in the figure is the characteristic of the drive circuit according to the first aspect of the present invention, and the characteristic indicated by B is the characteristic of the conventional drive circuit without the inductor L1. This is a simulation having a circuit configuration capable of outputting a bias current of 60 mA from the DC bias current supply circuit and 50 mA from the modulation circuit. As described above, in the conventional driving circuit, the modulation current amount starts to decrease from around 3.0 Gh (GHz), but in the present invention, the modulation current amount does not change up to around 10 Gh. That is, the drive circuit according to the present invention can provide a drive circuit that stably drives in a wide frequency band.

The inductor used in the present invention may be a spiral inductor, a short stub transmission line, or the like, and can be integrated on an IC.
At this time, the size of the inductor L1 is 0.1 nH
To about 10 nH, preferably about 0.1 nH to 5 nH, it becomes possible to integrate on an IC in a relatively small area.

Further, in the present invention, when the inductor L1 is designed to have a high frequency band of 10 Gbit / sec or more and is integrated on an IC, the size of the inductor L1 is set to 3 nH or less so that the self-resonance of the inductor (for example, a spiral inductor) is suppressed. It can be used in the frequency band to reduce the influence.

FIG. 4 shows a circuit diagram of a drive circuit according to the second and third aspects (claims 2 and 3) of the present invention. Figure 4
In the FET constituting the switch portion of the differential amplifier, the threshold Vth4 of the FET J4 whose drain electrode is connected to the ground through the resistor R2 and the FET J3 whose drain is connected in series to the DC load. Threshold value V
By setting the relationship of th3 to Vth4> Vth3, the amount of current flowing into the DC load increases by ΔI as compared with the conventional drive circuit. This means that the bias current from the voltage-current conversion circuit, which is the modulation circuit, can be supplied by ΔI more than the conventional drive circuit. This shows the following effects. (1) When the DC bias current supply circuit is composed of FETs, the gate width of the constant current source FET of the DC bias current supply circuit can be reduced by the increase ΔI of the bias current. Therefore, the gate-drain capacitance of the FET of the DC bias current supply circuit can be reduced by the amount that the gate width of the FET of the DC bias current supply circuit is reduced, and the decrease in impedance of the DC bias current supply circuit can be reduced. The leakage of the modulation current of the current conversion circuit can be reduced. Therefore, DC is stable even in the high frequency band.
It becomes possible to supply an electric current. (2) Since the current of the DC bias current supply circuit can be reduced by ΔI, power consumption can be reduced.

The drive circuit according to the third aspect of the present invention is an FE.
The relationship between the gate width W3 of TJ3 and the gate width W4 of FETJ4 is set as W4> W3. By doing this,
The value of (modulation current) / (input voltage) indicating the ratio of the modulation current amount to the input voltage of the drive circuit increases, and FETJ3
The relation between the gate width W3 of FET4 and the gate width W4 of FETJ4 is W
Since the amplitude value of the modulation current can be made larger than that in the case of 3 = W4, it becomes possible to obtain a signal having a sharper rise and fall and a high gain.

FIG. 5 shows the relationship between the potential difference .DELTA.V (Vin-V'in) of the differential input signals and the modulation current amount applied to the DC load in the drive circuit shown in FIG. However, V'in indicates an inverted signal of Vin. The characteristic indicated by A in the figure is the characteristic of the drive circuit according to the second aspect of the present invention, and is the threshold V of the FET J3.
th3 = -0.6V, gate width W3 = 170 μm, FET
J4 threshold Vth4 = -0.2V, gate width W4 = 1
The characteristics are shown when the thickness is 70 μm. The characteristic shown in B is the characteristic of the drive circuit according to the second and third aspects of the present invention,
Threshold voltage Vth3 of FETJ3 = -0.6V, gate width W
3 = 170 μm, threshold value Vth4 of FET J4 = −0.
The characteristics are shown when 2 V and the gate width W4 = 200 .mu.m. The characteristic indicated by C is the characteristic of the conventional drive circuit in which the two FETs of the differential amplifier of the voltage-current conversion circuit have the same threshold value and the same gate width. Thus, ΔI can be increased by making the threshold value of FETJ3 smaller than that of FETJ4, and making the gate width of FETJ3 smaller than that of FETJ4 (modulation current) / (Input voltage) = gradient can be increased.

In the drive circuit according to the third aspect of the present invention, as a means for improving the gain of (modulation current) / (input voltage), a method of making the gate width of FETJ4 larger than the gate width of FETJ3 is provided. Used, but conversely FET
The gate width of J3 may be increased. That is, the gain can be improved by making the gate width of at least one FET larger than the gate width of the other FET.

FIG. 14 shows a fourth mode of the present invention (claim 4).
2 is a circuit diagram of a driving circuit that is A field effect transistor is used as a transistor that is a constant current source of the DC bias current supply circuit. In addition to the field effect transistor, another transistor such as a bipolar transistor may be used.

In FIG. 14, the FET J1 is a DC load Z.
Is a field-effect transistor used as a circuit for supplying a bias current to the DC load Z, and the source electrode is connected to the negative power supply voltage Vss.
FETs J2, J3, and J4 are field-effect transistors that form a differential amplifier circuit. The drain electrode of FETJ3 is connected to the DC load Z and the drain electrode of FETJ1.
The source electrode is connected to the source electrode of FETJ4 and the drain electrode of FETJ2. Further, the drain electrode of the FET J4 is connected to the ground via the inductor L1, and the source electrode of the FET J2 is connected to the negative power supply voltage Vss. The drain electrode of the FET J4 is AC-connected to the gate electrode of the FET J1 via the capacitor C1. The gate electrode of the FET J1 is connected to the constant potential Vdc via the resistor R1. R2 and R3 are protective resistors.

In the circuit according to the fourth aspect of the present invention as described above, the phase of the AC current flowing through the drain of the FET J4 is opposite to the direction of the AC current flowing through the DC load Z,
The drain voltage of the FET J4 also has the opposite phase. Therefore, by applying the drain voltage of the opposite phase to the gate electrode of the FET J1 via the capacitor C1,
The direction of the AC current flowing through the drain electrode of 1 is DC load Z
The current has the same phase as the AC current flowing through the DC load Z, and the peaking is applied to the current flowing through the DC load Z. Therefore, DC in the high frequency band
It is possible to compensate for the characteristic deterioration of the current signal flowing through the load Z.

FE constituting a DC bias current supply circuit
When the gate width of T exceeds 100 μm, the value of the gate-source capacitance Cgd1 of the FET increases, so the FET
When the load connected to the drain electrode of J4 is only the resistor R2, that is, when there is no inductor L1, the phase of the voltage applied to the gate of the FET J1 via the capacitor C1 is delayed from the phase of the AC current flowing through the DC load Z. The above effect does not appear.

In the circuit according to the fourth aspect of the present invention, the FET
By adding the inductor L1 as a load connected to the drain electrode of J4, the phase of the drain voltage of the FET J4 can be advanced, and the signal deterioration becomes large even when the gate-drain capacitance Cgd1 of the FET J1 is large. It becomes possible to apply peaking with.
At this time, assuming that the value of C1 is C1 and the value of R1 is R1, peaking occurs in a frequency region f that satisfies “2π · f · R1 · C1 to 1 (to represent near equol, the same applies below). Therefore C
It suffices to control the values of 1 and R1 so that peaking is applied in the frequency region where the influence of the characteristic deterioration of the current signal flowing through the DC load Z is large.

FIG. 15 shows frequency characteristics of the amount of modulation current applied to the DC load of the drive circuit shown in FIG. In the figure, the characteristic indicated by A is the characteristic of the drive circuit according to the fourth aspect of the present invention, and the characteristic indicated by B is the inductor L1 and the capacitor C1.
This is a characteristic of a conventional drive circuit that does not have. This is a simulation having a circuit configuration capable of outputting a bias current of 60 mA from the DC bias current supply circuit and 50 mA from the modulation circuit. When the value of the inductor L1 is 0.2 nH, the value of the capacitor C1 is 150 fF, and the resistance 1 is 200 Ω, the current drive characteristic of the drive circuit according to the fourth aspect of the present invention shows a substantially flat characteristic up to around 8 GHz. It can be seen that a significant improvement in characteristics can be achieved as compared with the case where the circuit does not exhibit flat characteristics up to around 2 GHz.

In the fourth aspect of the present invention, the inductor L
Even if 1 is provided between the drain electrode of the FET J4 and the gate electrode of the FET J1, its effect can be expected. FIG. 21 shows a circuit diagram of a drive circuit according to a fifth aspect (claim 5) of the present invention.

The FETs J2, J3, and J4 are field-effect transistors that form a differential amplifier circuit. The drain electrode of the FET J3 is connected to the DC load Z and the DC current supply circuit, and the source electrode is the source electrode of the FET J4 and the differential amplifier. It is connected to the drain electrode of FETJ2 that constitutes the constant current source of the circuit. Further, the drain electrode of the FET J4 is connected to the ground via the inductor L1, and the source electrode of the FET J2 is connected to the negative power supply voltage Vss. Further, the drain electrode of FETJ4 is F through the capacitor C1.
It is AC-connected to the gate electrode of ETJ2. The gate electrode of the FET J2 is connected to the external bias terminal Vac via the resistor R1. R2 is a protective resistor.

In the circuit according to the fifth aspect of the present invention, the FET
By adding the inductor L1 as a load connected to the drain electrode of J4 to advance the phase of the drain voltage of the FET J4, the peaking occurs in a high frequency region where the signal deterioration is large even when the gate-drain capacitance Cgd1 of the FET J1 is large. It is possible to apply. At this time, assuming that the value of C1 is C1 and the value of R1 is R1, peaking occurs in the frequency region f that satisfies 2π · f · R1 · C1 to 1. Therefore C
It suffices to control the values of 1 and R1 so that peaking is applied in the frequency region where the influence of the characteristic deterioration of the current signal flowing through the DC load Z is large.

In the fifth aspect of the present invention, the inductor L
The effect can be expected even if 1 is provided between the drain electrode of the FET J4 and the gate electrode of the FET J2. Further, when the drive circuit according to the second or third aspect of the present invention and the drive circuit according to the fourth or fifth aspect are used together, the FET J4 to which the DC load is not connected is also used. Since the value of (modulation current) / (input voltage) becomes large, the amount of peaking can be increased, and a better effect can be obtained.

FIG. 22 shows a drive circuit using the drive circuit according to the second or third aspect of the present invention and the drive circuit according to the fourth or fifth aspect in combination at 10 Gbit / sec. The output signal waveform corresponding to the (01011011) input signal is simulated and compared with the drive circuit of the conventional example (FIG. 23). A is the characteristic of the present invention, and B is the characteristic of the conventional example. Thus, it can be seen that the drive circuit according to the present invention is more excellent in high frequency characteristics than the conventional one.

The inductor used in the present invention may be a spiral inductor or a short-tab transmission line, but the value of the inductor used in the circuit configuration of the present invention can be as small as about 0.2 nH, so that it is sufficiently small on the IC. It can be integrated in area. Moreover, since the value of the inductor used is small, the self-resonance frequency of the inductor also becomes high, and the adverse effect of the resonance of the inductor can be avoided.

[0037]

In the first aspect of the present invention, by connecting an inductor in series to the base electrode of the transistor of the DC bias current supply circuit, the impedance of this DC bias current supply circuit can be made a negative resistance. DC even in the high frequency band without reduction of modulation current
It becomes possible to supply a modulation current to the load.

In the second aspect of the present invention, one of the two FETs of the differential amplifier of the voltage-current conversion circuit is used.
By making the threshold value of the other FET different from that of the other FET, the flowing current can be made different, so that the power consumption of the drive circuit can be reduced and the modulation current can be stably supplied even in the high frequency band.

In the third aspect of the present invention, one of the two FETs of the differential amplifier of the voltage-current conversion circuit is used.
By making the gate width of the FET different from that of the other FET, the value of (modulation current) / (input voltage) indicating the ratio of the modulation current amount to the input voltage of the drive circuit is increased and the amplitude value of the modulation current is increased. Therefore, it is possible to obtain a signal having a sharper rise and fall and a high gain.

In the fourth aspect of the present invention, the phase of the current flowing through the grounded electrode of the field effect transistor J4 forming the differential amplifier circuit is opposite to the phase of the current flowing through the DC load. Field effect transistor J
4 has the same phase as the input signal to the gate of the field effect transistor J3 connected to the DC load.
Therefore, by applying the drain voltage of the field-effect transistor to the gate electrode of the field-effect transistor J1 via the capacitor, it is possible to peak the DC load and obtain a desired modulation current even in a high frequency band. .

In the fifth aspect of the present invention, the phase of the current flowing through the grounded electrode of the field effect transistor J4 forming the differential amplifier circuit is opposite to the phase of the current flowing through the DC load. Field effect transistor J
4 has the same phase as the input signal to the gate of the field effect transistor J3 connected to the DC load.
Therefore, by applying the drain voltage of the field effect transistor J4 to the gate electrode of the field effect transistor J2 via the capacitor, the amount of drive current increases in the high frequency region, and it becomes possible to peak the DC load, which is desirable even in the high frequency band. It is possible to obtain the modulation current of.

[0042]

FIG. 6 is a circuit diagram of a semiconductor laser drive circuit according to a first embodiment of the present invention. Although the voltage-current conversion circuit is composed of a differential amplifier in the following, other circuits such as a source-grounded amplifier and a gate-grounded amplifier may be used.

A differential amplifier is formed by the FETs J2, J3, and J4, and is a voltage-current conversion circuit that determines the HIGH level and the LOW level of the signal. Vac is a DC voltage applied to the gate electrode of FETJ2. In addition, FETJ1
Is a semiconductor laser L whose drain electrode is a DC load.
By being connected to D, it is used as a DC bias current supply circuit that supplies a DC bias current to a DC load.

Further, capacitors C1 and C2 are connected between the drain and the gate and between the source and the gate of the FET J1, and an inductor L1 is connected to the gate electrode and a resistor R.
A voltage Vdc having a constant potential is applied via 1. At this time, the FET J1 applies a DC bias current to the semiconductor laser LD up to near the threshold current at which light emission starts. The HIGH level and the LOW level of the signal are determined by the input signals Vin and V'in to the gates of J3 and J4, and Vin is HIGH.
In case of level, semiconductor laser LD from J2 through J3
A current flows into the semiconductor laser LD, and when it exceeds the threshold current value of the semiconductor laser LD together with the DC bias current, the semiconductor laser LD emits light. Note that R2 and R3 are protection resistors, and R5 is a terminating resistor that is required when connecting the semiconductor laser via a transmission line. Vss represents a negative power supply voltage.

As shown in this embodiment, a capacitor C1 is provided between the drain and the gate of the FET J1 and between the source and the gate of the FET J1.
By connecting C2, the negative resistance ZB of the DC bias current supply circuit is activated, and the frequency band capable of preventing the decrease of the modulation current can be adjusted. That is, it is possible to obtain a desired modulation current-frequency characteristic by appropriately selecting the size of the capacitor according to the frequency at which the modulation current amount of the drive circuit decreases. This effect can be expected by introducing both of the capacitors C1 and C2, or by expecting only one of them.

For example, when the drain-gate capacitance of the FET J1 is Cdg1 and the gate-source capacitance is Cgs1, Cdg = Cdg1 + C1 and Cgs = Cgs1 + in the equation (3) by adding capacitors C1 and C2.
Since it becomes C2, it is possible to reduce the frequency at which peaking occurs and to reduce the value of the inductor L1.

Since the peaking amount can be controlled by adjusting the value of the resistor R1 inserted in series with the inductor L1, the desired modulation current can be obtained by selecting the peaking amount according to the decrease in the modulation current amount of the drive circuit. -It becomes possible to obtain frequency characteristics. For example, by appropriately adjusting the value of R1, it is possible to suppress the decrease of the modulation current in the high frequency band and flatten the frequency characteristic of the modulation current.

Therefore, when the peaking is excessively caused when only the inductor is used, the value of R1 can be increased to flatten the frequency characteristic of the modulation current and suppress the ringing of the output signal caused by the excessive peaking.

When used at 10 Gbit / sec in this embodiment, the value of the inductor L1 is 0.3 nH to 1 nH, and good characteristics can be obtained. In this embodiment, as shown in FIG. 7, by inserting the reactance element Za between the drain electrode and the source electrode of the FET J1, the frequency at which peaking occurs and the peaking amount can be adjusted. A resistor, a FET, or the like can be used as the reactance element. When using a FET, it is desirable to apply a voltage of a constant potential to its gate electrode.

At this time, particularly when an FET is used as the reactance element Za, the DC bias current amount biased by the FET J1 to the semiconductor laser LD which is a DC load is IJ1, and the FET of the reactance element Za is biased to the semiconductor laser LD. When the DC bias current amount is set to IZa, an appropriate peaking amount can be obtained when IJ1 ≧ IZa. For example, when the threshold of the FET J1 and the threshold of the FET as the reactance element Za are the same, if the gate width of the FET J1 is WJ1 and the gate width of the FET of the reactance element Za is WZa, then WJ1 ≧ W
This can be achieved by using Za.

FIG. 8 is a circuit diagram of a semiconductor laser drive circuit according to a second embodiment of the present invention. The configuration of the voltage-current conversion circuit is the same as that of the first embodiment, so detailed description will be omitted.

In the DC bias current supply circuit, an inductor L1 is connected to a gate electrode, a drain electrode is connected to a semiconductor laser LD as a DC load, and a source electrode is connected to a source electrode of the FET J1. Is constituted by a FET J5 connected to the power source Vss. Vb and Vdc are FETJ1 and FETJ5
Is a constant potential voltage applied to the gate electrode of. C
Reference numerals 1 and C2 are capacitors connected between the drain and gate of FETJ1 and between the source and gate, respectively, and C3 is a capacitor connected between the drain and gate of FET5. R
Reference numeral 1 is a resistor connected in series with the inductor L1.

The capacitors C1, C2 and C3 have the same function as in the first embodiment, and are used for adjusting the frequency to which peaking is applied. The resistor R1 is also used for adjusting the peaking amount, as in the first embodiment.

The drain-gate capacitance of the FET J1 is C
If dg1, the gate-source capacitance is Cgs1, and the drain-gate capacitance of the FET5 is Cdg5, the values of Cdg and Cgs in the equation (3) are Cdg = Cdg1 + C1 and Cgs = 1 /.
It can be approximated as {1 / (Cgs1 + C2) + 1 / (Cdg5 + C3)}. In this embodiment, the gate width of the FET J1 is reduced to reduce the values of Cdg and Cgs, and the frequency at which peaking occurs can be made higher than that in the first embodiment.

When used at 10 Gbit / sec in this embodiment, the value of the inductor L1 is 0.8 nH to 2 nH, and good characteristics can be obtained. Also in this embodiment, as shown in FIG. 7, by inserting the reactance element Za into the drain electrode and the source electrode of the FET J1, the frequency at which peaking occurs and the peaking amount can be adjusted. When an FET is used, a voltage of constant potential is applied to its gate electrode.

FIG. 9 is a circuit diagram of a semiconductor laser drive circuit according to the third embodiment of the present invention. The configuration of the voltage-current conversion circuit is the same as that of the first embodiment, so detailed description will be omitted.

In the DC bias current supply circuit, the inductor L1 is connected to the gate electrode, the drain electrode is connected to the semiconductor laser LD which is a DC load, and the drain electrode is connected to the semiconductor laser LD, and the source electrode is connected to the power supply. It is composed of a FET J5 connected to Vss. Vdc1 and Vdc2 are constant potential voltages applied to the gate electrodes of FETJ1 and FETJ5. C1, C
Reference numeral 2 is a capacitor connected between the drain-gate and the source-gate of the FET J1. R1 is a resistor connected in series with the inductor L1.

In this embodiment, the DC bias current supply amount applied to the load is adjusted mainly by changing the bias voltage of the FET J5, so that the change in the bias current amount can be minimized and the peaking can be achieved. It is possible to suppress the fluctuation of the frequency that is applied.

When using a drive circuit in an actual system,
The heat generated by the driving circuit or the like causes the threshold value of the semiconductor laser to fluctuate, resulting in a problem that the emission level fluctuates. As a countermeasure, a system for monitoring the light emission level around the semiconductor laser and providing a feedback to the DC bias current supply circuit may be provided to keep the light emission level constant. In this embodiment, the feedback is FETJ5.
It is possible to suppress the fluctuation of the frequency to which peaking is applied by applying the signal to the gate of the.

When used at 10 Gbit / sec in this embodiment, the value of the inductor L1 is 0.3 nH to 1 nH, and good characteristics can be obtained. Also in this embodiment, as shown in FIG. 7, by inserting the reactance element Za into the drain electrode and the source electrode of the FET J1, the frequency at which peaking occurs and the peaking amount can be adjusted. When an FET is used, a voltage of constant potential is applied to its gate electrode.

FIG. 10 is a circuit diagram of a semiconductor laser drive circuit according to the fourth embodiment of the present invention. The configuration of the voltage-current conversion circuit is the same as that of the first embodiment, so detailed description will be omitted.

In the DC bias current supply circuit, the inductor L1 is connected to the gate electrode, the drain electrode is connected to the semiconductor laser LD which is a DC load, and the drain electrode is connected to the source electrode of the FET J1.
The FET J5 has a source electrode connected to the power supply Vss, and the FET J6 has a drain electrode connected to the semiconductor laser LD and a source electrode connected to the power supply Vss. Vb, Vdc1 and Vdc2 are FETJ1 and FETJ5
And a voltage of constant potential applied to the gate electrode of the FET J6. C1 and C2 are capacitors connected between the drain and gate and the source and gate of FET J1, C3
Is a capacitor connected between the drain and gate of the FET 5. R1 is a resistor connected in series with the inductor L1.

Also in this embodiment, the same effect as that of the third embodiment can be expected. When used at 10 Gbit / sec in this embodiment, the value of the inductor L1 is 0.8.
Good characteristics can be obtained from nH to 2 nH.

Also in this embodiment, as shown in FIG.
By inserting the reactance element Za into the drain electrode and the source electrode of the ETJ1, the peaking frequency and the peaking amount can be adjusted. When using a FET, it is desirable to apply a voltage of a constant potential to its gate electrode.

FIG. 11 is a circuit diagram of a semiconductor laser drive circuit according to the fifth embodiment of the present invention. The configuration of the voltage-current conversion circuit is the same as that of the first embodiment, so detailed description will be omitted.

The present embodiment has substantially the same structure as the semiconductor laser drive circuit shown in the fourth embodiment, and one of the resistors R1 connected in series to the inductor L1 and the other of which is the current-voltage conversion circuit. It is connected to the drain electrode of the FET J2 of the dynamic amplifier.

In this embodiment, when the differential amplifier, which is a current conversion circuit, has two-phase inputs, FETJ3 and FET
The point at which the source of J4 is coupled, that is, the voltage of the drain electrode of FET J2 is constant. By using the voltage of the drain electrode of the FET J2 as the bias for applying the voltage to the gate of the FET J1, it is possible to reduce the power consumption without providing an additional bias circuit.

The compensation current I (the amount of current supplied to the DC load) in the high frequency band generated by the DC bias current supply circuit of this embodiment having a negative resistance-IM (the voltage-current conversion circuit supplies it). The modulation current amount) is supplied to the DC load through the following two paths.

First, the resistance R1 and the inductor L are changed from Vac which is a high frequency GND seen from the DC bias current supply circuit.
1 to be supplied to the DC load through the second, secondly Vdc1 which is the high frequency GND seen from the DC bias current supply circuit
From the FET through FET J5 to the DC load. The current amount of the former is I1, and the constant current source F of the differential amplifier is
Assuming that the amount of current supplied by ETJ2 is Ia, the current that can be driven by the differential amplifier is Ia + I1. I1 is direct DC
Positive when FET J3 connected to the load is ON, F
It becomes negative when ETJ3 is OFF, so Ia + I1 is F
It increases when ETJ3 is ON and decreases when FETJ3 is OFF. Therefore, the rising and falling edges of the signal output from the differential amplifier become sharp, and the peaking amount of the modulation current can be further amplified.

When used at 10 Gbit / sec in this embodiment, the value of the inductor L1 is 0.8 nH to 2 nH, and good characteristics can be obtained. Also in this embodiment, as shown in FIG. 7, by inserting the reactance element Za into the drain electrode and the source electrode of the FET J1, the frequency at which peaking occurs and the peaking amount can be adjusted. When using a FET, it is desirable to apply a voltage of a constant potential to its gate electrode.

FIG. 12 is a circuit diagram of a semiconductor laser drive circuit according to the sixth embodiment of the present invention. Among the FETs forming the switch part of the differential amplifier which is the voltage-current conversion circuit, the relationship between the threshold Vth4 and the gate width W4 of the FET J4 and the thresholds Vth3 and W3 of the FET J3 whose drain is connected in series to the DC load. Vth3 <Vth4, W3 <W4
And

Specifically, the threshold value Vth3 of the FET J3 is
Is -0.6 V, gate width W3 is 170 μm, and FETJ
4 threshold value Vth4 is -0.2V, gate width W4 is 20
It was set to 0 μm. The DC bias current supply circuit is an FET
The drain electrode is connected to the semiconductor laser LD, which is a DC load, via the resistor R5, and the source electrode is connected to the power supply.

In this embodiment, ΔV (Vin-V'in) = 0
At that time, the current value output from the modulation circuit is 6.8 mA higher than that of the comparative example in which the gate electrodes of FETJ3 and FETJ4 have the same threshold voltage, and the current supply amount from the bias current circuit is 60 mA. Then, a bias current of 10% or more can be supplied from the modulation circuit. Further, for an input signal of 1 Vpp having the same amplitude value of the modulation current, the value of 53.4 mApp according to the present embodiment is approximately 6% larger than that of 50.2 mApp according to the comparative example.

FIG. 13 shows a combination of the first embodiment and the sixth embodiment, that is, the DC bias current supply circuit according to the first embodiment is used, and the voltage-current conversion circuit is the sixth embodiment. Of the semiconductor laser drive circuit using the
This is a simulation of the output signal waveform for the 10 Gbit / sec input signal pattern of 0110). A
Is an embodiment of the present invention, and B is a comparative example in which two transistors of the voltage-current conversion circuit have the same threshold value and gate width and an inductor is not connected to the gate electrode of the FET of the DC bias current supply circuit. Is a characteristic of.

According to the embodiment of the present invention shown in FIG.
It can be seen that it is possible to obtain characteristics having higher high frequency characteristics with less power consumption than the comparative example. In each of the above-described embodiments, the example in which the capacitor is inserted between the gate and the drain, between the gate and the source of the FET as the DC bias current supply circuit has been described, but the present invention is not limited to these examples. In addition to the semiconductor laser, a resistor, a diode, or the like can be used as the DC load.

FIG. 16 is a circuit diagram of a semiconductor laser drive circuit according to the seventh embodiment of the present invention. A field effect transistor is used as a transistor that is a constant current source of the DC bias current supply circuit.

In FIG. 16, FETJ1 is a field effect transistor used as a circuit for supplying a bias current to the semiconductor laser LD which is a DC load, the drain electrode is connected to the semiconductor laser LD, and the source electrode is connected to the negative power supply voltage Vss. It is connected. FETs J2, J3, and J4 are field effect transistors that form a differential amplifier circuit,
The drain electrode of the FET J3 is a semiconductor laser LD or FE.
It is connected to the drain electrode of TJ1 and the source electrode is FET
It is connected to the source electrode of J4 and the drain electrode of FET J2. Further, the drain electrode of the FET J4 is connected to the ground via the inductor L1, and the source electrode of the FET J2 is connected to the negative power supply voltage Vss. Also FE
The drain electrode of TJ4 is FET through the capacitor C1.
It is AC-connected to the gate electrode of J1. Also FE
The gate electrode of TJ1 is connected to a constant potential Vdc via a resistor R1. R2 and R3 are protection resistors, and R5 is a terminating resistor required when connecting the semiconductor laser LD via a transmission line.

In the semiconductor laser drive circuit according to the seventh embodiment of the present invention as described above, the phase of the AC current flowing through the drain of the FET J4 is opposite to the direction of the AC current flowing through the DC load Z, and the drain voltage of the FET J4 is also equal. The phase is opposite to this. Therefore, by applying this opposite-phase drain voltage to the gate electrode of the FET J1 via the capacitor C1, the direction of the AC current flowing through the drain electrode of the FET J1 becomes the same phase as the AC current flowing through the DC load Z, and D
Peaking is applied to the current flowing through the C load Z. Therefore, it becomes possible to compensate for the characteristic deterioration of the current signal flowing through the DC load Z in the high frequency band.

FIG. 17 is a circuit diagram of a semiconductor laser drive circuit according to the eighth embodiment of the present invention. The resistor R1 of the semiconductor laser drive circuit of the seventh embodiment shown in FIG. 16 is divided into resistors R11 and R12, R11 is interposed between the gate electrode of FETJ1 and the capacitor C1, and R12 is FETJ.
It is interposed between the first gate electrode and the external terminal Vdc. When an inductor and a resistor are actually integrated in an IC, the characteristics of what can actually be obtained may differ from the designed value. However, since the required inductance value of the inductor is small, when the inductance value deviates from the design, There is a possibility that peaking will not be applied in the frequency band of. In this embodiment, the amount of peaking applied to the gate of the FET J1 is set to R12 / (R11 + R) by R11 and R12.
By setting 12), it is possible to suppress the fluctuation of the characteristics when the inductance value deviates from the design. Therefore, according to such a configuration, the amount of peaking can be easily adjusted and stable characteristics can be exhibited.

FIG. 18 is a circuit diagram of a semiconductor laser drive circuit according to the ninth embodiment of the present invention. In addition to the semiconductor laser drive circuit of the seventh embodiment shown in FIG.
Resistor R2 and inductor L between the drain electrodes of ETJ4
A capacitor is newly provided in parallel with 1. Inductor L1
Self-resonance (parallel resonance) causes the impedance of the inductor to rapidly increase near the resonance point. When the resonance frequency of the inductor is equal to or lower than the maximum operating frequency of the output signal of the circuit, the signal applied to the gate of the FET J1 via the capacitor C1 also sharply increases, causing excessive peaking and adversely affecting the output signal. In this embodiment, a resistor R2 and a capacitor C1 are newly provided in parallel with the resistor R2 and the inductor L1 between the ground and the drain electrode of the FET J4. With such a configuration, the load impedance of the FET J4 composed of R1, L1, and C1 does not suddenly increase even when the inductor L1 self-resonates, and stable characteristics can be exhibited. Become.

In this embodiment, the resistor R2 and the capacitor C
2. The inductor L1 can be integrated inside the IC. In addition, the drain electrode of the FET J4 is I / O such as a pad.
It is also possible to provide a resistor R2, an inductor L1, and a capacitor C2 by connecting to the O terminal. In this case, the capacitance of the pair of pads may be the capacitor C2. Further, since the resistors are externally attached, the values of the resistor R1 and the inductor L1 can be easily changed, so that the peaking amount can be easily adjusted.

FIG. 19 is a circuit diagram of a semiconductor laser drive circuit according to the tenth embodiment of the present invention. The seventh shown in FIG.
The semiconductor laser drive circuit of the embodiment described above is further provided with a new capacitor C3 in parallel with the resistor R2.
It is possible to prevent the peaking from becoming excessive for the same reason as in the above embodiment.

At this time, the resistor R2 and the capacitor C2 are connected to the IC.
Although it can be integrated inside, the inductor L1 is connected to an I / O terminal such as a pad, and a resistor R2 is provided outside the IC.
It is also possible to provide. At this time, a chip resistor or the like is used as the resistor R1. In this case, the paired capacitance of the pads plays the role of the capacitor C3. Further, since the values of the resistor R1 and the inductor L1 can be easily changed, the peaking amount can be easily adjusted.

FIG. 20 is a circuit diagram of a semiconductor laser drive circuit according to the eleventh embodiment of the present invention. The seventh shown in FIG.
In addition to the FET J1 as the DC bias current supply circuit, the FET for supplying the DC bias current is further divided in the semiconductor laser drive circuit of the embodiment of the present invention, and only one of them is peaked. It is possible to suppress variation in characteristics when the inductance value deviates from the design.

FIG. 23 is a circuit diagram of a semiconductor laser drive circuit according to the twelfth embodiment of the present invention. FET J2, J
Reference numerals 3 and J4 are field effect transistors that form a differential amplifier circuit. The drain electrode of FETJ3 is connected to the semiconductor laser LD that is a DC load and the field effect transistor FETJ1 that is a DC current supply circuit, and the source electrode is FE.
It is connected to the source electrode of TJ4 and the drain electrode of FETJ2 that constitutes the constant current source of the differential amplifier circuit. Further, the drain electrode of the FET J4 is connected to the ground via the inductor L1, and the source electrode of the FET J2 is connected to the negative power supply voltage Vss. The drain electrode of the FET J4 is AC-connected to the gate electrode of the FET J2 via the capacitor C1. The gate electrode of the FET J2 is connected to the external bias terminal Vac via the resistor R1. R2 and R3 are protective resistors, and R5 is a terminating resistor required when connecting the semiconductor laser LD via a transmission line.

In the laser drive circuit according to the twelfth embodiment of the present invention, the phase of the current flowing through the grounded electrode of the field effect transistor J4 forming the differential amplifier circuit is D
The phase is opposite to the phase of the current flowing in the C load, and the drain voltage of the field effect transistor J4 is now in phase with the input signal to the gate of the field effect transistor J3 connected to the DC load. Therefore, the field effect transistor J4
By applying the drain voltage of 1 to the gate electrode of the field effect transistor J2 via the capacitor, the amount of drive current increases in the high frequency region, and it becomes possible to peak the DC load, and a desired modulation current is obtained even in the high frequency band. It becomes possible.

FIG. 24 is a circuit diagram of a semiconductor laser drive circuit according to a modification of the seventh embodiment. A resistor R2 and an I / O terminal such as an IC pad are further connected to the semiconductor laser drive circuit of the seventh embodiment, and a bonding wire is connected to GND as an inductor L2. Peaking is applied using the inductor component of wire bonding.
Although L1 is an inductor built in the IC, this inductor L1 may be omitted. Since the inductance value can be adjusted by changing the length of the bonding wire, the peaking amount can be easily adjusted.

FIG. 25 is a circuit diagram of a semiconductor laser drive circuit according to a modification of the seventh embodiment. In the semiconductor laser drive circuit of the seventh embodiment, the load of the FET J4 is set to the resistance R.
With only 2, the signal at the drain of the FET J4 is input to the gate of the FET J1 via the inductor L1 and the capacitor C1 for peaking. 10G in this modification
When used at bits per second, the inductor value is 0.8
Good characteristics can be obtained from nH to 2 nH. Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications can be applied within the scope of the invention.

[0089]

As described above, since the drive circuit according to the present invention can stably supply the DC bias current in the high frequency band, it is possible to provide a drive circuit suitable for high speed operation. Is possible.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a drive circuit of the present invention.

FIG. 2 is an equivalent circuit diagram of a DC bias current supply circuit of a drive circuit of the present invention.

FIG. 3 is a diagram comparing a modulation current amount frequency characteristic of a drive circuit of the present invention with a comparative example by simulation.

FIG. 4 is a circuit diagram of a drive circuit of the present invention.

FIG. 5 is a diagram comparing the modulation current amount input voltage characteristic of the drive circuit of the present invention with a comparative example by simulation.

FIG. 6 is a circuit diagram of a semiconductor laser drive circuit according to a first embodiment of the present invention.

FIG. 7 is a circuit diagram of a semiconductor laser drive circuit according to a second embodiment of the present invention.

FIG. 8 is a circuit diagram of a semiconductor laser drive circuit according to a second embodiment of the present invention.

FIG. 9 is a circuit diagram of a semiconductor laser drive circuit according to a third embodiment of the present invention.

FIG. 10 is a circuit diagram of a semiconductor laser drive circuit according to a fourth embodiment of the present invention.

FIG. 11 is a circuit diagram of a semiconductor laser drive circuit according to a fifth embodiment of the present invention.

FIG. 12 is a circuit diagram of a semiconductor laser drive circuit according to a sixth embodiment of the present invention.

FIG. 13 is a diagram comparing the output waveform of the drive current amount of the drive circuit of the present invention with a comparative example by simulation.

FIG. 14 is a circuit diagram of a drive circuit of the present invention.

FIG. 15 is a diagram comparing the modulation current amount frequency characteristic of the drive circuit of the present invention with a comparative example by simulation.

FIG. 16 is a circuit diagram of a semiconductor laser drive circuit according to a seventh embodiment of the present invention.

FIG. 17 is a circuit diagram of a semiconductor laser drive circuit according to an eighth embodiment of the present invention.

FIG. 18 is a circuit diagram of a semiconductor laser drive circuit according to a ninth embodiment of the present invention.

FIG. 19 is a circuit diagram of a semiconductor laser drive circuit according to a tenth embodiment of the present invention.

FIG. 20 is a circuit diagram of a semiconductor laser drive circuit according to an eleventh embodiment of the present invention.

FIG. 21 is a circuit diagram of a drive circuit of the present invention.

FIG. 22 is a diagram comparing the output waveform of the drive current amount of the drive circuit of the present invention with a comparative example by simulation.

FIG. 23 is a circuit diagram of a semiconductor laser drive circuit according to a twelfth embodiment of the present invention.

FIG. 24 is a circuit diagram of a semiconductor laser drive circuit according to a modification of the seventh embodiment of the present invention.

FIG. 25 is a circuit diagram of a semiconductor laser drive circuit according to a modification of the seventh embodiment of the present invention.

FIG. 26 is a circuit diagram of a conventional drive circuit.

[Explanation of symbols]

 J1, J2, J3, J4, J5, J6 ... FETs R1, R2, R3, R4, R5 ... Resistors L1, ... Inductors C1, C2, C3 ... Capacitors LD ... Semiconductor laser Z ... DC load

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04B 10/26 10/14 10/04 10/06

Claims (5)

[Claims] 1. A voltage-current conversion circuit for converting a voltage signal into a current signal, a DC load that operates according to an output current signal of the voltage-current conversion circuit, and a bias current supply circuit that supplies a bias current to the DC load. The bias current supply circuit includes a transistor having one electrode of a collector electrode or an emitter electrode connected to the DC load, and the other electrode of the collector electrode or the emitter electrode of the transistor is A drive circuit, which is connected to a DC power source, and an inductor is connected to a base electrode of the transistor. 2. A voltage-current conversion circuit composed of a differential amplifier composed of field-effect transistors, a DC load which operates according to an output current signal of the voltage-current conversion circuit, and a bias which supplies a bias current to the DC load. In the drive circuit including a current supply circuit, the voltage-current conversion circuit includes a first field effect transistor in which one of a drain electrode and a source electrode is connected to the DC load, and one of a drain electrode and a source electrode. The electrode is the first
A second field effect transistor connected to the other electrode of the drain electrode or the source electrode of the field effect transistor of, and the threshold value of the first field effect transistor is the second field effect transistor.
Drive circuit characterized by being smaller than the threshold value of the field effect transistor of. 3. A voltage-current conversion circuit comprising a differential amplifier composed of field-effect transistors, a DC load which operates in response to an output current signal of the voltage-current conversion circuit, and a bias which supplies a bias current to the DC load. In the drive circuit including a current supply circuit, the voltage-current conversion circuit includes a first field effect transistor in which one of a drain electrode and a source electrode is connected to the DC load, and one of a drain electrode and a source electrode. The electrode is the first
A second field effect transistor connected to the other electrode of the drain electrode or the source electrode of the field effect transistor of, and the gate width of the first field effect transistor is the second field effect transistor.
A drive circuit characterized by being smaller than the gate width of the field effect transistor of. 4. A voltage-current conversion circuit composed of a differential amplifier composed of field-effect transistors, a DC load which operates according to an output current signal of the voltage-current conversion circuit, and a bias which supplies a bias current to the DC load. In the drive circuit including a current supply circuit, the bias current supply circuit includes a transistor in which one of a collector electrode and an emitter electrode is connected to the DC load, and the voltage-current conversion circuit includes a drain electrode or A first field effect transistor in which one of the source electrodes is connected to the DC load, and one of the drain electrode or the source electrode is the first field effect transistor
A second field effect transistor connected to the other electrode of the drain electrode or the source electrode of the field effect transistor, and the inductor is connected to the other electrode of the drain electrode or the source electrode of the second field effect transistor. The base electrode of the transistor forming the bias current supply circuit is connected to the other electrode of the drain electrode or the source electrode of the second field effect transistor via a capacitor and forms the bias current circuit. A drive circuit characterized in that a voltage is applied to the base electrode of the transistor through a resistor. 5. A voltage-current conversion circuit composed of a differential amplifier composed of field-effect transistors, a DC load which operates according to an output current signal of the voltage-current conversion circuit, and a bias which supplies a bias current to the DC load. In the drive circuit including a current supply circuit, the voltage-current conversion circuit includes a first field effect transistor in which one of a drain electrode and a source electrode is connected to the DC load, and one of a drain electrode and a source electrode. The electrode is the first
A second field effect transistor connected to the other electrode of the drain electrode or the source electrode of the field effect transistor of, and one electrode of the drain electrode or the source electrode is the first electrode.
A third field effect transistor connected to the other electrode of the drain electrode or the source electrode of the field effect transistor and the one electrode of the drain electrode or the source electrode of the second field effect transistor, The other electrode of the drain electrode or the source electrode of the field effect transistor is connected to an inductor, and the gate electrode of the third field effect transistor is connected to the drain electrode or the source electrode of the second field effect transistor via a capacitor. A drive circuit connected to the other electrode, and a voltage is applied to the gate electrode of the third field effect transistor through a resistor.