JPH07298053A - Image processing unit - Google Patents

Abstract

PURPOSE:To provide an image processing unit in which the increase of the hardware is suppressed and a binary image jointing smoothly borders of plural divided images is generated with a small memory capacity. CONSTITUTION:The image processing unit is made up of a CCD 3 reading divided images of an object 1 reflected from a rotational mirror 2, a frame memory 5 storing divided image data by one frame from the CCD 3 via an A/D converter 4, a binarization processing section 6 converting multi-value divided image data from the frame memory 5 into binary divided image data by adopting the error spread method or the dither method, and a memory control section 7 reading repetitively n-sets of head image data in the binarizing processing direction of the divided images to generate interpolation image data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus which divides and reads one subject image and binarizes it.

[0002]

2. Description of the Related Art Conventionally, as a binarizing method for expressing a halftone in a digital printer, a digital copying machine, etc., in 1976, by Floid and Steinberg,
“An Adaptive Algorithm for Spatial Grayscale”
(Proceeding of the SID Vol. 17/2 Second
There is an error diffusion method proposed in a paper called Quater 1976). This binarization method is characterized in that the error generated in the binarization process is dispersed to surrounding pixels and the image density is preserved. When this method is applied to an image processing apparatus that performs processing by dividing an image area into (A), (B), ... As shown in FIG. 16, “streaks” appear at the boundaries of each divided area. Streaks occur. This is a phenomenon that occurs when the error diffusion method is applied to the divided area (B) in FIG. 16 because there is no error at the edge of the image and the error amount is set to “0” at the edge portion to perform the calculation. .

As a means for solving the problem, as shown in FIG. 17, when a divided area (A) is processed, a part of the divided area (B) is read by overlapping, and the divided area (B) is read from the divided area (A). ), The error read out from the memory storing the error diffused in) is used to process the divided area (B), and the error diffused from the divided area (B) to the divided area (C) is again detected. Hold in memory and divide area (C)
There is a method of using it again when processing.

Further, as an improvement measure of this method, Japanese Patent Laid-Open No. Hei-2
-62165 does not use the memory to store the error, but uses the binary data of the previous screen to perform the processing, thereby reducing the memory capacity and creating a "streak" pattern at the boundary. A method of eliminating the line is proposed.

[0005]

However, as shown in FIG.
In the binarization processing method shown in, in order to hold the error diffused from the divided area (A) to the divided area (B), an 8-bit line is set according to the error diffusion range (normally 1 to 3 lines). There is a drawback that the memory is required and the hardware is increased. Further, the image processing method proposed in Japanese Patent Laid-Open No. 2-62165 does not use an 8-bit line memory for storing an error, but must store a binary image of the previous screen. However, there was a drawback that the hardware increased.

The present invention has been made to solve the above problems in the conventional binarized image processing method.
An object of the present invention is to provide a high-definition image processing device capable of smoothly combining the boundary portions between the regions of a plurality of error diffusion-processed divided images with a small memory capacity while suppressing an increase in hardware. . Next, the objects of the invention described in each claim are listed as follows. An object of the present invention is to provide an image processing apparatus capable of suppressing the increase in hardware, and using a small memory capacity to smoothly combine the boundary portions between the regions of a plurality of error diffusion processed divided images. Is to provide. An object of the invention described in claim 2 is to realize the object of the invention described in claim 1 with a simpler circuit configuration for the means for generating the interpolated image, without adding a special memory capacity. Claim 3
An object of the described invention is to simplify the hardware configuration by reading the image of the same line n times in succession and using the image as an interpolation image. The object of the invention described in claim 4 is as follows. That is, as an image binarization method, as described above, there is an error diffusion method which is said to be excellent in halftone expression. When the pixel of interest is binarized by this method, the information of surrounding pixels is considerably affected. On the other hand, if there is information about surrounding pixels, a better halftone expression can be achieved. Therefore, an object of the present invention is to eliminate streaks occurring at the boundary in the binarized representation of a divided image using the error diffusion method and to obtain a good pseudo-halftone image. The object of the invention described in claim 5 is to apply a dither method in the binarized representation of the divided image to eliminate streaks occurring at the boundary portion and to provide a good pseudo-halftone image with a simple circuit, as in the case of claim 4. It is to be configured in the configuration. An object of the invention described in claim 6 is to realize the invention described in claim 1 by sharing the split screen capture and storage means and with a small memory capacity.

[0007]

In order to solve the above problems, the invention according to claim 1 divides a subject into a plurality of regions, and obtains image information of each divided region from a sensor and pastes the image information. In an image processing apparatus that acquires one original image by combining and obtains a binarized image from this original image, a unit that divides an image of a subject into a plurality of units, a unit that captures and stores the divided image, and a divided image And a means for binarizing each divided image including the interpolated image, and binarizing each divided image unit including the interpolated image for binarization. It is configured to obtain an image.

In the image processing apparatus thus configured, one divided image of the subject is loaded into the storage means, an interpolated image is generated using only the image data of the divided image, and two divided images including the interpolated image are generated. The image is binarized and the effective area of the image is extracted, and then the next divided image is updated and stored in the storage means. This eliminates the need for a memory that stores the image data of all images, suppresses an increase in hardware scale, and uses a small memory capacity to smoothly combine the boundary portions between divided images with high-definition binary images. Is obtained.

According to a second aspect of the present invention, the means for dividing the image of the subject into a plurality of images is configured such that the direction of dividing the image is perpendicular to the binarization processing direction. This simplifies the means for generating the interpolated image.

According to a third aspect of the present invention, the means for forming the interpolated image is configured to form the interpolated image by repeating n pieces of the first image data in the binarization processing direction of the divided image. is there. As a result, it is possible to easily generate the interpolated image without controlling the image data itself and controlling the method of reading the image data from the memory.

According to a fourth aspect of the invention, the binarizing means is constituted by the binarizing means by the error diffusion method, and the fifth aspect of the invention is that the binarizing means is the binarizing means by the dither method. It is what constitutes. This makes it possible to obtain a pseudo intermediate image in which the boundary portions between the divided images are smoothly pasted together.

According to a sixth aspect of the present invention, the means for fetching and storing the divided images is configured to be shared by the divided images. As a result, each divided image is input in a time-divisional manner, the image data is stored in the same memory by overwriting, and therefore the memory capacity can be reduced.

[0013]

【Example】

[First Embodiment] Next, an embodiment will be described. Figure 1
FIG. 1 is a block configuration diagram showing a first embodiment of an image processing apparatus according to the present invention. In FIG. 1, 1 is a subject, and 2 is a rotatable mirror for reflecting an image of the subject on the CCD 3. 3 is a CCD for reading the image of the subject 1 reflected from the mirror 2, 4 is an A / D converter for converting a video analog signal from the CCD 3 into a digital signal, and 5 is a divided image for one frame from the CCD 3. A frame memory for storing data, 6 is a binarization processing unit for converting multivalued divided image data from the frame memory 5 into binary divided image data, and 7 is a frame memory 5 or 2
It is a memory control unit for controlling a line memory that stores an error amount in the digitization processing unit 6.

Next, the operation of the first embodiment thus constructed will be described with reference to FIGS. 2 and 3. Mirror 2
2, the image 10 of the subject 1 is divided and read as divided images A, B, ... O. More specifically, when the mirror 2 is in the state A in FIG. 1, the divided image of the portion A shown in FIG. 2 is reflected by the CCD 3, and when the divided image A is taken, the mirror 2 rotates, and The divided image B is reflected by the CCD 2, and the divided images C,
D ... is reflected.

Now, assuming that the mirror 2 scans and the divided image A is reflected by the CCD 3, the CCD 3 converts this divided image A into an electric signal, and the A / D converter 4 further converts it into a digital image signal. , Are stored in the frame memory 5. Once the divided image signal is stored in the frame memory 5, the mirror 2 moves to rotate so as to project the next divided image on the CCD 3. The image data stored in the frame memory 5 is sent to the binarization processing unit 6 by a special read scan described later, and error diffusion processing is performed based on the image data of the divided image A, and is output as a binary image. .
The above is a series of operations for processing the divided image A and obtaining a binary image. By repeating this process several times, one subject image 10 as shown in FIG. 2 can be converted into a binary image. In this embodiment, the first divided image, the second divided image, ..., The kth divided image, ... Not stored,
As shown in FIG. 3, the frame memory 5 is used as a common memory, and the contents of the entire screen are updated and used. By sharing the memory in this way, the memory capacity can be reduced (see claim 6).

Next, the memory control section 7 of the first embodiment shown in FIG. 1 will be described in detail. It is assumed that the frame memory 5 of FIG. 1 stores a divided image 11 as shown in FIG. Now, the scanning direction of the divided images is the H direction, and the divided images A, B, C, and
A case will be described in which D and E are scanned and bonded at each boundary. That is, in this aspect, as described in claim 2, the means for dividing the original image of each region into a plurality of images is a unit of one sensor line perpendicular to the binarization processing direction. In FIG. 4B, 1
The image 2 is the same as the image on the leftmost column of the divided images 11, and is arranged in n columns. The memory control unit 7 controls the generation of the image 13 shown in FIG. 4B from the divided image 11 shown in FIG. 4A and performs simple image interpolation processing. reference).

FIG. 5 shows an example of a simple circuit configuration for controlling the image interpolation processing, and FIG. 6 shows a timing chart for explaining the operation. In FIG. 5, 15 is HB
A shift register that delays LK (horizontal synchronization signal) by m clocks, 16 is an AND gate, and 17 is an up counter that is reset by HBLK and counts the number of CKs (clocks).

Next, the operation of the control circuit shown in FIG. 5 will be described with reference to FIG. However, the direction of the binarization processing described here is the H (horizontal) direction. Now, it is assumed that HBLK (horizontal synchronization signal) is input for each row in the divided image 11 shown in FIG. It is assumed that the "H" period of this HBLK is the effective period of the image, and the frame memory 5 stores only the image of this "H" period. Here, the frame memory 5 is an SRAM, and the corresponding image data can be read by giving an address. The shift register 15 shown in FIG.
And AND gate 16 causes HBLK to fall, m
When the signal rising after the clock is EN, the "H" period of EN is the valid period of the image read from the frame memory 5 ((B) of FIG. 4), so it is used as the read enable signal of the frame memory 5. There is. On the other hand, from the rising edge of EN to the rising edge of HBLK, since HBLK is "L", the counter 17 is in the reset state and the output of the counter 17 is in the constant state ("0"). Therefore, in this period, the image in the 0th column is continuously read out in n columns (n times).

When HBLK rises from "L" to "H", the counter 17 counts up from the next clock, and this signal becomes the address (column address) of the frame memory 5. By performing this process for one frame, the image 13 as shown in FIG. 4B can be retrieved from the frame memory 5. In this configuration example, the reset terminal of the counter 17 is controlled to read n columns repeatedly, but the load value and load terminal of the counter may be controlled.

Next, the case where the divided images A, F and K shown in FIG. 2 are pasted together will be described. In this case, the bonding direction is as shown in FIG. As the interpolation image in this case, as in the method described above, the interpolation image is generated by repeating n lines of the image of the first line of the k-th divided image (the image of one line in the H direction). That is, also in this case, the scanning direction of the divided image and the direction of the interpolation image are vertical. (See claim 2)

In this case, when generating the interpolated image,
The control circuit as shown in FIG. 5 is not necessary, and in order to repeat the image of the first line (the image of one line in the H direction) for n lines, it is sufficient to read the image for that line n times continuously. Therefore, the divided images A, B, C in FIG.
The processing circuit becomes simple as compared with the case where an interpolated image is generated in order to combine the D and E images. As described above, when it is desired to process the k-th divided image, the interpolation process does not use the (k−1) -th divided image, but generates the interpolated image using only the k-th image. The biggest advantage is that there is no need to use.

The image data read out by performing the interpolation process as described above is transferred to the next binarization processing unit 6. In this embodiment, an example of binarization by the error diffusion method described in claim 4 is shown. For example, 2 as shown in FIG.
Considering a line matrix, if P is the pixel data of interest read from the frame memory 5, then G1, G
2, G3 and GP1 represent the error amount when binarizing at that position, and FIG. 8B shows the weighting coefficient for the error amount. Here, α is represented by the following equation. α = K1 + K2 + K3 + K4

FIG. 9 shows an error diffusion processing circuit in this case. In FIG. 9, 21-1 to 21-8 are single-stage registers, 22-1 to 22-4 are multipliers for integrating the weighting coefficient and the error amount, 23-1 to 23-4 are adders, Two
4 is a comparator for outputting "H" when the d signal is smaller than the threshold level (Thresh), 25 is a subtractor, 26 is an output of the subtractor 25 when the S terminal is "L", and "H" ”
At the time of, a selector for selecting the d signal, and 27 is a line memory for storing an error for one line.

Next, the operation of the error diffusion processing circuit having the above configuration will be described with reference to the timing chart of FIG.
When considering binarizing the pixel data of the pixel of interest P, the error amounts G1 to G3 of the periphery (one line before) are G1 at time t0, G2 at time t1, and time t1, as shown in FIG.
If G3 is input as error data in step 2, the a signal is a signal that is output through the register 21-2 after the error amount G1 and the coefficient K1 / α are integrated in the multiplier 22-1, and b The multiplier 22-2 multiplies the signal by the error amount G2 and the coefficient K2.
/ Α is integrated, the a signal is added to the integrated signal by the adder 23-1, and is output through the register 21-3. Similarly, the c signal is output by the multiplier 22-3. The error amount G3 and the coefficient K3 / α are integrated, the b signal is added to the integrated signal by the adder 23-2, and the register 21-4 is added.
Is a signal output via. The c signal at this time represents the sum total of the calculation of the error amount of the periphery (one line before).
(Time t4)

At the next time t5, the pixel data d is corrected by the error in the periphery of the pixel of interest P. The corrected pixel data d is binarized, and the corrected pixel data d corresponds to the binarized threshold level (Thresh) preset in the comparator 24. When compared, the output is determined to be "L" when it is higher than the threshold level, and white ("L") is output as the binary output D1 at time t6. Similarly, when the pixel data d is smaller than the threshold level, black (“H”) is output as the binary output D2 at time t7.

When the comparator 24 makes a judgment of white ("L"), the selector 26 selects the output of the subtractor 25. In the subtractor 25, the pixel data d
And White (the maximum white level) are subtracted, and the error from White is sent from the selector 26 as the error amount in the pixel of interest P. When the comparator 24 determines that the pixel is black (“H”), the selector 26 selects the pixel data d, and the error from the maximum black level (“0”), that is, the pixel data d It is sent as an error amount at P. This error amount is fed back as an error amount GP1 on the left side when processing the next pixel, and is stored in the line memory 27 to be used as an error of the next line.

By performing the above processing, the entire image 13 shown in FIG. 4B can be binarized. After this, a binary image corresponding to the divided image 11 excluding the interpolated image 12 shown in FIG. 4B may be extracted. The above is a series of operations for processing one divided image. By repeating these processes as shown in the timing chart of FIG.
The image 10 can be binarized. FIG. 11A is an example of an image when two lines of divided images (a left side screen and a right side screen) are pasted together by a conventional method and a “streak” X appears, and FIG. FIG. 9 is a diagram showing an image in which “streaks” are not generated, which is obtained by applying interpolation of about 30 columns according to the present embodiment.

In this embodiment, an example in which only the image of the end line is used is shown, but not limited to only the end line, any data may be used as long as it is data in the divided image of interest. Absent. Further, in the present embodiment, the data in the focused divided image is used as it is, but the average value calculation may be performed on the pixels around the edge, or the predicted pixel may be generated and interpolated using the image around the edge.

[Second Embodiment] In the first embodiment, an error diffusion method is applied as the binarizing means. However, the dither method may be applied in consideration of reducing the circuit scale. Next, the second method using the dither method as the binarization means
Examples will be described. In FIG. 12, 31 is a divided image and 32 is a dither matrix. FIG. 13 is a diagram showing a dither matrix, and the number in the cell divided into 16 equal parts is the binarization threshold level of the image. FIG. 14 is a basic circuit diagram of binarization by the dither method. When image data A> dither matrix threshold level B, “L”
(White), when the image data A <dither matrix threshold level B, the comparator 4 outputs “H” (black).
1 is configured. In this embodiment, the image data is represented by an 8-bit digital signal.

In FIG. 12, when the divided images 31 are sequentially scanned and input, the binarization of the pixel of interest is compared with the threshold level of the corresponding dither matrix 32 to determine the binarization level. . For example, when the number of the dither matrix corresponding to the pixel of interest is 9, 8-bit pixel data is compared with 9 × (256/16) = 144, and black / white is determined depending on whether it is large or small. When the binarization process is performed in this way, a binary image as shown in FIG. 15 is obtained.

The problem here is the interpolated image at the boundary portion, but this may be performed by performing n lines of interpolation as in the first embodiment. The hardware for realizing the binarization processing in this embodiment is configured only by a comparator as shown in FIG. 14, and binarization is performed by comparing the pixel data of interest and the threshold level by the dither matrix. This is an effective method for reducing the circuit scale because it can be performed.

[0032]

As described above on the basis of the embodiments,
According to the invention of claim 1 of the present application, it is possible to obtain a high-definition binary image by suppressing the increase in the scale of the hardware and smoothly bonding the boundary portions between the regions of the divided images with a small memory capacity. You can According to the second aspect of the present invention, an interpolated image can be easily formed without providing any special interpolated pixel calculation means, and a high-definition binary image in which boundary portions between divided images are smoothly pasted together can be obtained. Obtainable.
According to the third aspect of the present invention, since the binarizing means using the error diffusion method is provided, it is possible to obtain a high-definition binary image in which the boundary portions between the divided images are smoothly pasted together.
According to the fifth aspect of the invention, since the binarizing means using the dither method is provided, the boundary portion between the divided images can be smoothly pasted with a simple circuit configuration. According to the invention described in claim 6, the boundary portion between the divided images can be smoothly pasted together with a small memory capacity.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a first embodiment of an image processing apparatus according to the present invention.

FIG. 2 is a diagram showing an example of divided images processed according to the first embodiment shown in FIG.

FIG. 3 is a timing chart for explaining the operation of the first embodiment shown in FIG.

FIG. 4 is a diagram for explaining an interpolated image formed in the first embodiment shown in FIG.

FIG. 5 is a diagram showing a configuration example of an image interpolation processing control circuit for forming an interpolation image.

6 is a timing chart for explaining the operation of the image interpolation processing control circuit shown in FIG.

FIG. 7 is a diagram for explaining the pasting of images divided in the vertical direction.

FIG. 8 is an explanatory diagram of a matrix of error diffusion processing.

FIG. 9 is a diagram illustrating a configuration example of an error diffusion processing circuit.

10 is a timing chart for explaining the operation of the error diffusion processing circuit shown in FIG.

11A and 11B are diagrams showing an image processed by the embodiment shown in FIG. 1 and an image processed by a conventional processing method.

FIG. 12 is a diagram for explaining the second embodiment.

FIG. 13 is a diagram for explaining a dither matrix used in the second embodiment.

FIG. 14 is a diagram illustrating a binarizing circuit according to a second embodiment.

FIG. 15 is a diagram showing a binary image sequence obtained according to the second embodiment.

FIG. 16 is an explanatory diagram illustrating a configuration example of conventional divided image processing.

FIG. 17 is an explanatory diagram showing another configuration example of conventional divided image processing.

[Explanation of symbols]

 1 subject 2 mirror 3 CCD 4 A / D converter 5 frame memory 6 binarization processing unit 7 memory control unit 10 subject image 11 divided image 12 interpolation image 13 divided image with interpolation image 15 shift register 16 AND gate 17 up counter 21-1 to 21-8 One-stage register 22-1 to 22-4 Multiplier 23-1 to 23-4 Adder 24 Comparator 25 Subtractor 26 Selector 27 Line memory 31 Divided image 32 Dither matrix 41 Comparator

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H04N 1/387 G06F 15/68 320 A

Claims (6)

[Claims] 1. An image in which a subject is divided into a plurality of regions, image information of each divided region is obtained from a sensor, and one original image is obtained by pasting, and a binary image is obtained from this original image. In the processing device, means for dividing an image of a subject into a plurality of portions, means for loading and storing the divided images, means for generating an interpolated image based on image data of the divided images, and each divided image including the interpolated image And an image processing apparatus configured to obtain a binary image by binarizing each divided image unit including an interpolated image. 2. The means for dividing the image of the subject into a plurality of images is configured such that the direction of dividing the image is perpendicular to the binarization processing direction. The image processing device described. 3. The interpolation image forming means is configured to form an interpolation image by repeating n pieces of the first image data in the binarization processing direction of the divided image. The image processing device according to item 1 or 2. 4. The binarizing means uses the error diffusion method
The image processing device according to claim 1, wherein the image processing device is a value conversion unit. 5. The image processing apparatus according to claim 1, wherein the binarizing unit is a dithering binarizing unit. 6. The image processing according to claim 1, wherein the means for fetching and storing the divided images is configured to be shared by the divided images. apparatus.