JPH07297290A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor integrated circuit device in which a dummy transistor is formed by effectively utilizing an empty space in a cell and a circuit can be changed only by changing a pattern of a power supply wiring. [Structure] In the cells 1A and 1B, P is provided below the power supply wiring 10.
A dummy transistor 13 formed of a MOS transistor is formed, and a dummy transistor 14 formed of an NMOS transistor is formed below the power supply wiring 11. The pattern of the wiring 11 is changed so that the gate electrode 20 of the transistor 14 of the cell 1A is exposed, and the wiring 1 is exposed so that the gate electrode 17 of the transistor 13 of the cell 1B is exposed.
The 0 pattern has been changed. Both N-type regions of the transistor 14 are connected to the wiring 11, and both P-type regions of the transistor 13 are connected to the wiring 10. The contact 21a of the signal line 21 and the electrodes 20 and 17 are connected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device (LSI), and more particularly to an LSI having a large number of cells each formed of a CMOS transistor.

In recent years, LSIs have become large-scale and highly integrated. On the other hand, it is required to shorten the delivery time of LSI and reduce the cost. Therefore, it is necessary to change a highly integrated circuit at a minimum cost and in a short delivery time even when timing adjustment is necessary or when the circuit is changed when there is a defect in the circuit.

[0003]

2. Description of the Related Art FIG. 5 shows a conventional standard cell LSI.
The cell 41 in FIG. This cell 41 is CM
It has an OS configuration and three Ps are formed at a predetermined interval.
The semiconductor regions 42, 43, and 44 are provided with three N-type semiconductor regions 45, 46, and 47 that are formed at predetermined intervals. Each P-type semiconductor region and each N-type semiconductor region are arranged to face each other. P-type regions 4 adjacent to each other
Gate electrodes 48 and 49 are formed above the gaps 2, 43 and 44. P-type regions 42 and 43 and gate electrode 48
Form a PMOS transistor T5, and the P-type regions 43 and 44 and the gate electrode 49 form a PMOS transistor T6. Therefore, the P-type regions 42, 4
4 serves as the sources of the transistors T5 and T6, and the P-type region 43 serves as the drains of the transistors T5 and T6. The gate electrodes 48 and 49 extend above the N-type regions 45, 46 and 47 adjacent to each other. The N-type regions 45 and 46 and the gate electrode 48 form an NMOS transistor T7, and the N-type regions 46 and 47 and the gate electrode 49 form an NMOS transistor T8. Therefore, the N-type region 45 becomes the source of the transistor T7, and the N-type region 46 becomes the drain of the transistor T7. The N-type region 46 becomes the source of the transistor T8, and the N-type region 47 becomes the drain of the transistor T8.

Contact formation regions 42a, 44a, 45a are formed at the outer ends of both P-type regions 42, 44 and N-type region 45.
Are formed so as to be separated from each other. A power supply line 50 is provided above the contact formation regions 42a and 44a and extends in the arrangement direction of the transistors T5 and T6 along the outer ends of the PMOS transistors T5 and T6. Above the contact formation region 45a, a power supply wiring 51 is provided extending along the outer ends of the NMOS transistors T7 and T8 in the arrangement direction of the transistors T7 and T8. High potential and low potential power supplies VDD and VSS are applied to the wirings 50 and 51.

In the cell 41 described above, a formation region 42 is formed.
a and 44a are wiring 5 by contacts 42b and 44b.
0, and the power source VDD is applied to the P-type regions 42 and 44. The formation region 45a is connected to the wiring 51 by the contact 45b, and the power supply VSS is applied to the N-type region 45.

The gate electrodes 48, 49 have input terminals A1,
A2 is provided. P-type region 43 and N-type region 47
Are connected by a signal wire 52, and the wire 52 is provided with an output terminal X. As described above, the cell 41 is provided with the input terminals A1 and A2 and one output terminal X.
An input NAND circuit is formed.

[0007]

However, in the above-mentioned conventional cell 41, there is an empty space below the power supply wirings 50 and 51, which is not effectively used. Although this empty space is small when considered as one, the area of the semiconductor chip increases because there are as many cells as there are on the semiconductor chip.

Further, since it is necessary to adjust the timing of the designed circuit or to change all the wiring layers when the circuit is changed when a circuit failure occurs, a large amount of cost and time are spent.

When a dummy cell similar to the cell 41 is provided on the semiconductor chip, the area of the dummy cell increases. Further, since such a dummy cell is provided at a position irrelevant to a predetermined circuit, when using the dummy cell, the wiring length becomes long and the wiring must be changed significantly. Furthermore, the function that can be generated by using dummy cells is also determined, and there are some dummy cells that are not used, resulting in wasted space.

The present invention has been made to solve the above problems, and its purpose is to form dummy transistors by effectively utilizing the empty space in the cell, and only change the wiring pattern when changing the circuit. It is to provide a semiconductor integrated circuit device that can handle the above.

[0011]

According to the invention of claim 1, P
The MOS transistor and the NMOS transistor are arranged so as to face each other, and contact formation regions for forming a contact with the power supply wiring are separated from each other at the outer ends of both the MOS transistors in the arrangement direction of both the MOS transistors. Form to form cells. A pair of power supply wirings extending above the contact formation regions of both MOS transistors along the outer ends of both MOS transistors are formed. Dummy transistors are formed in the cell below the pair of power supply lines.

According to the second aspect of the present invention, the power supply wiring is patterned so that a part of the dummy transistor is exposed. In the invention of claim 3, the power supply wiring is patterned so that at least the gate contact portion of the dummy transistor is exposed, and the source and drain regions of the dummy transistor are connected to the power supply wiring above the dummy transistor, The gate electrode is connected to the signal line.

According to another aspect of the present invention, the power supply wiring is patterned so that, in two different cells, one of the gate contact portion and the source or drain region of the dummy transistor provided in each cell is exposed.
Each gate electrode is connected to a common first signal line, one region is connected to a common second signal line, and the other region is connected to a power supply wiring above each region.

In the invention of claim 5, the cell is a pair of PMOs.
It is composed of an S transistor and a pair of NMOS transistors. The pair of PMOS transistors includes three P-type semiconductor regions formed at a predetermined interval and a pair of gate electrodes formed above the P-type semiconductor regions. The pair of NMOS transistors are composed of three N-type semiconductor regions formed at a predetermined interval and a pair of gate electrodes formed above the N-type semiconductor regions.

[0015]

Therefore, according to the first aspect of the present invention, the empty space in the cell is effectively used, and despite the provision of the dummy transistor, the increase in the area of the semiconductor chip can be suppressed and the cost can be reduced. Becomes

According to the second aspect of the present invention, when the timing adjustment is necessary or when the circuit is changed, the dummy transistor can be used only by changing the power supply wiring. Further, the function is determined by the combination of the dummy transistors when the wiring is changed.

According to the third aspect of the invention, since the gate electrode of the dummy transistor is connected to the signal line, the propagation time of the signal propagating through the signal line is delayed and the timing is adjusted.

According to the fourth aspect of the invention, one of the dummy transistors operates based on the voltage level of the signal on the first signal line, and the voltage of the power supply wiring connected to the dummy transistor is the second voltage. Is output via the signal line.

According to the invention of claim 5, a pair of PMOSs is provided.
The transistor is composed of three P-type regions, and one P-type region is common to both transistors. A pair of N
The MOS transistor is composed of three N-type regions, and one N-type region is a region common to both transistors. Therefore, the area occupied by the cells is reduced and the degree of integration is improved.

[0020]

【Example】

[First Embodiment] A first embodiment in which the present invention is embodied in a standard cell will be described below with reference to FIG.

FIG. 1 shows two cells 1A and 1B of this embodiment.
Two 2-input NAND circuits configured using are shown. The cells 1A and 1B have the same configuration, and the CMO
It is composed of S transistors. The cells 1A and 1B have three P-type semiconductor regions 2, which are formed at a predetermined interval.
3 and 4 and three N-type semiconductor regions 5, 6 and 7 formed at a predetermined interval. Each P-type region 2, 3,
4 and the N-type regions 5, 6 and 7 are arranged to face each other.

Gate electrodes 8 and 9 are formed above the P-type regions 2, 3 and 4 adjacent to each other. The PMOS transistor T is formed by the P-type regions 2 and 3 and the gate electrode 8.
1 is formed, and the P-type regions 3 and 4 and the gate electrode 9 form a PMOS transistor T2. Therefore,
The P-type regions 2 and 4 become sources of the transistors T1 and T2, and the P-type region 3 becomes drains of the transistors T1 and T2.

Further, N-type regions 5, 6, 7 which are adjacent to each other
The gate electrodes 8 and 9 extend above the space. The N-type regions 5, 6 and the gate electrode 8 form an NMOS transistor T3, and the N-type regions 6, 7 and the gate electrode 9 form an NMOS transistor T4. Therefore, the N-type region 5 becomes the source of the transistor T3,
The mold region 6 becomes the drain of the transistor T3. The N-type region 6 becomes the source of the transistor T4, and the N-type region 7 becomes the drain of the transistor T4. The pair of PMOS transistors T1 and T2 have the P-type region 3 and the both transistors T
It is set as a common area of 1 and T2. The pair of NMOS transistors T3 and T4 have the N-type region 6 and the both transistors T
The area is common to T3 and T4. Therefore, cell 1A,
The area occupied by 1B can be reduced, and the degree of integration of semiconductor chips can be improved.

Contact forming regions 2a, 4a, 5a are formed in the outer end portions of both P-type regions 2, 4 and N-type region 5 in a direction away from each other. Contact formation region 2a,
A power supply wiring 10 extending in the arrangement direction of the transistors T1 and T2 is provided along the outer ends of the transistors T1 and T2 above 4a. Above the contact formation region 5a, a power supply wiring 11 extending in the arrangement direction of the transistors T3 and T4 is provided along the outer ends of the transistors T3 and T4. High potential and low potential power supplies VDD and VSS are applied to the wirings 10 and 11.

In the cells 1A and 1B, a dummy transistor 13 formed of a PMOS transistor is formed below the wiring 10 and a dummy transistor 14 formed of an NMOS transistor is formed below the wiring 11. The transistor 13 has two P-type semiconductor regions,
The gate electrode 17 is formed between the two P-type regions. The transistor 14 is composed of two N-type semiconductor regions and a gate electrode 20 formed above both N-type regions.

In the above cells 1A and 1B, the formation regions 2a and 4a are connected to the wiring 10 by the contacts 2b and 4b, and the power source VDD is applied to the P-type regions 2 and 4.
The formation region 5a is connected to the wiring 11 by the contact 5b, and the power supply VSS is applied to the N-type region 5.

The gate electrodes 8 and 9 have input terminals A1 and A2, respectively.
Is provided. The P-type region 3 and the N-type region 7 are connected by a signal wiring 12, and the wiring 12 is provided with an output terminal X. As described above, the cells 1A and 1B form the two-input NAND circuit having the input terminals A1 and A2 and the one output terminal X.

A signal line 21 from another circuit is wired between the two 2-input NAND circuits. In FIG. 1, the timing adjustment of the signal propagating through the signal line 21 and the circuit change are unnecessary. Therefore, the dummy transistors 13 and 1
4 is not used, the transistors 13 and 14 are the power supply wiring 1
It is covered with 0 and 11.

The transistors 13 and 14 can be used by patterning the portions of the power supply wirings 10 and 11 corresponding to these transistors 13 and 14 to expose the transistors 13 and 14.

As described above, in this embodiment, the power supply wiring 1
In the empty space in cells 1A and 1B below 0 and 11,
Dummy transistors 13 and 14 are formed. Therefore, the empty space in the cells 1A and 1B can be effectively used, and although the dummy transistor is provided,
It is possible to suppress an increase in the area of the semiconductor chip and thus reduce costs.

[Second Embodiment] Next, a second embodiment will be described with reference to FIG. Note that, for convenience of explanation, the same configurations as those in FIG.

As shown in FIG. 2, even in this embodiment, 2
Two 2-input NAND circuits are configured by using one cell 1A, 1B. In the present embodiment, the power supply wiring 11 is patterned so that at least the gate contact portion of the gate electrode 20 of the dummy transistor 14 is exposed on the cell 1A side. On the cell 1B side, the power supply wiring 10 is patterned so that at least the gate contact portion of the gate electrode 17 of the dummy transistor 13 is exposed. Both N-type regions of the transistor 14 are connected to the wiring 11, and both P-type regions of the transistor 13 are connected to the wiring 10.

A contact 21a is provided in the middle of the signal line 21.
Is formed, and this contact 21a and both gate electrodes 2 are formed.
0 and 17 are respectively connected by signal wiring.
As described above, this embodiment has the same effect as that of the above embodiment. Since the load capacitances of the gate electrodes 17 and 20 of both transistors 13 and 14 are connected to the signal line 21, the propagation time of the signal propagating from the terminal SA of the signal line 21 to the terminal SX is delayed to adjust the timing. be able to.

Further, when this circuit is changed, the required functions can be realized by using dummy transistors in a plurality of cells adjacent to each other and wiring them. Therefore, it is not necessary to significantly change the signal wiring at the time of such a circuit change, the wiring length for realizing the function can be shortened, and the cost and required time can be reduced.

Further, this embodiment has the same effect as that of the above embodiment. [Third Embodiment] Next, a third embodiment will be described with reference to FIG. Note that, for convenience of explanation, the same configurations as those in FIG.

As shown in FIG. 3, even in this embodiment, 2
Two 2-input NAND circuits are configured by using one cell 1A, 1B. In the present embodiment, on the cell 1A side, one N-type region (source region) of the dummy transistor 14 and the gate electrode 20 are exposed.
The power supply wiring 11 is patterned. The other N-type region (drain region) of the transistor 14 is connected to the wiring 11. Further, on the cell 1B side, the power supply wiring 10 is patterned so that one P-type region (drain region) of the dummy transistor 13 and the gate electrode 17 are exposed. The other P-type region (source region) of the transistor 13 is connected to the wiring 10.

Two 2-input NAND circuits (cells 1A, 1
Between B), a signal line 22 as a first signal line having a terminal SA and a signal line 23 as a second signal line having a terminal SX are wired. A contact 22a is formed at the inner end of the signal line 22, and the contact 22a and both gate electrodes 20 and 17 are connected by signal wiring. A contact 23 a is formed at the inner end of the signal line 23, and the contact 23 a is exposed to the exposed P-type region of the transistor 13 and the exposed N-type region of the transistor 14.
and a are respectively connected by signal wiring. Therefore, the dummy transistors 13 and 14 form a CMOS inverter, and the input signal of the terminal SA is inverted and output from the terminal SX.

This embodiment also has the same effect as the second embodiment. [Fourth Embodiment] Next, a fourth embodiment will be described with reference to FIG. Note that, for convenience of explanation, the same configurations as those in FIG.

FIG. 4 shows a cell 2 constructed using cell 1A.
2 using input NAND circuit and cell 1C
The input NOR circuit is shown. Cell 1C of this embodiment
The contact formation region 4a is not formed in the P-type region 4 of the PMOS transistor T2 in FIG. Therefore, the power supply VDD is applied only to the P-type region 2 through the power supply wiring 10.

In the cell 1A, the dummy transistor 13 is formed below the power supply wiring 10, and two dummy transistors 24 and 25, which are NMOS transistors, are formed below the power supply wiring 11. Transistors 24 and 25 are three Ns formed at a predetermined interval.
The type semiconductor region and the gate electrodes 26 and 27 formed above the N-type regions.

In the cell 1C, two dummy transistors 28 and 29 made of PMOS transistors are formed below the power supply wiring 10, and the dummy transistor 14 is formed below the power supply wiring 11. Transistors 28 and 29 are three Ps formed at a predetermined interval.
It is composed of a type semiconductor region and gate electrodes 30 and 31 formed above each P type region.

The 2-input NAND circuit is constructed by using the cell 1A. Also, the above cell 1
In C, the formation region 2a is connected to the wiring 10 by the contact 2b, and the power source VDD is applied to the P-type region 2. The formation regions 5a and 7a are connected to the wiring 11 by the contacts 5b and 7b, and the power supply VSS is applied to the N-type regions 5 and 7. The gate electrodes 8 and 9 have input terminals A1 and A2, respectively.
Is provided. The P-type region 4 and the N-type region 6 are connected by a signal wiring 12, and the wiring 12 is provided with an output terminal X. The two-input NO having the input terminals A1 and A2 and the one output terminal X by the cell 1C as described above.
An R circuit is formed.

In this embodiment, on the cell 1A side, the power supply wiring 11 is patterned so that one N-type region of the dummy transistor 24, the gate electrode 26 and the entire dummy transistor 25 are exposed. The other N-type region of the transistor 24 is connected to the wiring 11.

On the cell 1C side, the power supply wiring 10 is patterned so that the P-type region (drain) common to the dummy transistors 28 and 29 and the gate electrodes 30 and 31 are exposed. The other P of the transistor 28
The mold region is connected to the wiring 10.

A signal line 32 having terminals SA and SX and a signal line 3 having terminals SB and SY are provided between the 2-input NAND circuit (cell 1A) and the 2-input NOR circuit (cell 1C).
3 is wired. A contact 32a is formed in the middle of the signal line 32, and the contact 32a and the gate electrode 2 are formed.
Signal lines 6 and 30 are connected to each other.

The exposed common P-type regions of transistors 28 and 29 and the exposed right N-type of transistor 25.
The mold region and the output terminal OP are connected to each other by signal wiring.

A contact 33a is provided in the middle of the signal line 33.
Are formed, and the contact 33a and the gate electrodes 27 and 31 are formed.
And are connected by signal wiring. Therefore,
2 by dummy transistors 24, 25, 28, 29
An input NAND circuit is configured. When both the input signals of the terminals SA and SB are at the H level, the output terminal OP outputs a signal at the L level (level of the power supply VSS).

This embodiment also has the same effect as that of the second embodiment. In addition to the CMOS inverter and the NAND circuit, the dummy transistors in the plurality of cells may be used to configure other logic circuits such as an OR circuit, a NOR circuit, and an Ex-OR circuit (exclusive OR circuit). Good.

[0049]

As described above in detail, the invention of claim 1 can effectively utilize the empty space in the cell, and can suppress the increase of the area of the semiconductor chip to reduce the cost.

According to the second aspect of the present invention, when the timing adjustment is necessary or when the circuit is changed, the dummy transistor can be used only by changing the power supply wiring. Further, the function can be determined by combining the dummy transistors when the wiring is changed.

According to the third aspect of the invention, the timing can be adjusted by delaying the propagation time of the signal propagating through the signal line. According to the invention of claim 4, a circuit that operates based on the voltage level of the signal of the first signal line can be configured by using a plurality of dummy transistors.

According to the fifth aspect of the invention, the area occupied by the cells can be reduced and the degree of integration can be improved.

[Brief description of drawings]

FIG. 1 is a layout diagram showing a first embodiment embodying the present invention.

FIG. 2 is a layout diagram showing a second embodiment.

FIG. 3 is a layout diagram showing a third embodiment.

FIG. 4 is a layout diagram showing a fourth embodiment.

FIG. 5 is a layout diagram showing a conventional cell.

[Explanation of symbols]

 1A, 1B, 1C Cell 2a, 4a, 5a, 7a Contact formation region 2-4 P-type semiconductor region 5-7 N-type semiconductor region 10,11 Power supply wiring 13,14 Dummy transistor T1, T2 PMOS transistor T3, T4 NMOS transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/08 321 Z

Claims (5)

[Claims] 1. A PMOS transistor (T1, T2)
And the NMOS transistors (T3, T4) are arranged so as to face each other, and power supply wiring (10, T4) is provided at the outer ends of both MOS transistors in the arrangement direction of both MOS transistors.
11), contact forming regions (2a, 4a, 5a) for forming a contact with each other are formed in a direction away from each other to form cells (1A, 1B), and the contact forming regions (2a, 4a, 5a) are formed. ) Above the MOS transistors (T1, T2, T3, T4) in a semiconductor integrated circuit device having a pair of power supply wires (10, 11) extending along the outer ends of the cells (1A, 1B). Inside the pair of power supply wiring (1
The semiconductor integrated circuit device is characterized in that dummy transistors (13, 14) are formed under each of (0, 11). 2. The semiconductor integrated circuit device according to claim 1, wherein the power supply line (10, 11) is patterned so that a part of the dummy transistor (13, 14) is exposed. . 3. The power supply wiring is patterned so that at least the gate contact portion of the dummy transistor is exposed, and the source and drain regions of the dummy transistor are connected to the power supply wiring above the dummy transistor. 3. The semiconductor integrated circuit device according to claim 2, wherein the gate electrode of is connected to a signal line. 4. The power supply wiring is patterned so that, in two different cells, one of a gate contact portion and one of a source / drain region of the dummy transistor provided in each cell is exposed, and each gate electrode is It is characterized in that it is connected to a common first signal line, said one region is connected to a common second signal line, and the other region is connected to said power supply wiring above each region. The semiconductor integrated circuit device according to claim 2. 5. The cell (1A, 1B) is a pair of PMOs.
Each of the pair of PMOS transistors (T1, T2) is composed of an S-transistor (T1, T2) and a pair of NMOS transistors (T3, T4). Two
3, 4) and a pair of gate electrodes (8, 9) formed above the P-type semiconductor regions (2, 3, 4), and the pair of NMOS transistors (T3, T4) are Three N-type semiconductor regions (5, 5) formed at predetermined intervals
6, 7) and a pair of gate electrodes (8, 9) formed above the N-type semiconductor regions (5, 6, 7). The semiconductor integrated circuit device according to one item.