JPH07297185A - Metal wiring, thin film transistor using the same, TFT liquid crystal display device, and method for forming metal wiring - Google Patents

Abstract

(57) [Abstract] [Purpose] To suppress the occurrence of hillocks in metal wiring and to reduce the step difference to improve the coverage of the insulating film formed on the upper part. [Structure] A laminated film of thin films containing Al as a main component,
Moreover, by forming the upper layer film of the laminated film as an Al thin film to which Ta is added, the generation of hillocks can be suppressed. Further, the sectional taper angle θ ₁ of the laminated film is set to 30 ° or more and less than 90 °, and the sectional taper angle θ ₂ of the laminated film is set to 130 ° or more,
When the angle is less than 180 °, the step can be made gentle and the coverage of the insulating film formed on the metal wiring can be improved. By using this metal wiring for the gate electrode of the thin film transistor, the insulation failure of the interlayer insulating film is eliminated, there is no residue of a-Si which is the semiconductor layer in the gap portion of the gate electrode, and it is used for the source electrode / drain electrode. This improves the coverage of the protective insulating film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal wiring, a thin film transistor (hereinafter referred to as "TFT") using the metal wiring, a TFT liquid crystal display device, and a method for forming the metal wiring.

[0002]

2. Description of the Related Art A conventional TFT will be described below.
FIG. 10 is a sectional view showing the basic structure of a conventional TFT. Figure 10
In, 101 is a substrate, 102 is a gate electrode, and 103
Is a gate insulating film, 104 is a first interlayer insulating film, 105 is a semiconductor layer, 106 is a second interlayer insulating film, 107 is an ohmic contact layer, 108 is a source electrode / drain electrode, and 109 is a protective insulating film.

Next, a manufacturing process of the TFT having the above structure will be briefly described with reference to FIG. Hereinafter, the aluminum oxide film is an AlO _x film and the silicon nitride film is SiN.
_{Described as an X} film. A glass substrate is used as the substrate 101,
An Al thin film is formed on this glass substrate by a DC sputtering method and processed by a photolithography technique to form a gate electrode 102. Then, the surface of the gate electrode 102 is anodized and an AlO _x film is formed to form the gate insulating film 103. Then the entire surface in the first interlayer insulating film 104 as a SiN _X film, a-Si film as a semiconductor layer 105, SiN _X as the second interlayer insulating film 106
Three layers of the film are sequentially formed by a chemical vapor deposition method. After that, a SiN _x film that is the second interlayer insulating film 106 is formed in an island shape, and an n ⁺ -type a film is formed as the ohmic contact layer 107.
-Form a Si film. Further, as a barrier metal layer, Ti
After a thin film and an Al thin film as a conductor layer are continuously formed by a DC sputtering method, the Ti thin film, the Al thin film, and the a-Si film are simultaneously patterned by dry etching. Thus, the source electrode / drain electrode 108 composed of two layers of the Ti thin film and the Al thin film is formed. Finally, a SiN _x film is formed on the entire surface as a protective insulating film 109 to form T
FT is completed.

[0004]

However, in the above conventional configuration, when the film is formed by the chemical vapor deposition method, etc.
Due to the presence of a heat step during the manufacturing process, hillocks are generated on the gate electrode 102, the contact property is deteriorated, and the step of the gate wiring portion is large, the cover of the interlayer insulating film formed thereon is large. There are problems that the ledge deteriorates, insulation failure occurs at the pattern edge portion, and a residue of a-Si that is the semiconductor layer 105 and the ohmic contact layer 107 occurs at the time of forming the pattern of the source electrode / drain electrode 108. . Also, on the source electrode and the drain electrode 108, there protective hillocks may occur by deposition of the SiN _X film is an insulating film 109, a problem such as coverage of the protective insulating film 109 because the step is large is deteriorated.

As described above, in the conventional metal wiring such as the gate electrode 102, the source electrode / drain electrode 108, etc., the problem of deterioration of contact property due to the generation of hillocks, steps, etc., and the cover of the insulating film formed on the upper part There was a problem that the ledge was bad. A first object of the present invention is to provide a metal wiring capable of suppressing the generation of hillocks and a manufacturing method thereof.

A second object of the present invention is to provide a metal wiring and a method for manufacturing the same which can make the step gentle and improve the coverage of the insulating film formed on the upper portion. A third object is to suppress the occurrence of hillocks on the gate electrode due to a thermal process in the manufacturing process, to improve the contact property, to eliminate the insulation failure of the interlayer insulating film at the pattern edge portion of the gate electrode, and to further improve the gate property. A thin film transistor in which a residue of a-Si, which is a semiconductor layer, is not generated in a step portion of a wiring portion, hillock generation on a source electrode / drain electrode is suppressed, and coverage of a protective insulating film thereover is favorable. And to provide a TFT liquid crystal display device using the same.

[0007]

According to a first aspect of the present invention, there is provided a metal wiring comprising a laminated thin film having Al as a main component patterned on a substrate, and the upper layer of the laminated film is formed by adding Ta to the film.
It is composed of a thin film. A metal wiring according to a second aspect is the metal wiring according to the first aspect, wherein a sectional taper angle formed by the lower layer film of the pattern edge portion of the laminated film with the substrate is 30.
The cross-section taper angle formed by the upper film of the pattern edge portion of the laminated film and the surface flat portion of the upper film is 130 ° or more and less than 180 °.

According to a third aspect of the present invention, in the metal wiring according to the first or second aspect, the concentration of Ta in the Al thin film to which Ta is added as the upper layer film is 1.0 atomic% or more, 2.0 or more.
It is characterized by being at most atomic%. The metal wiring according to claim 4 is the metal wiring according to claim 1 or 2, wherein
An oxide film is provided between the upper layer film and the lower layer film.

According to a fifth aspect of the present invention, there is provided the metal wiring according to the fourth aspect, wherein the upper layer film is Ta-added Al.
The Ta concentration of the thin film is 1.0 atomic% or more and 3.0 atomic% or less. According to a sixth aspect of the present invention, there is provided the metal wiring according to the first, second, third, fourth or fifth aspect, wherein a part of the surface is covered with an anodic oxide film formed by anodic oxidation.

According to a seventh aspect of the present invention, in a thin film transistor, a gate electrode formed on a substrate and a source electrode formed on the gate electrode with an interlayer insulating film and a semiconductor layer interposed therebetween.
A thin film transistor comprising a drain electrode and a protective insulating film formed on the source electrode / drain electrode, wherein the gate electrode or the source electrode / drain electrode is defined by claim 1, 2, 3, 4, 5 or 6. It is characterized by using metal wiring.

A TFT liquid crystal display device according to an eighth aspect uses the thin film transistor according to the seventh aspect. The method for forming a metal wiring according to claim 9 is a sputtering method in which a lower layer film A is formed on a substrate in vacuum.
l thin film and an Al thin film on which an upper layer film of Ta having an Ta concentration of 1.0 atom% or more and 2.0 atom% or less is added continuously to form a laminated film The process includes a step and a step of patterning the laminated film by etching.

A method of forming a metal wiring according to claim 10 is
In a vacuum by a sputtering method, a step of forming an Al thin film to be a lower layer film on the substrate, a step of forming an Al thin film and then forming an oxide film on the surface of the Al thin film, and a sputtering method in a vacuum to oxidize The concentration of Ta, which is the upper layer film, on the film is 1.0 atom% or more and 3.0 atom% or more.
The following step of forming an Al thin film to which Ta is added,
Al thin film and oxide film as the lower layer film and Ta as the upper layer film
And patterning by etching a laminated film made of an Al thin film to which is added.

A method of forming a metal wiring according to claim 11 is
The method of forming a metal wiring according to claim 9 or 10, characterized in that the method includes a step of etching the patterned laminated film to form a pattern, and then covering a part of the surface of the laminated film with the anodic oxide film by anodic oxidation. The cross-sectional taper angle formed by the lower layer film of the pattern edge portion of the laminated film with the substrate and the cross-sectional taper angle formed by the upper layer film of the pattern edge portion of the laminated film with the surface flat portion of the upper film are respectively shown in FIG. ), Θ ₁ and θ ₂ shown in), and hereinafter referred to as the sectional taper angle θ ₁ and the sectional taper angle θ ₂ .

Further, Al containing Ta is added to Al-T
a, and the concentration of Ta added is fixed, for example, Al is 1.5 at.
Described as% Ta.

[0015]

According to the structure of the present invention, the metal wiring is formed of a laminated film of thin films containing Al as a main component, and the upper film of the laminated film is an Al thin film to which Ta is added. It is possible to suppress the occurrence of the above phenomenon and improve the coverage of the insulating film formed on the metal wiring. Further, the sectional taper angle θ ₁ formed by the lower layer film of the pattern edge portion of the laminated film with the substrate is 30 ° or more and less than 90 °, and the upper layer film of the pattern edge portion of the laminated film forms the surface flat portion of the upper layer film. Section taper angle θ ₂ is 130 ° or more, 1
By setting the angle to less than 80 °, the step of the metal wiring can be made gentle and the coverage of the insulating film formed on the metal wiring can be improved. Further, the withstand voltage can be improved by covering a part of the surface with an anodic oxide film formed by anodic oxidation.

The above two sectional taper angles θ ₁ and θ
₂ is Ta in which the concentration of Ta thin film as the lower layer film on the substrate and Ta as the upper layer film on the Al thin film is 1.0 atom% or more and 2.0 atom% or less in the vacuum by the sputtering method. After forming a continuous film with an Al thin film added with Al, etching is performed to form a pattern, or Al is used as a lower layer film on the substrate in a vacuum by a sputtering method.
After forming the thin film, the vacuum is broken to form an oxide film, and then, in a vacuum by a sputtering method, the concentration of Ta serving as an upper layer film on the oxide film is 1.0 atomic% or more, and 3.
Forming an Al thin film containing Ta of 0 atomic% or less,
It is obtained by etching and patterning.

Further, by using this metal wiring for the gate electrode of the thin film transistor, the contact property is good while suppressing the generation of hillocks on the gate electrode due to the thermal process in the manufacturing process, and the interlayer at the pattern edge portion of the gate electrode is suppressed. Insulation defects of the insulating film can be eliminated, and generation of a residue of a-Si that is a semiconductor layer can be suppressed in the step portion of the gate wiring portion.

Further, by using the metal wiring for the source electrode / drain electrode of the thin film transistor, generation of hillocks on the source electrode / drain electrode can be suppressed and the coverage of the protective insulating film thereon can be improved. .

[0019]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a sectional view showing the basic structure of a TFT using a metal wiring as a gate electrode in the first embodiment of the present invention. In FIG. 1, 11 is a substrate, 12 is a gate electrode, 13 is a gate electrode lower layer portion, 14 is a gate electrode upper layer portion, 15 is a first interlayer insulating film, 16 is a semiconductor layer, 17 is a second interlayer insulating film, 18 is an ohmic contact layer, 1
Reference numeral 9 is a source electrode / drain electrode, and 110 is a protective insulating film.

The method of manufacturing this TFT will be described in detail below with reference to FIG. A glass substrate was used as the substrate 11. On this glass substrate, a pure Al thin film without addition of impurities as a gate electrode lower layer portion 13, and a gate electrode upper layer portion 14
As the Al-1.5 at% Ta thin film is continuously formed by the DC sputtering method without breaking the vacuum so that the film thickness becomes 250 nm and 100 nm, respectively, and then processed by the photolithography technique to form the gate electrode 12 and To do. As the etching solution, a phosphoric acid: nitric acid: acetic acid: water system solution is used.
The liquid temperature was kept constant at 40 ° C. As a result, the sectional taper angle θ ₁ (see FIG. 2) was about 50 °. The photoresist pattern serving as a mask when etching the gate electrode 12 is shown by reference numeral 25 in FIG.
At the time of this etching, the etching liquid penetrates into the interface between the surface of the gate electrode upper layer portion 14 and the photoresist pattern 25 (FIG. 2), and the surface of the gate electrode upper layer portion 14 is etched more than other portions, so that the cross section is reduced. It becomes a taper shape. Here, although the etching rate of the pure Al thin film (gate electrode lower layer portion 13) with respect to the etching liquid used in this example is higher than that of the Al-1.5 at% Ta thin film (gate electrode upper layer portion 14), The feature is that the cross-section has a tapered shape as shown in FIG.

Next, Si is used as the first interlayer insulating film 15.
An N _x film having a film thickness of 300 nm and a-Si as the semiconductor layer 16
The film has a film thickness of 50 nm, and SiN is used as the second interlayer insulating film 17.
_{The X} film is sequentially formed by a chemical vapor deposition method so as to have a film thickness of 200 nm. The second interlayer insulating film 17 S
The iN _x film is formed into islands. Next, as the ohmic contact layer 18, an n ⁺ -type a-Si film is formed on the entire surface so as to have a film thickness of 50 nm.

Further, a Ti thin film having a thickness of 100 nm as a barrier metal layer and a pure Al thin film having a thickness of 350 nm as a conductor layer are continuously formed thereon by a DC sputtering method, and then Ti is dry-etched. Thin film,
Pattern pure Al thin film and a-Si film. As a result, the source / drain electrode 19 consisting of two layers of the Ti thin film and the pure Al thin film is formed. Finally, a SiN _x film is formed as the protective insulating film 110 on the entire surface so as to have a film thickness of 200 nm, and the TFT according to the present invention is completed.

The thicknesses of the pure Al thin film and the Al-1.5 at% Ta thin film forming the gate electrode 12 are each 150 n in order to suppress the generation of voids and hillocks.
m or more and 80 nm or more, and the upper limit is determined according to the configuration, if necessary. Further, as described below, pure Al
The thin film and the Al-1.5 at% Ta thin film may be formed by discontinuous film formation.

FIG. 2 shows a cross-sectional taper shape of the metal wiring used as the laminated film used for the gate electrode. The cross-sectional taper shape is a smooth taper shape (FIG. 2B), a two-step taper shape (FIG. 2C), or a tapered taper shape (FIG. 2C) depending on the method of forming the laminated film and the concentration of Ta added in the upper layer portion. Two
There are three types of (d)). Each taper shape will be briefly described. In addition, FIG. 2A is an explanatory view of the taper angle of the cross section as described above.

The taper shape of the metal wiring shown in FIG. 2B is used for the gate electrode 12 of this embodiment, and is a pure Al thin film 21 and an Al-1.5 at% Ta thin film 22.
Can be obtained by continuously forming a film. The tapered shape shown in FIG. 2C is obtained by forming the pure Al thin film 21 and then breaking the vacuum once to form the Al-1.5 at% Ta thin film 22. This tapered shape is pure Al
Since the oxide film 24 is formed at the interface between the thin film 21 and the Al-1.5 at% Ta thin film 22, the etching time is consumed there, so that the Al-1.5 at% Ta thin film 22 further has a taper angle and a taper. There are two stages of shape,
Furthermore, there is no occurrence of a histograph as shown in FIG. Since the oxide film 24 is so thin as to have a film thickness of 10 Å or less, it does not function as an insulator and does not affect the function as a gate electrode or wiring. If the thickness of the oxide film 24 is 10
If it is Å, the withstand voltage is 0.7 V or less, and its insulating property is lost when a voltage is applied.

The taper shape shown in FIG. 2D is pure Al.
It can be obtained by continuously forming the thin film 21 and the Al-2.5 at% Ta thin film 23 without breaking the vacuum. Here, the Al-2.5 at% Ta thin film 23 is the same as A in FIG.
The Ta concentration is higher than that of the 1-1.5 at% Ta thin film 22. If this taper-shaped metal wiring is used for the gate electrode, the source electrode / drain electrode, the coverage of the interlayer insulating film or the protective insulating film is deteriorated, and the interlayer insulating film causes insulation failure.

FIG. 3 shows the amount of hillocks and abnormal hillocks generated with respect to the additive concentration of Ta in Al of the metal wiring in which the pure Al thin film and the Al--Ta thin film are laminated, the contact resistance, and the resistance of the hiss shown in FIG. 2 (d). The relation diagram of incidence is shown.
4 is a perspective view of the abnormal hillock described here, and 41 is an abnormal hillock generated in the metal wiring 42. Note that FIG. 4 is an enlarged view with a magnification of 8200 times, and the size of this abnormal hillock 41 is 4.5 μm in length and 4.3 in width.
The height was 4.0 μm.

As shown in FIG. 3, in order to suppress the hillocks and improve the contact resistance, T in Al should be used.
Although it is necessary to set the concentration of a added to 1.0 atomic% or more,
If the added concentration exceeds 3.0 atomic%, abnormal hillocks as shown in FIG. 4 increase. In addition, a pure Al thin film and Al-
In the case of continuously forming a Ta thin film, if the concentration of Ta added exceeds 2.0 atomic%, the number of the peaks shown in FIG. 2D increases. Incidentally, when the pure Al thin film and the Al-Ta thin film are formed discontinuously, the peak-shaped one does not occur as described in the explanation of FIG. 2 (c).

From the above, the addition amount of Ta in Al is 1.0 atomic% or more due to factors such as improvement of hillock and contact property in continuous film formation, generation of hiss and so on.
0 atomic% or less is optimal, and since a film is not generated in the case of discontinuous film formation, 1.0 atomic% or more and 3.0 atomic% or less is optimal due to factors such as hillocks and improvement in contact property. .

Metal wiring (gate electrode 12) is shown in FIG.
Of the occurrence rate of chipping of the pattern edge portion with respect to the taper angle θ ₁ of the cross section, and FIG. 5B shows the incidence rate of defective insulation of the pattern edge portion of the interlayer insulating film (first interlayer insulating film 15) with respect to the taper angle of the cross section θ ₂ Indicates. FIG. 6 is a perspective view of a chipped portion of the pattern edge portion, and 61 is a chipped portion of the metal wiring 63 formed on the substrate 62. Note that FIG. 6 is an enlarged view at a magnification of 49000 times, and the size of the chipped portion 61 was about 0.7 μm in width, about 0.15 μm in height, and about 0.7 μm in depth.

As shown in FIG. 5, if the sectional taper angle θ ₁ becomes too small, the occurrence rate of chipping at the pattern edge portion as shown in FIG. 6 increases. In addition, the taper angle θ
_The larger ₂ means better coverage of the interlayer insulating film,
The incidence of insulation failure at the pattern edge is reduced. Further, when the metal wiring is used for the source electrode / drain electrode as in the second embodiment described below, the coverage of the protective insulating film is improved. When the metal wiring is used as the gate electrode 12 as in this embodiment, the semiconductor layer 16 is reduced as the sectional taper angle θ ₁ becomes smaller.
Also, the possibility of the residue of a-Si in the ohmic contact layer 18 is reduced.

From the above, the sectional taper angle θ ₁ is 3
The optimum angle is 0 ° or more and less than 90 °, and the sectional taper angle θ ₂ is 130 ° or more and less than 180 °. The sectional taper angles θ ₁ and θ ₂ can also be controlled by changing the nitric acid concentration of the etching solution, and if the nitric acid concentration is increased,
Since the sectional taper angle θ ₁ is small and the sectional taper angle θ ₂ is large, the angle can be adjusted as necessary.

According to this embodiment, the gate electrode 12 is
If a thin film laminated film containing Al as a main component is used and the film forming method is continuous film formation, Al containing 1.0 atomic% or more and 2.0 atomic% or less of Ta in the gate electrode upper layer 14 is used. If it is used and if the film formation is discontinuous, A in which Ta is added at 1.0 atom% or more and 3.0 atom% or less in the gate electrode upper layer portion A
By using ₁ , the sectional taper angle θ ₁ is 30 ° or more and less than 90 °, the sectional taper angle θ ₂ is 130 ° or more,
Tapered to less than 180 °, thereby causing no problems with hillocks and contact properties on the gate electrode 12,
Insulation defects of the interlayer insulating film 15 at the pattern edge portion can be eliminated, and a-Si residue of the semiconductor layer 16 and the ohmic contact layer 18 can be eliminated at the step portion of the gate electrode 12.

On the other hand, the TFT characteristics of this embodiment are equivalent to those of the conventional example. That is, according to this embodiment, it is possible to have excellent TFT characteristics, eliminate the occurrence of defects in the manufacturing process, and improve the manufacturing yield. Therefore, if this TFT is used in a TFT liquid crystal display device, TF
The manufacturing yield of the T liquid crystal display device can be improved.
This also applies to the second and third embodiments described below.

[Second Embodiment] A second embodiment of the present invention will be described below with reference to the drawings. FIG. 7 shows the metal wiring in the second embodiment of the present invention as a source electrode.
It is a basic composition sectional view of TFT used for a conductor layer of a drain electrode. In FIG. 7, 71 is a substrate, 72 is a gate electrode, 73 is a first interlayer insulating film, 74 is a semiconductor layer, 75 is a second interlayer insulating film, 76 is an ohmic contact layer, 7
Reference numeral 7 is a source electrode / drain electrode composed of a barrier metal layer 78, a conductor layer lower layer portion 79a and a conductor layer upper layer portion 79b, and 710 is a protective insulating film.

The manufacturing method of this TFT will be specifically described below with reference to FIG. A glass substrate was used as the substrate 71. After forming a Cr thin film with a thickness of 200 nm on this glass substrate, patterning was performed to form a gate electrode 72. Then, a SiN _x film as the first interlayer insulating film 73 is formed to a film thickness of 30.
0 nm, an a-Si film as the semiconductor layer 74 having a film thickness of 50 n
m, a SiN _x film as the second interlayer insulating film 75 having a film thickness of 20
After sequentially deposited by chemical vapor deposition such that 0 nm, the second interlayer insulating film 75 a is SiN _X film into an island shape. Then, as the ohmic contact layer 76, an n ⁺ type a
A -Si film is formed on the entire surface so as to have a film thickness of 50 nm.

Further, a Ti thin film having a thickness of 100 nm is used as the barrier metal layer 78, and pure A is used as the conductor layer lower layer portion 79a.
l thin film having a film thickness of 250 nm and an Al-1.5 at% Ta thin film as a conductor layer upper layer portion 79b having a film thickness of 100 nm are continuously formed by a DC sputtering method. Then, the pure Al thin film and the Al-1.5 at% Ta thin film are patterned by wet etching. As the etching solution, a phosphoric acid: nitric acid: acetic acid: water system solution is used, and the solution temperature is 40
The temperature was constant.

Subsequently, the Ti thin film which is the barrier metal layer 78 and the a-Si film of the semiconductor layer 74 and the ohmic contact layer 76 are patterned by dry etching. Thus, the source / drain electrode 77 is formed. Finally, a SiN _x film is formed as the protective insulating film 710 so as to have a film thickness of 200 nm, and the TFT according to the present invention is completed.

Also, as in the first embodiment, the pure Al thin film of the conductor layer lower layer portion 79a and the Al of the conductor layer upper layer portion 79b are formed.
The -1.5 at% Ta thin film may be formed by discontinuous film formation. In the case of discontinuous film formation, a pure Al thin film and Al-
An oxide film is formed between the thin film and the 1.5 at% Ta thin film. According to this embodiment, a thin film laminated film containing Al as a main component is used as the conductor layer of the source electrode / drain electrode 77,
As in the first embodiment, if the film forming method is continuous film forming,
1. At least 1.0 atomic% of Ta in the conductor layer upper layer portion 79b, 2.
By using Al added with 0 atomic% or less, and in the case of discontinuous film formation, by using Al added with 1.0 atomic% or more and 3.0 atomic% or less of Ta in the conductor layer upper layer portion 79b, The cross-section taper angle θ ₁ of the conductor layer of the electrode / drain electrode 77 is 30 ° or more and less than 90 °, and the cross-section taper angle θ ₂ is 130 ° or more and less than 180 °, whereby the source / drain electrode 77 is formed. The upper hillocks are suppressed, and the coverage of the protective insulating film 710 is improved.

Further, similarly to the gate electrode shown in the third embodiment described below, the surface of the source electrode / drain electrode 77 of this embodiment is anodized to further suppress the generation of hillocks. . [Third Embodiment] A third embodiment of the present invention will be described below with reference to the drawings.

FIG. 8 is a sectional view of the basic structure of a TFT using a metal wiring as a gate electrode in the third embodiment of the present invention. In FIG. 8, 81 is a substrate, 82 is a gate electrode,
83 is a gate insulating film, 84 is a first interlayer insulating film, 85 is a semiconductor layer, 86 is a second interlayer insulating film, 87 is an ohmic contact layer, 88 is a source electrode / drain electrode, 89
Is a protective insulating film.

The method of manufacturing this TFT will be specifically described below with reference to FIG. A glass substrate was used as the substrate 81. On this glass substrate, as in the case of the first embodiment, pure A
l thin film and Al-1.5 at% Ta thin film are continuously formed by a DC sputtering method without breaking the vacuum so as to have film thicknesses of 250 nm and 100 nm, respectively, and then processed by a photolithography technique to form a gate electrode. 82. A phosphoric acid: nitric acid: acetic acid: water solution was used as the etching solution, and the solution temperature was kept constant at 40 ° C. As a result, the sectional taper angle θ ₁ became about 50 °.

Then, in a later step, a resist pattern is formed in a portion where a contact hole is formed and an electrode is taken out, and the gate electrode 8 where the resist pattern is not formed is formed.
The gate insulating film 83 is formed by anodizing the surface of No. 2 and forming an anodized film (AlO _x film) of 200 nm so as to cover the gate electrode 82. Here, as the anodizing liquid, a mixture of 1% by weight ammonium borate aqueous solution and ethylene glycol was used, and the temperature of the liquid was 30 ° C.
Constant. Further, the constant current is applied during the anodization, and the voltage is, for example, about 1.4 nm per 1 V when the anodized film is formed to a thickness of 200 nm.
It was set to 0V.

The subsequent steps are the same as those in the first embodiment, and the description thereof will be omitted. That is, the first interlayer insulating film 8
4, the semiconductor layer 85, the second interlayer insulating film 86, the ohmic contact layer 87, the source electrode / drain electrode 88, and the protective insulating film 89 are respectively the first interlayer insulating film 15, the semiconductor layer 16, and the first insulating layer 15 shown in FIG. 2 interlayer insulating film 17, ohmic contact layer 18, source electrode / drain electrode 19,
It corresponds to the protective insulating film 110.

As with the first embodiment, the pure Al thin film and the Al-1.5 at% Ta thin film may be formed by discontinuous film formation. FIG. 9 shows the pure Al thin film and Al- of this example.
Using a laminated film formed by continuously forming a 1.5 at% Ta thin film,
The breakdown voltage of the AlO _x film obtained by anodizing the metal wiring having the tapered shape shown in FIG. 2B is shown by a solid line 91, and a pure Al thin film and an Al-1.5 at% Ta thin film are used as a laminated film by discontinuous film formation. The withstand voltage of the AlO _x film obtained by anodizing the metal wiring whose tapered shape is shown in FIG.
The withstand voltage of the AlO _x film obtained by anodizing the metal wiring whose tapered shape is shown in FIG. 2D using a laminated film formed by continuously forming a pure Al thin film and an Al-2.5 at% Ta thin film is broken line 93.
Indicate.

As shown in FIG. 9, FIG. 2 (b) and FIG.
By anodizing the tapered metal wiring of (c), an insulating film having an excellent withstand voltage can be obtained. As described above, according to the third embodiment, in addition to the first embodiment, the surface of the gate electrode 82 is anodized to form AlO _x.
By covering the film with the gate insulating film 83, generation of hillocks can be further suppressed, and the gate insulating film 83 with excellent withstand voltage can be obtained.

[0047]

As described above, according to the present invention, the metal wiring is
An insulating film formed on the upper part of the metal wiring by suppressing the generation of hillocks on the metal wiring by forming a laminated film of a thin film containing 1 as a main component and forming an upper layer film of the laminated film with an Al thin film. The coverage of the membrane can be improved. Further, the sectional taper angle θ ₁ formed by the lower layer film of the pattern edge portion of the laminated film with the substrate is 30 ° or more and less than 90 °, and the upper layer film of the pattern edge portion of the laminated film forms the surface flat portion of the upper layer film. By setting the sectional taper angle θ ₂ to 130 ° or more and less than 180 °, the step of the metal wiring can be made gentle and the coverage of the insulating film formed on the metal wiring can be improved. Further, the withstand voltage can be improved by covering a part of the surface with an anodic oxide film formed by anodic oxidation.

Further, by using this metal wiring for the gate electrode of the thin film transistor, the contact property is good while suppressing the generation of hillocks on the gate electrode due to the thermal process in the manufacturing process, and the interlayer at the pattern edge portion of the gate electrode is suppressed. Insulation defects of the insulating film can be eliminated, and generation of a residue of a-Si that is a semiconductor layer can be suppressed in the step portion of the gate wiring portion.

Further, by using the metal wiring for the source electrode / drain electrode of the thin film transistor, generation of hillocks on the source electrode / drain electrode can be suppressed and the coverage of the protective insulating film thereon can be improved. . Therefore, it is possible to eliminate the occurrence of defects in the manufacturing process of this thin film transistor and improve the manufacturing yield. If this TFT is used in a TFT liquid crystal display device, the manufacturing yield of the TFT liquid crystal display device can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view of the basic structure of a TFT using a metal wiring as a gate electrode in a first embodiment of the present invention.

FIG. 2A is a sectional taper angle θ ₁ or θ _{2 of a} metal wiring.
, (B) is a smooth tapered sectional view, (c) is a two-step tapered sectional view,
(D) is a cross-sectional view of a tapered taper shape.

FIG. 3 is a relationship diagram of the amount of hillocks and abnormal hillocks generated with respect to the concentration of Ta added to Al in a metal wiring in which a pure Al thin film and an Al—Ta thin film are laminated, the contact resistance, and the incidence of hiss.

FIG. 4 is a perspective view of an abnormal hillock.

5 is a relationship diagram of the chipping occurrence rate, and poor insulation incidence of pattern edge portion of the interlayer insulating film to the cross-sectional taper angle theta ₂ of the pattern edge portion to the cross-sectional taper angle theta ₁ of the metal interconnect.

FIG. 6 is a perspective view of a chipped portion of a pattern edge portion of metal wiring.

FIG. 7 is a cross sectional view showing the basic constitution of a TFT in which a metal wiring according to a second embodiment of the present invention is used for a conductor layer of a source electrode / drain electrode.

FIG. 8 is a cross sectional view showing the basic constitution of a TFT using a metal wiring as a gate electrode in the third embodiment of the present invention.

FIG. 9 is a third embodiment of the invention in which the metal wiring having the tapered shape shown in FIGS. 2 (b) to 2 (d) is anodized A.
is a diagram illustrating the breakdown voltage of lO _X film.

FIG. 10 is a cross-sectional view of the basic configuration of a conventional TFT.

[Explanation of symbols]

 11 substrate 12 gate electrode 13 gate electrode lower layer portion 14 gate electrode upper layer portion 15 first interlayer insulating film 16 semiconductor layer 17 second interlayer insulating film 18 ohmic contact layer 19 source electrode / drain electrode 110 protective insulating film 21 pure Al thin film 22 Al-1.5 at% Ta thin film 23 Al-2.5 at% Ta thin film 24 Oxide film 71 Substrate 72 Gate electrode 73 First interlayer insulating film 74 Semiconductor layer 75 Second interlayer insulating film 76 Ohmic contact layer 77 Source electrode -Drain electrode 79a Conductor layer lower layer portion 79b Conductor layer upper layer portion 710 Protective insulating film 81 Substrate 82 Gate electrode 83 Gate insulating film 84 First interlayer insulating film 85 Semiconductor layer 86 Second interlayer insulating film 87 Ohmic contact layer 88 Source / drain electrode 89 Protective insulation film

Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number for FI 9056-4M H01L 29/78 311 G 9056-4M 311 S (72) Inventor Iwa ▲ Katsuo Kadoma City, Osaka Prefecture Oji Kadoma 1006 Matsushita Electric Industrial Co., Ltd. (72) Inventor Rei Otsuka Rei Odaka, Kadoma City Osaka Pref. 1006 Kadoma Matsushita Electric Industrial Co., Ltd. In-house (72) Inventor Jun Kuwata 1006 Kadoma, Kadoma-shi, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Tomoji Dobashi, 1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (11)

[Claims] 1. A laminated film of a thin film containing Al as a main component patterned on a substrate, wherein an upper film of the laminated film is T.
Metal wiring consisting of an Al thin film added with a. 2. A cross-sectional taper angle formed by a lower layer film of a pattern edge portion of the laminated film with a substrate is 30 ° or more and less than 90 °, and an upper layer film of the pattern edge portion of the laminated film has a surface flat portion of the upper layer film. The metal wiring according to claim 1, wherein the taper angle of the cross section is 130 ° or more and less than 180 °. 3. The metal wiring according to claim 1, wherein the concentration of Ta in the Al thin film to which Ta is added as the upper layer film is 1.0 atom% or more and 2.0 atom% or less. 4. The metal wiring according to claim 1, wherein an oxide film is provided between the upper layer film and the lower layer film. 5. The metal wiring according to claim 4, wherein the concentration of Ta in the Al thin film to which Ta is added as the upper layer film is 1.0 atom% or more and 3.0 atom% or less. 6. The metal wiring according to claim 1, 2, 3, 4, or 5, wherein a part of the surface is covered with an anodic oxide film formed by anodic oxidation. 7. A gate electrode formed on a substrate, a source electrode / drain electrode formed on the gate electrode via an interlayer insulating film and a semiconductor layer, and a source electrode / drain electrode.
A thin film transistor comprising a protective insulating film formed on a drain electrode, wherein the metal wiring according to claim 1, 2, 3, 4, 5 or 6 is used for the gate electrode or the source electrode / drain electrode. Characteristic thin film transistor. 8. A TFT liquid crystal display device using the thin film transistor according to claim 7. 9. The concentration of Ta thin film, which is a lower layer film on the substrate, and Ta, which is an upper layer film on the Al thin film, is 1.0 atomic% or more in a vacuum by a sputtering method.
A method for forming metal wiring, comprising: a step of continuously forming an Al thin film containing Ta of 0 atomic% or less to form a laminated film; and a step of etching and patterning the laminated film. 10. A step of forming an Al thin film to be a lower layer film on a substrate in a vacuum by a sputtering method; a step of forming the Al thin film and then forming an oxide film on the surface of the Al thin film; 2. The concentration of Ta, which is an upper layer film, on the oxide film is 1.0 atomic% or more in a vacuum according to the method.
A step of forming an Al thin film containing Ta of 0 atomic% or less, and etching a laminated film composed of the Al thin film to be the lower layer film, the oxide film and the Al thin film to which the Ta layer is to be the upper layer film, and patterning A method of forming a metal wiring, the method including: 11. The metal wiring according to claim 9, further comprising a step of etching and patterning the laminated film and then covering a part of the surface of the laminated film with the anodic oxide film by anodic oxidation. Forming method.