JPH07295922A - Data processing device and data processing system using the same - Google Patents

Abstract

(57) [Summary] [Object] To provide a microcomputer capable of automatically generating a command write bus cycle for an external flash memory whose operation is instructed by a command. [Configuration] An address area to which an external bus cycle other than an external bus cycle designated by a built-in bus master such as a CPU or a DMAC can be designated by a register 45, and an address output by the bus master with respect to the address designated by the register 45 Further, a timing control circuit 44 for automatically adding an external bus cycle such as command writing based on the control signal is provided in the bus controller 4 of the microcomputer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and relates to a technique effective when applied to a memory which requires a command for an operation instruction, for example, a microcomputer to which a flash memory is connected. is there. The present invention also relates to an emulator that evaluates a system to which such a data processing device is applied or debugs software for the system.

[0002]

[Prior Art] March 1993, Hitachi, Ltd. "H
8/3003 Hardware Manual ”, a microcomputer composed of a semiconductor integrated circuit uses an address bus, a data bus, and a control signal as an external address with a part or all of an address space of a CPU as a central processing unit. It can input / output to / from the outside and read / write the memory or other circuits connected to the outside. At this time, depending on the setting of a predetermined register, an area decode signal corresponding to an area obtained by dividing the address space, for example, a chip selection signal is output, a row address / column address is multiplexed and output, and various strobe signals are output. Change the waveform, mask ROM, static R
AM (SRAM), pseudo static RAM (PSRA
Various memories such as M) and dynamic RAM (DRAM) are directly connected to enable read / write.

[0003]

However, the address / data given to or read from the memory at the time of reading / writing may not be directly related to the information stored in the memory. For example, a flash memory described in "Hitachi IC Memory 2" pp280-304 issued by Hitachi, Ltd. in September 1993, in which a command for designating a memory operation must be given in advance from a data bus. There is.

FIG. 26 shows an example of the command of the flash memory. In the figure, W is a write operation, R is
Is a read operation, × is an arbitrary value, RA is a read address, R
D is read data, BA is a block address, PA is a write address, PD is write data, and H'is a hexadecimal number. The block address BA is address information for designating a block to be erased in block units. For example, when writing, write the command (H'10) before writing the data, and then write
The data to be written (P) to the address to be written (PA)
D) is written.

A program example of the write operation by the CPU is shown below. The instruction is the same as the CPU described in "H8 / 3003 Hardware Manual" issued by Hitachi, Ltd. in March 1993. MOV. B #CMD, R0L ... (1) MOV. BR0L, @FMEM ... (2) MOV. B #DATA, R0L ... (3) MOV. BR0L, @WADR (4) In the description of the above command, CMD is a command value (see FIG. 2).
In the example of No. 6, H'10), DATA is write data, and # indicates immediate data. Also, FMEM
Is an arbitrary address of the flash memory, and WADR is a write address. @ Indicates a memory address. The instruction (1) is an instruction to transfer the command CMD to the register R0L of the CPU, and (2) is an instruction to transfer the command of the register R0L to the address @FMEM of the flash memory.
(3) is write data DAT in the register R0L of the CPU
An instruction to transfer A, and (4) is an instruction to transfer the data in the register R0L to the write address WADR.

The address can be designated as an absolute address, or can be a register indirect or the like. Write data may also be prepared on the general-purpose register. As is clear from the above instruction description, in writing 1-byte data, the instructions (1) and (2) for writing the command into the flash memory are necessary. 2 in total
Double instruction execution is required. As a result, the program size also increases and the processing speed also decreases.

Since the CPU can execute an arbitrary program, if the load of software is increased as described above,
It is possible to write data to the flash memory by the command method. However, the direct memory access controller (DMAC) and the like can only perform simple data transfer, determine whether the access target is, for example, SRAM or flash memory, and insert a further command. Is not easy. According to the study by the present inventor, when writing such data is to be realized by the DMAC, the transfer source must also store the command together with the write data.
If such an attempt is actually made, the load on the CPU prior to the DMA transfer will be significantly increased, and the throughput of the system will be significantly reduced. In other words, it is not a realistic method. An example of the DMAC is described in "H8 / 3003 Hardware Manual" issued by Hitachi, Ltd. in March 1993. Also, DMA
In addition to C, data transfer controller (DT
The same applies to C) and the like. The DTC is described, for example, in "H8 / 532 Hardware Manual" issued by Hitachi, Ltd. in December 1988.

An object of the present invention is to provide a data processing device capable of automatically adding or inserting a bus cycle for command transfer to a peripheral circuit such as a flash memory whose operation is instructed by a command. Another object of the present invention is to provide a data processing device which automatically adds or inserts the bus cycle according to bus information for accessing a required peripheral circuit. It is another object of the present invention to provide a data processing device which automatically adds or inserts the bus cycle by writing control information to a predetermined internal register. Still another object of the present invention is to reduce the instruction execution time for accessing a peripheral circuit such as a flash memory whose operation is instructed by a command, and
It is to provide a data processing device that can reduce the program size. Another object of the present invention is to provide a data processing device such as a DMAC which can be directly connected to and accessed by a peripheral circuit such as a flash memory whose operation is instructed by a command. In addition, the present invention provides an emulator for evaluating the system to which the data processing device is applied so that the function of the data processing device capable of automatically adding or inserting a bus cycle for command transfer and performing software debugging for the system. It is to provide technology that does not reduce usability.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

(1) A data processing device (for example, a single-chip micro-processor) that incorporates bus master means (for example, CPU2 or DMAC3) that can use an external bus and can be connected to an external circuit (for example, flash memory 10) whose operation is instructed by a command. The computer 1), in response to an instruction to access an external predetermined address space from the bus master means, prior to generation of an external bus access cycle corresponding to the access instruction, the external to the predetermined address space Bus control means for generating a first command write cycle for writing a command for instructing the operation of the circuit (for example, bus controller 4)
It is equipped with.

(2) The bus control means is an address space designating means (for example, a register CMDC) for designating an address space in which the first command write cycle is to be activated.
R) and determination means (for example, control circuit 41) for determining whether or not the access address by the bus master means is included in the address space designated by the address space designation means.
And a timing control unit (for example, a timing control circuit 44 including the configuration shown in FIG. 17) that generates the first command write cycle based on the detection result of inclusion by the determination unit.

(3) The command to be written in the first command write cycle can be rewritably held in the command storage means (eg, registers WCMD, CDATA0, CDATA1).

(4) Further, in the bus control means, the control register means (for example, register CNTL) and the first bit (for example, bits BE0 to BE0) of the control register means by the CPU are provided.
Timing control means (eg, shown in FIG. 19) for generating a second command write cycle for writing predetermined command data (for example, a command for erasing a block of the flash memory) in a predetermined address space by operating BE3). Control circuit 4 including a configuration
4) and can be further provided.

(5) The address to be output in the second command write cycle can be stored in the address storage means (for example, registers BADR0 to BADR3).

(6) Further, in the bus control means, the CPU controls the second bit (for example, bit R) of the control register means.
By operating the E, bit POL), a signal (for example, the output signal RDY / of the flash memory) input from a predetermined external terminal (for example, the ready input terminal READY) is input.
BUSY *) may be further provided with timing control means (eg, timing control circuit 44 including the configuration shown in FIG. 19) for generating an external read cycle for performing polling control.

(7) It is desirable to provide the emulation data processing device with an emulation interface for outputting an identification signal indicating whether or not the external bus cycle is the command write cycle. Further, in the emulation data processing device, the CPU outputs a control signal for prohibiting the generation of the first command cycle by the bus control means based on a predetermined external interrupt (for example, a break signal). Such a data processing device is
A data processing system can be configured by an emulator coupled to an emulation interface included in the data processing device. The emulator has a trace memory and a break control circuit. The trace memory inputs and stores the identification signal together with bus information of the data processing device, and the break control circuit predicts the control state of the data processing device. When the set state is reached, a break signal is output as the interrupt signal to the data processing device.

(8) The data processing device further comprises a direct memory access controller as the bus master means, and can be formed as a single chip microcomputer on one semiconductor substrate. Such a data processing device can configure a data processing system, for example, by including a flash memory as an external circuit directly connected to the data processing device.

(9) The data processing device having a built-in bus master unit capable of using an external bus and connectable to a flash memory whose operation is instructed by a command responds to an instruction to access an external predetermined address space by the bus master unit. And bus control means for generating a command write cycle for writing a command for instructing the operation of the flash memory to the predetermined address space prior to the generation of the external bus access cycle corresponding to the access instruction. It can be formed and formed on one semiconductor substrate, including an external input terminal for a signal indicating the internal operation state of the flash memory instructed by the command write.

[0020]

According to the means (1) to (3) described above, when a predetermined address space allocated to an external circuit such as a flash memory is accessed, the operation of the external circuit is performed prior to the access. A first command write cycle for writing an instructed command is automatically inserted. This eliminates the need for a process for writing a command each time writing in a byte or page unit to the flash memory and a program description defining the command.

According to the means (4) and (5) described above, when a predetermined bit of the built-in control register is operated by the CPU, a command for instructing the operation of the external circuit is written next to the operation. Second command write cycle is automatically inserted. This means that the command description may specify writing to the control register, etc. even when command writing divided into a plurality of times such as block erasing to the flash memory is required. And the reduction of the program size are realized.

According to the above-mentioned means (6), starting and maintaining the external read cycle for polling control by the operation of the predetermined bit of the built-in control register by the CPU is similar to the above in that the external bus cycle is generated. It is possible to improve the data processing efficiency and reduce the program size.

According to the above-mentioned means (7), there is no corresponding instruction description in the specially inserted command write cycle, but if this does not hinder the emulation for verifying the instruction execution locus from the trace information. Thus, the identification signal acts to indicate that it is a specially inserted command write cycle. Also, in the state where the operation space of the data processing device is switched after the break and the control program for emulation is executed, the control RAM or the like is allocated so as to overlap the address at which the command write cycle should be inserted. In this case, a command write cycle is automatically generated to prevent the data in the RAM from being accidentally rewritten, and the function of the data processing apparatus is to add or insert a command write cycle automatically. Do not reduce the usability of the emulator that evaluates the system to which is applied and debugs the software for the system.

Even if the bus master means is a direct memory access controller as explicitly shown in the above means (8), the direct memory access controller can also perform such a command format flash by the automatic insertion of the command write cycle. The memory can be used as a data transfer source or a data transfer destination.

According to the data processor of the above means (9), the interface with the flash memory whose operation is instructed by the command is simplified and the usability is improved.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a single chip microcomputer which is an embodiment of a data processing device according to the present invention. The single-chip microcomputer 1 shown in the figure includes a CPU 2, a DMAC 3, a bus controller (BSC) 4, a ROM 5, a RAM 6, a timer 7, a serial communication interface (SCI) 8, first to ninth input / output ports IOP1 to IOP9, The clock oscillator (CPG) 9 is composed of functional blocks or modules, and is formed as a semiconductor integrated circuit on one semiconductor substrate by a known semiconductor manufacturing technique.

The single chip microcomputer 1 has a ground level terminal Vss, a power supply voltage level terminal Vcc, and other dedicated control terminals as power supply terminals.
Reset terminal RES, standby terminal STBY, mode control terminal MODE, clock input terminals EXTAL, XT
Have AL. They are external terminals. The single-chip microcomputer 1 operates in synchronization with system clocks φ1 and φ2 generated by the clock oscillator 9 based on a crystal oscillator (not shown) connected to the clock input terminals EXTAL and XTAL. Alternatively, an external clock may be input to the EXTAL terminal. One cycle of the system clocks φ1 and φ2 is called one state. The system clocks φ1 and φ2 are non-overlapping two-phase clocks, and φ2 is a clock that is substantially inverted or phase-shifted by 180 ° with respect to φ1.

The above functional blocks are interconnected by an internal bus. The internal bus includes an address bus / data bus, a read signal, a write signal, a bus size signal, and a control bus including system clocks φ1 and φ2. The internal address bus is
IAB, PAB exist, IDB, and internal data bus
There is a PDB. CPU2 and ROM for IAB and IDB
5, RAM 6, bus controller 4, input / output port IO
It is connected to a part of P1 to IOP9. The PAB and PDB are connected to the bus controller 4, the timer 7, the SCI 8, and the input / output ports IOP1-9. IAB, PAB, IDB
The PDB and PDB are respectively interfaced with the bus controller 4. Although not particularly limited, PAB and PDB are exclusively used for register access in the functional block to which they are connected.

The input / output ports IOP1 to IOP9 are also used for input / output of external bus signals and input / output signals of the input / output circuit. The functions of these are selected and used according to the operation mode or software settings. The I / O ports IOP1 to IOP3 are also used as address bus outputs, the I / O ports IOP4 and IOP5 are also used as data bus I / O, and the I / O ports IOP6 and IOP7 are also used as bus control signals. The external address and the external data are respectively connected to the IAB and IDB via buffer circuits (not shown) included in these input / output ports. PAB, PD
B is used for reading / writing the internal registers such as the input / output port and the bus controller 4, and has no direct relationship with the external bus.

Both the internal bus and the external bus have a 16-bit bus width, and read / write of byte size (8 bits) and word size (16 bits) is performed. The external bus may have a width of 8 bits.

The bus control signals include area selection signals CS0 * to CS7 *, read signals RD *, write signals HWR *, LWR *, column address strobe signal C, which will be described later.
AS *, wait signal WAIT *, ready signal READ
There is Y etc.

When a reset signal is applied to the reset terminal RES, the operation mode given by the mode control terminal MODE is fetched, and the single chip microcomputer (hereinafter also simply referred to as microcomputer) 1 is reset. The operation mode is not particularly limited, but the internal ROM 5 is enabled / disabled and the address space is set to 16
Mbyte or 1Mbyte, the initial value of the data bus width is 8
Bit or 16 bits. The mode control terminal MODE has a plurality of terminals as necessary, and the operation mode is determined by the combination of the input states to these terminals.

When the built-in ROM 5 is invalidated, the external address is validated, and the address corresponding to the ROM 5 becomes the external address. The built-in ROM 5 is a mask ROM, a PROM (programmable ROM), or the like. Since the contents of the mask ROM are written in the manufacturing process of the semiconductor integrated circuit, it takes a considerably long time from the user's program creation to the acquisition of the microcomputer. Moreover, rewriting cannot be performed. The PROM can be programmed by the user, but cannot be rewritten while it is installed in the system. Alternatively, the storage capacity of the ROM 5 that can be built in the microcomputer is RO
It is not as large as M alone, and the user cannot always store all desired program scales in the built-in ROM 5. Therefore, it is conceivable to provide an external ROM for storing the program separately from the microcomputer without using the built-in ROM. By exchanging the external ROM for storing the program with the microcomputer mounted in the system, it is possible to shorten the time from program creation to obtaining the system and change the system specifications. Hereinafter, the case where the program ROM is provided outside without using the built-in ROM will be described.

When the reset state is released, the CPU 2
The start address is read, and reset exception handling is performed to start reading an instruction from this start address. It is assumed that the start address is stored in an area starting from address 0 although it is not particularly limited.
After that, the CPU 2 sequentially executes the instructions from the start address.

The DMAC 3 transfers data under the control of the CPU 2. The CPU 2 and the DMAC 3 mutually perform read / write operations using the internal bus and the external bus. The bus controller 4 arbitrates which of the CPU 2 and the DMAC 3 operates.

The bus controller 4 is the CPU 2 or DM
A bus cycle is constructed in response to the operation of AC3. That is, a bus cycle is formed based on the address, read signal, write signal, and bus size signal output from the CPU 2 or the DMAC 3. For example, when the CPU 2 outputs an address corresponding to the RAM 6 to the internal address bus IAB, the bus cycle is set to 1 state, and read / write is performed in 1 state regardless of the byte / word size. When the CPU 2 outputs addresses corresponding to the timer 7, SCI8, and input / output ports IOP1 to IOP9 to the internal address bus IAB, the bus cycle is set to 3 states, and the contents of the internal address bus IAB are output to the internal address bus PAB. The read / write operation is performed in three states regardless of the byte / word size. This control is performed by the bus controller 4.

FIG. 2 shows an example of the address map of the microcomputer 1. 16 address spaces in total
The address space is divided into 8 areas of 2 M bytes each. Area selection signals CS0 * to CS7 * corresponding to these areas are output. For example, when the area 0 is accessed, the area selection signal CS0 * becomes active. The area selection signal is a signal that is used as a chip selection signal for the circuit to which it is input.

The access method for each area is as follows: 5 registers of 8 bits each included in the bus controller 4, BSWCR, ASTCR, WSCRA-B, MPX.
Specified by CR and CMDCR. Each bit of each register controls the area of the corresponding number. These correspondences are shown in the figure. For example, area 0 is BSWCR, ASTCR, WSCRA-B (WSC
RA and WSCRB), MPXCR, and CMDCR are controlled by bit 0 of each. These registers are the CPU
Read / write is always possible from 2. Register BSW
The initial value of CR is determined by the operation mode. That is,
If the initial value of the data bus width is 8 bits, H'FF, 1
If it is 6 bits, it is initialized to H'00. Register A
The initial value of STCR and WSCRA-B is H'FF,
The initial values of the registers MPXCR and CMDCR are H'00.

The register BSWCR specifies the bus width of each area. A bus width of 8 or 16 bits is selected.
A 16-bit bus is selected when the corresponding bit is cleared to "0", and an 8-bit bus is selected when set to "1".

The registers ASTCR and WSCRA-
B designates the number of bus cycles in each area. The number of bus cycles is selected from 2, 3, 4, 5, and 6 states. When the corresponding bit of the register ASTCR is cleared to "0", 2-state access is performed, and when it is set to "1", the number of states designated by the register WSCRA-B is obtained. Register WSCRA-B sets the number of wait states.
Set the corresponding bits of register WSCRA-B to "
When it is cleared to 0, there is no wait state (3 state access). When the corresponding bit of the register WSCRA is cleared to “0” and the corresponding bit of the register WSCRB is set to “1”, 1 state wait (4
State access), the corresponding bit of the register WSCRA is set to "1" and the corresponding bit of the register WSCRB is cleared to "0", the state becomes 2-state wait (5-state access).
When all the corresponding bits of AB are set to "1", 3-state wait (6-state access) is performed. The weight inserted by the register WSCRA-B is called a programmable weight and is distinguished from the external weight designated from the outside of the microcomputer.

Register MPXCR specifies the address multiplex. This is valid when the bus cycle is 3 states or more. For example, 16-bit 4M-bit DRA
When M is connected, the row address (logical address A18-A10) is first output to the address output A9-A1 of the microcomputer, and then the column address (logical address A9-A1) is output. At this time, the waveform of the area selection signal is changed at the same time, and the RAS * (row address strobe) signal is activated after the row address is output. Row address setup / hold is secured. Further, after the column address is output, the CAS * (column address strobe) signal is activated from another terminal.

The register CMDCR specifies an area for automatically generating a command cycle. In the area where the corresponding bit of the register CMDCR is set to "1", the CP
When U2 or DMAC3 makes a predetermined access, a bus command cycle is automatically inserted. For example, CP
U2 is the MOV. B #DATA, R0L MOV. When an instruction "BR0L, @WADR" is executed and a data DATA write cycle for the address WADR is executed, the address WADR corresponds to the area in which the corresponding bit of the register CMDCR is set to "1". Then, for example, a write cycle for a command CMD for instructing a write operation to the flash memory is automatically activated and inserted, and then a bus cycle for a write operation for the data DATA to the address WADR is performed. It will be started. here,
When writing a command, if the chip selection signal for the target circuit such as a flash memory is directly supplied to the circuit as an area selection signal,
The address output to the outside during command writing has no substantial meaning. In the case of this example, for convenience, the same address as the address of the next data write is output.
RAM 6, timer 7, SCI 8, input / output port I
Although the built-in memories such as OP1 to IOP9 and peripheral functions are included in the area 7, they are fixed to their own bus widths and bus cycle numbers.

FIG. 3 and FIG. 4 show other register configurations for controlling the bus. The register WCMD has an 8-bit structure and stores data which is a command to be output prior to the above write cycle. Register C
DAT0 and CDAT1 each have an 8-bit structure,
Data that becomes a command to be output prior to the above-mentioned write cycle is stored. CDAT0 is the first command and CDAT1 is the second command. That is, when the required command is 2 bytes, the registers CDAT0 and CDAT1 are used. As an example of the 2-byte command, there can be mentioned commands H'20 and H, B0 for block erasing shown in FIG. The registers BADR0 to BADR3 each have a 16-bit configuration and store address information.
WCMD, CDAT0 to CDAT1, BADR0 above
Each register of ~ BADR3 is always readable / writable by the CPU 2, and its initial value is H'00.

The register CNTL has an 8-bit structure,
Conditions for adding a command bus cycle are set. Bits BE0 to BE3 are block erasing condition bits for the external flash memory, and bit POL is a condition bit for polling. Bit RE out of it
including. The bit RE can always be read / written by the CPU 2, but the bits BE0 to BE3 and the bit POL can only write "1", and are automatically cleared to "0" when a predetermined operation is completed. . Bits 4 and 5 are reserved bits, and when read, "0" is read and write is invalid.

The initial value of the register CNTL is H'00. When the bit RE is set to "1", the input to the READY terminal of the microcomputer becomes valid. In this state, when the bit POL is set to "1" by the CPU 2, a polling read cycle is automatically inserted to the outside following the bus cycle. At this time, the RE of the microcomputer 1 described later will be described.
A busy signal input from the flash memory to the ADY terminal is recognized as a wait signal. For example, when the external flash memory is in the internal operation and outputs a busy signal, that is, when the external flash memory is in the internal operation, the microcomputer 1 waits until the internal operation is completed. During that time, the polling read cycle is automatically continued.

During the internal operation of the flash memory, if there is any other content to be processed by the microcomputer 1, the RDY / BUSY * signal output from the flash memory (ready at high level, busy at low level)
As an interrupt input of the microcomputer 1, this rising edge may be detected to generate an interrupt. That is, the microcomputer 1 instructs the RDY / BU after writing or erasing the flash memory.
The end of the operation is detected by an interrupt due to the rising edge of the SY * signal. Therefore, during that time, the microcomputer does not have to constantly monitor the end of the operation of the flash memory, which reduces the load on the operation control of the flash memory. When the bit RE is cleared to "0", the input of the READY terminal becomes invalid, and the corresponding terminal can be used as an input / output port.

Any one of the bits BE0 to BE3 is set to "1".
If set to, the command write cycle for block erase to the external flash memory is started following the bus cycle. The command has the contents stored in the registers CDAT0 and CDATA1 in advance. Block erase is instructed by a 2-byte command. At this time, the block address to be erased is the register B
The address is designated by ADR0 to BADR3.
For example, if the block size of the flash memory is 512 bytes, 4 blocks can be simultaneously designated as addresses. Therefore, 2 kbytes can be continuously erased.

The registers BADR0 to BADR3 each have 16 bits, and the lower 1 bit is ignored. The lower 8 bits of these 16 bits are set to H'00 to specify the erase block address. This has 16 address spaces
Corresponds to being M bytes. Therefore, register BA
When H'0123 is set in DR0, the start address of the erase block is H'012200. At this time, the register CMD corresponding to the area including this address
The bit of CR shall be set to "1". If H'20 is stored in the register CDAT0 and H'B0 is stored in the register CDAT1 and the bit BE0 is set to "1", two write cycles are executed for the address H'012200, and the first data is written. Is H'2
The 0th and 2nd data becomes H'B0, and the 146th block of the flash memory is erased.

When chip erasing or continuous block erasing is performed, the command data set in CDAT0 and CDATA1 may be changed to data corresponding to chip erasing or continuous block erasing. In addition, the registers CDAT0,
If the command data set in CDATA1 is changed to data equivalent to page write, and a bus command is issued and then write cycles are sequentially performed, page write can be performed using the register CNTL. When using a 16-bit bus, the same command data is output to the upper 8 bits and the lower 8 bits.

As described above, the write operation for the flash memory, the block erasing, the polling, etc., in which the operation instruction is given by the command, can be performed while reducing the load on the CPU 2. The write operation for the flash memory can be performed in the same way as when the DMAC 3 starts the bus cycle as in the case of the CPU 2.

The read operation for the flash memory can be performed randomly. That is, according to FIG. 26, the read operation is instructed by the command H'00, but when the read operation is instructed by the command, the flash memory can be read at any time unless another operation mode is instructed thereafter. To be For example, upon power-on reset or exceptional processing, the microcomputer 1 unconditionally writes a command H'00 for instructing a read operation to the flash memory. The information stored in the flash memory is, for example, constant data or tuning information to be rewritten, in addition to the operation program exclusively used for reading. If the constant data and the tuning information are rewritten by exception processing in the system to which the microcomputer 1 is applied, the read operation to the flash memory can be performed at any time.

FIG. 5 shows an example of a system using the single chip microcomputer 1 described above. The system shown in the figure is a printer control system, although not particularly limited, and includes a single-chip microcomputer 1, a flash memory 10 for storing programs and tuning information of the single-chip microcomputer 1, a DRAM (buffer) for a data buffer. RA
11), a mask ROM (referred to as CGROM) 12 for character generation, an SRAM (output buffer) 13 for temporarily storing print data, a Centronics interface circuit 14 interfaced with a host processor (not shown), and a print head drive. The circuit 15 is provided, and these are connected via the external bus 16 of the single-chip microcomputer 1. The Centronics interface circuit 14 and the print head driving circuit 15 are composed of the same semiconductor integrated circuit, for example, a gate array (G / A), and the other circuits are respectively composed of separate semiconductor integrated circuit chips. Further, although not shown, the SCI 8 of the microcomputer 1 is connected to the host processor and includes a line feed motor, a carriage return motor, etc. of the printer controlled by the output of the timer 7 of the microcomputer 1.

The single-chip microcomputer 1 operates based on the program stored in the flash memory 10. For example, based on such a program,
Data sent from the host processor is sent to the buffer RA via the Centronics interface circuit 14.
It is transferred to M11. The data transferred to the buffer RAM 11 is referred to by the CGROM 12,
Converted to font data. The font data is stored in the output buffer RAM 13. After that, the single-chip microcomputer 1 outputs a pulse using the timer 7, and drives a carriage return motor (not shown). The print head is moved by the rotation of the carriage return motor. The font data is transferred from the output buffer RAM 13 to the print head drive circuit 15 in accordance with the movement of the print head. For the data transfer from the Centronics interface circuit 14 to the buffer RAM 11 and the data transfer from the output buffer 13 to the print head drive circuit 15, the D of the single chip microcomputer 1 is incorporated.
MAC3 can be used. Flash memory 10
The system can be finely adjusted by rewriting the tuning information stored in. Further, the operation program stored in the flash memory 10 may be modified by version upgrade or use change. Rewriting to the flash memory 10 can be efficiently performed by the above-mentioned automatic insertion of the command cycle or the additional function of the single-chip microcomputer.

For example, in the system of FIG. 5, the flash memory 10 is set to area 0, the CGROM 12 is set to area 4, the buffer RAM 11 is set to area 5, the output buffer 13 is set to area 6, and the Centronics interface circuit 14 and the print head drive circuit 15 are set to area 7. . Area 0 is 16-bit bus, 3 states, command valid, area 4 is 16-bit bus, 3 state, area 5 is 16-bit bus, 3 states, address multiplex, area 6 is 16-bit bus, 2 The area 7 has an 8-bit bus and 3 states, and the programmable wait is not inserted in any area. At this time, the register settings are BSWCR = B'10000000, ASTCR = B'10110001, WSCRA = B'00000000, WSCRB = B'00000000, MPXCR = B'0010000, and CMDCR = B'00000001.

FIG. 6 shows an example of the connection state by the external bus 16 in the system of FIG. G in the figure
/ A is a gate array which constitutes the Centronics interface circuit 14 and the print head drive circuit 15. The flash memory 10 is 16 Mbits described in "Hitachi IC Memory 2" pp305-321 issued by Hitachi, Ltd. in September 1993, and the mask ROM 12 is "Hitachi IC Memory 2" pp681 issued by Hitachi, Ltd. in September 1993.
16M bit described in -687, DRAM 11 is 1
4M bits described in "Hitachi IC Memory 3" pp432-455, published by Hitachi, Ltd., September 993. There are two SRAMs 13 each having 4 Mbits described in "Hitachi IC Memory 1" pp470-477 issued by Hitachi, Ltd. in September 1993.

The address is the flash memory 10, DRA
M11, mask ROM12, SRAM13, G / A1
Input to all 4,15. However, the number of bits corresponding to each capacity is input. For example, since the flash memory 10 has a capacity of 1 M words (16 M bits), the address is 20 bits. Since the single-chip microcomputer 1 has an address in bytes and the flash memory 10 has an address in words, the least significant bit of the address output by the microcomputer 1 is ignored and the address of the microcomputer 1 is halved. The address is supplied to the flash memory 10. That is, the address terminal A2 of the microcomputer 1
0 to A1 are address terminals A19 of the flash memory 10.
~ A0. One of the SRAMs 13 has an even address and the other has an odd address, and the address terminals A19 to A1 of the microcomputer are connected to the address terminals A18 to A0 of the SRAM 13.

The upper parts of the data bus D15 to D8 are the flash memory 10, the DRAM 11, the mask ROM 12 and the SR.
It is connected to all of AM (even address) 13 and G / A 14, 15. The lower bits D7 to D0 of the data bus are the flash memory 10, the DRAM 11, the mask ROM 12, and the SRA.
It is connected to M (odd address) 13. Output terminal CS0
* (The symbol * means that the active level of the signal to which it is attached is low level, and the horizontal bar line above the signal name is attached instead of the symbol * in the drawing) Is connected to the flash memory 10, the output terminal CS4 * is connected to the mask ROM 12, and the output terminal CS6 * is connected to each chip selection signal input terminal CS * of the SRAM 13. Output terminal C
S5 * is connected to the row address strobe signal input terminal RAS * of the DRAM 11. The output terminal CS7 is G
/ A14, 15 chip select signal input terminal CS *. The above CS0 *, CS4 *, CS5 *, CS6
* And CS7 * are output terminals for the area selection signal.

The output terminal RD * of the read signal is connected to the input terminal OE * of the output enable signal of the flash memory 10, the mask ROM 12, and the SRAM 13,
It is also connected to the G / A input terminal OE *. The upper byte write signal output terminal HWR * is connected to the upper write enable signal input terminal UW * of the flash memory 10 and the DRAM 11, the write enable signal input terminal WE * of the SRAM (even address) 13, and also to the G / A. It is also connected to the write enable signal input terminal WE *.
The write signal output terminal LWR * of the lower byte is the flash memory 10, the lower write enable signal input terminal LW terminal of the DRAM 11, the SRAM (odd address) 13
Is connected to the write enable signal input terminal WE *.
The column address strobe signal output terminal CAS * of the microcomputer 1 is connected to the column address strobe signal input terminal CAS * and the output enable signal input terminal OE * of the DRAM 11. Furthermore, the output terminal R of the ready / busy signal of the flash memory 10
DY / BUSY # is connected to the input terminal READY of the microcomputer 1. The symbols of the above-mentioned various terminals are also used as the signs of the input or output signal names of the corresponding terminals in the following description.

FIGS. 7 to 15 show the registers BSWCR, ASTCR, WSCRA, and the registers in the system of FIG.
The timing of a typical bus cycle in the setting state of WSCRB, MPXCR, and CMDCR, for example, the timing of word data access is shown. Note that at the timings shown therein, word data access is limited to 2-byte data starting from an even address. Although not particularly limited, the upper bits D15 to D8 of the data bus are used for the 8-bit bus. All bus control signals are negative logic.

(1) 16-bit bus in area 0, 3-state access Bus cycle timings for read and write operations in this case are shown in FIGS. 7 and 8. Area 0
In the case of 16-bit bus and 3-state access, read / write is performed by using the upper part of the data bus for the data of even addresses and the lower part of the data bus for the data of odd addresses. The microcomputer 1 reads the read signal RD * / the upper write signal HW corresponding to the read / write of the even address.
The read signal RD * / lower write signal LWR * is activated in response to the read / write of the odd address.
The read is controlled by 16 bits at a time. Writes are controlled in bytes. The address and CS0 * signal output are valid during the bus cycle. Read signal RD * is T1
Falling of clock φ in state (clock φ
2 rise), the active level is set in synchronization with T
It is returned to inactive in synchronization with the fall of clock φ in three states (the rise of clock φ2). The high-order write signal HWR * and the low-order write signal LWR * output from the microcomputer 1 rise in the clock φ in the T2 state (rise in the clock φ1).
To the active level in synchronism with, and is returned to inactive in synchronization with the fall of the clock φ in the T3 state (the rise of the clock φ2). At this time,
The read operation is performed as it is, but when a write operation is instructed, a command write cycle for the flash memory is inserted. In the write cycle of the command, the CPU 2 or D is connected to the external address bus.
The address output by the bus master such as MAC3 is output. The data at that time is the command data held in the WCMD register. Address and control signal outputs are the same as above.

(2) 16-bit bus in area 4, 3-state access The bus cycle timings of the read and write operations in this case are shown in FIGS. 7 and 9. Area 4
In the 16-bit bus and 3-state access, the data of even addresses is read using the upper part of the data bus and the data of odd addresses is read using the lower part of the data bus. The read is controlled by 16 bits at a time. The address and output signal CS4 * indicates a valid value during the bus cycle. The read signal RD * is set to the active level in synchronization with the falling of the clock φ in the T1 state (the rising of the clock φ2), and is returned to the inactive level in synchronization with the falling of the clock φ in the T3 state.

(3) 16-bit bus in area 5, 3-state access, address multiplex access Bus cycle timings of read and write operations in this case are shown in FIGS. In this case, the row address in the T1 state and the column address in the T2 and T3 states are output to A10 to A1, respectively. The CS5 *, RD *, HWR *, and LWR * output signals are set to the active level in synchronization with the falling edge of the clock φ in the T1 state, and are returned to the inactive level in synchronization with the falling edge of the clock φ in the T3 state. Be done. Column address strobe signal C
AS * is set to the active level in synchronization with the falling edge of the clock φ in the T2 state, and is returned to the inactive level in synchronization with the falling edge of the clock φ in the T3 state. Similarly to the above, the data of even addresses is read and written using the upper part of the data bus and the data of odd addresses is used lower part of the data bus. The HWR * is activated in correspondence with the write of the even address, and the LWR * is activated in correspondence with the write of the odd address.

(4) 16-bit bus in area 6 and 2-state access Bus cycle timings of read and write operations in this case are shown in FIGS. 12 and 13. In this case, read / write is performed using the upper part of the data bus for the data of even addresses and the lower part of the data bus for the data of odd addresses. The output signal of RD * or HWR * corresponds to the read / write of even addresses and the read / write of odd addresses.
The output signal of RD * or LWR * is activated in response to the write. The read is controlled by 16 bits at a time. Writes are controlled in bytes. The address and output signal CS6 * is made active during the bus cycle. Each output signal of RD *, HWR *, and LWR * is T1
It is set to the active level in synchronization with the falling edge of the clock φ in the state, and is returned to the inactive level in synchronization with the falling edge of the clock φ in the T3 state.

(5) 8-bit bus in area 7 and 3-state access Bus cycle timings of read and write operations in this case are shown in FIGS. 14 and 15. In this case, reading / writing is performed using the upper part of the data bus. That is, the RD * or HWR * signal is selectively activated. Address and output signal C
S7 * is activated during the bus cycle. The output signal RD is set to the active level in synchronization with the falling edge of the clock φ in the T1 state, and is returned to inactive in synchronization with the falling edge of the clock φ in the T3 state. The output signal HWR * is set to the active level in synchronization with the rising edge of the clock φ in the T2 state, and is returned to inactive in synchronization with the falling edge of the clock φ in the T3 state. As shown in FIGS. 14 and 15, when a bus master such as the CPU 2 or the DMAC 3 accesses word data,
Byte access is performed twice in the order of even address and odd address.

FIG. 16 is a block diagram showing an example of the bus controller 4 which generates various bus access timings as described above. The bus controller 4 includes an address decoding circuit 40, a control circuit 41, a bus right arbitration circuit 42, a selection circuit 43, a timing control circuit 44, a control register 45, a command register 46, and an address register 4.
It consists of 7. The control register 45 is the register B described above.
SWCR, ASTCR, WSCRA-B, MPXCR,
Includes CMDCR and CNTL. The command register 46 includes the registers WCMD and CDAT0 to CDATA1. The address register 47 is the register BADR0 above.
Includes BADR3. In FIG. 16, the functions included in the input / output port are the input / output buffer and the multiplexers 47, 4
8 and the output buffer are typically shown. 47
Is an address multiplexer, and 48 is a data multiplexer.

The bus right arbitration circuit 42 includes the CPU 2 or D.
Controls which of the MAC3s uses the bus. For example, when a data transfer start factor occurs in the DMAC3, DM
When the AC bus request signal is set to an active level such as 1 level, the bus arbitration circuit 42 permits the DMAC 3 to use the bus at a predetermined timing instructed by the timing control circuit 44 and sets the DMAC bus right permission signal to 1 The active level such as the level is returned to the DMAC3. At other times, the CPU 2 has the bus right. When the CPU 2 regains the bus right when the DMAC 3 has the bus right, the CPU bus right request signal and the CPU bus right grant signal are used in the same manner as above. Based on this control, CPU2 and DM
The AC3 can exclusively use the address / data bus.

The selection circuit 43 selects a bus control signal output from the CPU 2 and the DMAC 3, such as a read signal RD, a write signal HWR, LWR, and bus size information, based on an instruction from the bus right arbitration circuit 42, and performs timing control. It is given to the circuit 44. That is, if the DMAC bus right grant signal is at 1 level, the bus control signal from the DMAC 3 is given to the timing control circuit 44, and otherwise the bus control signal from the CPU 2 is given to the timing control circuit 44.
Whichever of CPU2 and DMAC3 has the bus right,
The internal operation of the bus controller 4 is basically the same.

The address decoding circuit 40 decodes which area the address output by the CPU 2 or the DMAC 3 to the address bus IAB corresponds to. The decoding result is output as an area selection signal from a predetermined terminal via the output buffer. The control circuit 41 determines which area is selected by the output of the address decoding circuit 40, and determines which bit of the control register 45 should be referred to. The determination result is given as an instruction to the timing control circuit 44. The timing control circuit 44 generates a bus cycle based on the output of the control circuit 41 and outputs internal and external bus control signals. It also gives instruction on the operation timing of the input / output buffer, multiplexer, and bus arbitration circuit. Further, when the bus cycle generated by it is a command write bus cycle or the like, the control signal DAT is issued as necessary.
The command register 46 is selected by ASEL or CDATSEL.

The address multiplexer 47 included in the output buffer selects a row address and a column address, and selects the contents of the address bus IAB and the registers BADR0 to BADR3 included in the address register 47 according to the instruction of the timing control circuit 44. . The data multiplexer 48 included in the input / output buffer inputs / outputs data on the data bus IDB, or registers WCMD and CDAT0 to CDAT included in the command register 46.
Select whether to output the contents of DATA1. Note that the timing control circuit 44 is related to the generation of the write cycle.
Only byte write is valid for the bit bus, and only word write is valid for the 16 bit bus.

FIG. 17 shows a concrete first circuit example of the timing control circuit 44. FIG. 18 shows an example of the operation timing chart of FIG. In the circuit example of FIG. 17, in order to make the contents easy to understand, the logical configuration of the block erasing and polling functions is omitted. That is, this is an example of a circuit focusing on a configuration for automatically generating and inserting a bus cycle for command writing by write access to a predetermined area. Also,
This circuit example is shown in positive logic.

The RD + WR signal is the CPU2 or DMAC3.
Is an internal signal for bus activation of a read operation or a write operation by and is an output of the selection circuit 43. BUS8A, ST
3A and CMDA are signals obtained by decoding the address in the address decoding circuit 40, and the area and BSW
It is a signal generated from the corresponding bits of the CR, ASTCR, and CMDCR registers. That is, the signal BUS8
In A, ST3A, and CMDA, the area to be accessed at that time is an 8-bit bus area, a 3-state access area (the total number of states is more than that according to the number of wait states), and a command valid area. Shown by high level. The internal signal WR is used as a bus activation internal signal for the write operation. WORD is a signal obtained by decoding an address in the address decoding circuit 40, and is set to a high level in the case of word access. W
Both the R and WORD signals are outputs of the selection circuit 43.

The bus cycle is basically 2 states and 3
If the number of states is equal to or more than the state, the wait state is inserted after the T1 state (when the wait state is inserted, the wait state is referred to as T2 state and the next state is referred to as T3 state for convenience). In the 3-state access area, the wait request signal wait includes a wait request by the registers WSCRA and WSCRB and a wait request by the wait signal WAIT supplied to the external terminal. That is, the wait signal WAIT from the outside is passed through the flip-flops FF7 to FF9, which are D-type latches in three stages in series, and the wait request signal wai.
t. Regarding the programmable wait by the registers WSCRA and WSCRB, the register WSCR concerned
Wait request signal wai according to the contents of A and WSCRB
t is generated. In any weight request,
The signal ST3A is set to high level during the wait period. However, the signal ST3A is not set to a high level at all unless the register ASTCR specifies that it is not a 2-state access area.

The clock φ1B is the wait request signal wa.
It is a logical sum signal of it and clock φ1, and clock φ
2B is a logical product signal of the inverted signal of the wait request signal wait and the clock φ2. During the wait, the clock φ1B is fixed at the high level and the clock φ2B is fixed at the low level, and the clock inputs of the flip-flops FF1 to FF4 do not change. Therefore, the state is retained. Signal DATAS
EL is a signal for selecting whether to output the command held by the register WCMD or the content of the data bus IDB.

The selection circuit SEL outputs the outputs of the flip-flops FF1, FF2, FF3 which are serially connected three stages of D-type latch circuit circuits to which the bus activation signal RD + WR is supplied to the first stage via the OR gate OR1. Input it. A φ1 and φ2 synchronizing circuit is also included. This selection circuit SE
L outputs the above various bus timing signals. That is, area selection signals CS0 * to CS7 *, address strobe signal AS *, read signal RD *, write signal HW.
R *, LWR *, column address strobe signal CAS
Generates and outputs the * output waveform and address multiplex timing. For example, the waveform of the read signal RD * is an inverted signal of the output signal of the second flip-flop FF2. Set the corresponding bit of register MPXCR to "
When set to "1", the area selection signal is the inverted signal of the logical product signal of the address decode result and the flip-flop FF2.

Bus activation signal RD + WR is applied to timing control circuit 44 in synchronization with system clocks φ1 and φ2 before the start of the bus cycle. The flip-flop FF1 outputs a signal in synchronization with the rising of the clock φ1B in the T1 state. Similarly, each of the flip-flops FF2, FF3, FF4 latches and outputs the input signal in synchronization with the rising of the clock φ2B in the T1 state, the rising of the clock φ1B in the T2 state, and the rising of the clock φ2B in the T3 state. The latch operation of the flip-flop FF4 is synchronized with the rising edge of the clock φ2 in the T3 state after releasing the wait. For example, in the case of word access to the 8-bit bus area (BUS8
A and RD are high level), or in the case of a data access cycle following the command cycle (flip-flop FF6 is in the set state), the output of FF4 is set to high level at the end of the first bus cycle. , This output is fed back to the flip-flop FF1 via the OR gate OR1 and is latched in the FF1.
That is, the activation of the second bus cycle is instructed.

Whether the first bus cycle or the second bus cycle is the RS (reset set) type fifth or sixth
Of the flip-flops FF5 and FF6. The flip-flop FF5 is set to the set state for the first bus cycle and reset for the second bus cycle. The set state of the flip-flop FF5 is substantially meaningful when the signal WORD is set to a high level meaning word access and the flip-flop FF10 is latching it, and the word access is This is when the operation is performed via the 8-bit bus (the signal BUS8A is at the high level). The flip-flop FF6 is used in the command cycle, that is, when writing to the command valid area (WR and CMDA).
Is at a high level) and the signal BRKAK is at a low level as an inactive state, the state is set, and the high level output of the flip-flop FF4 causes a reset state.

The signal BRKAK is a signal indicating that the CPU 1 is in a break state, in consideration of the case where the microcomputer 1 is used for emulation. When the signal BRKAK is set to a high level as an active level, the command cycle insertion is prohibited, and the address space of the microcomputer is switched from the address space for the target program to the control space for evaluation after the break. If so, a write cycle is automatically inserted, eliminating the risk of undesired rewriting of data. Details of this point will be described later.

As described above, the timing control circuit 4 of FIG.
4 is a write to the command valid area when the word access is performed by the 8-bit bus first (WR
And CMDA are high level) in the case of a command cycle instructed when the signal BRKAK is inactive,
A predetermined bus cycle is continuously generated twice.

FIG. 19 shows a concrete second circuit example of the timing control circuit 44. In this example circuit,
In order to make the contents easier to understand, FIG. 17 shows only the logical configuration of the omitted block erasing and polling functions. In addition, this circuit example also has a positive logic. FIG. 19
In FIG. 17, the same signals and circuit elements as in FIG. 17 are assigned the same reference numerals and detailed explanations thereof will be omitted.

The timing control circuit 44 shown in the figure exclusively shows a structure for automatically activating a predetermined bus cycle by writing to the register CNTL by the CPU 2. The signal REGCLR is a signal for clearing the contents of the register CNTL to end the automatically generated bus cycle. According to this example, the number of bus cycles automatically generated for block erasing of the flash memory is two, and the number of bus cycles automatically generated for polling is one. The high level output of the flip-flop FF4 is used as the activation signal of the second cycle, and the flip-flop CFF4 controls the signal RECGLR to the high level at the timing when the automatically generated bus cycle ends. The flip-flop CFF5 and the NAND gate NAND1 are set to 1 in two command write cycles for block erase.
FF4 is used in the cycle, CFF4 is used in the second cycle, and only CFF4 is used in the bus cycle for polling.

Timing control circuit 44 shown in FIG.
Is supplied with a POL bit set signal SETPOL from the register CNTL. The SETPOL signal is validated in synchronization with the rising edge of the clock φ2 in the T3 state of the write cycle for the register CNTL. However, the POL bit set signal is valid only when the RE bit is set to "1". This S
The logical product signal of the ETPOL signal and the RE signal is supplied to the logical sum gate OR2 as a start signal, which is latched by the flip-flop FF1 and the polling read cycle is started to the outside following the internal register write cycle. To be done. Polling read cycle is P
Recognized by setting the OL bit. The address at this time is not particularly limited, but register B
The address is designated by ADR0.

At this time, the signal RDY / BUSY * (ready input signal READ from the flash memory input to the ready terminal READY of the microcomputer 1)
Y) is supplied to the flip-flop FF7 as a signal equivalent to the wait signal WAIT from the outside. That is, when the flash memory is in the internal operation, the ready input signal READY is set to the inactive low level. Therefore, until the internal operation of the flash memory is terminated and the input signal READY is set to the active high level, The computer 1 is placed in a wait state.
That is, during that time, the levels of the clocks φ1B and φ2B are fixed and the latch operation of the flip-flop FF3 is suppressed. When the input signal READY is set to the active level and the wait is released, the bus cycle is ended after the T3 state of the polling read cycle.
Upon termination, the signal REGCLR is set to high level.

Further, the timing control circuit 44 is supplied with the logical sum signal SETBE of the set signals of BE0 to BE3 from the register CNTL. This signal SET
BE becomes valid in synchronization with the rising of the clock φ2 in the T3 state of the write cycle of the register CNTL. This signal SETBE is also used as a bus activation signal and supplied to the OR gate OR2. Further flip-flop C
It is input to the reset terminal of FF5. Also, BE0-B
E3 bit OR signal BEOR signal is NAND gate N
It is supplied to one input of AND1. The flip-flop CFF5 is connected to the other input of the NAND gate NAND1.
An inverted signal of the output of is supplied. The output of the NAND gate NAND1 is set to the low level in the state where the block erase of the flash memory is instructed by writing to the register CNTL. Therefore, at the end timing of the first cycle in the command write cycle for block erase, the output of the flip-flop FF4 is set to the high level, and the second command write bus cycle is started for the flip-flop FF1. Is instructed. At the same time, the flip-flop CFF5 is set to enable the data input operation of the flip-flop CFF4 this time. Therefore, at the end timing of the second command write cycle, the flip-flop CFF4 latches the output of FF3 and outputs the signal REGCL.
The automatic generation of the bus cycle is ended by setting R to the high level.

FIG. 20 shows the operation timing relating to the automatic generation of the command write cycle for the block erase. A command write cycle is started following the write cycle of the CPU 2 for the register CNTL by using the signal SETBE as a start signal. That is, the flip-flop FF1 latches the activation signal, and the flip-flop CFF5 is reset. The address at this time is the register BADR0 to BAD.
The address is designated by R3. Register BAD
R0 to BADR3 are specified by BE0 to BE0 of the register CNTL.
It is performed according to the state of the BE3 bit.

In the first command cycle, CFF5 is in the reset state and BEOR is at the high level, and FF4 is synchronized with the rise of the clock φ2 in the T3 state.
Is set. The second command cycle is activated by using this as an activation signal, the FF1 latches the activation signal, and the CFF5 is set.

In the second command cycle, CFF5 is in the set state, and FF4 is controlled to the state in which data cannot be input. On the other hand, the CFF4 becomes ready for data input, and the register clear signal REGCLR is set to the high level in synchronization with the rising of the clock φ2 in the T3 state. As a result, the BE0 to BE3 bits that are the trigger factors of the command write cycle this time are cleared.

At this time, the command written in the flash memory has the contents of the registers CDAT0 and CDATA1, and the output of the registers CDAT0 and CDATA1 is selected by the signal CDATSEL output from the CFF5. Register CDAT0 when CFF5 is in reset state
, The contents of the CDAT1 register are output when CFF5 is in the set state. The internal bus is a 16-bit bus, and the same command data is output to upper 8 bits and lower 8 bits. In 8-bit bus mode,
The lower 8 bits of data are not output to the external data bus. As for the BE0 to BE3 bits and the POL bit, only one arbitrary bit can be set to "1", and it is prohibited to set a plurality of bits to "1" at the same time.

The specific structure of the timing control circuit 44 has been separately described in FIGS. 17 and 19, but in practice
The timing circuit is realized by combining the circuits of FIGS. 17 and 19. In the case of combining, for example, the flip-flops FF1, FF2, FF3, FF7, FF8, FF9 and the clock system are made common, and other circuit elements are separately provided to perform path selection according to the operation mode, or other It can be easily realized by a known method of guiding a signal from a circuit element to a common circuit element through an OR circuit.

The flash memory can be connected to the outside of a single-chip microcomputer as a semiconductor integrated circuit device or can be incorporated therein. For example, like the cell-based IC, the system shown in FIG. 5 can be used as one semiconductor integrated circuit to reduce the size of the system. In this case, the above register that can set an arbitrary value can be eliminated. That is, it is possible for a user of such a cell-based IC to fixedly determine which memory is connected to which area, and it is not necessary to arbitrarily set the register. For example BSWC
R, ASRCR, WSCRA-B, MPXCR, CMD
CR and the like can be fixed. The outputs of these registers may be fixed to either "0" or "1". Besides fixing the value of the register, those signal lines may be pulled up or pulled down.

In order to speed up the system, it is necessary to improve the processing speed of the CPU 2. In order to improve the processing speed of the CPU 2, it is necessary to improve the instruction fetch speed. Since the flash memory is slower than the SRAM, the improvement of the instruction fetch speed is limited. On the other hand, the SRAM cannot hold the stored contents when the system is stopped. Therefore, it is conceivable that the program stored in the flash memory operates immediately after the reset, the program is transferred to the SRAM, and the program on the SRAM is executed after the transfer is completed. Further, the vector address used in the exceptional processing of the microcomputer may be fixed in the address space of the CPU 2 such as area 0. Therefore, even if the program on the SRAM is being executed, the program on the flash memory must be executed each time an exception process such as an interrupt occurs. In particular, interrupt processing and the like often require a reduction in response time, which is a constraint for speeding up the system. Therefore, when accessing the area 0 in which the flash memory is arranged, the area selection signal CS0 * can be set to the non-selected state, and instead, the area selection signal CS2 * of the area 2 in which the SRAM is arranged can be set to the selected state. It is a good idea. A case where this control is performed using the control bit CS0C will be described.

FIG. 21 shows a circuit configuration example for the above CS control. The control bit CS0C is composed of a flip-flop circuit FF20 to which one bit of the data bus is connected. After reset, the control bit CS0C is cleared to "0". When a write is performed to the address where the control bit CS0C exists, the internal data bus PD
The contents of B0 are stored. The contents of the address (IAB) output from the bus master such as the CPU 2 and the DMAC 3 are decoded, and ICS0 to ICS7 are generated. Since there is no direct relationship for areas other than areas 0 and 2, ICS
Other than 0 and ICS2, illustration is omitted in FIG.

When the control bit CS0C is cleared to "0", when the area 0 is accessed, that is, when ICS0 is the high level which is the selection level and ICS2 is the low level which is the non-selection level, the area selection signal CS0 is The selection level is set to high level, and CS2 is set to non-selection level, low level. When the control bit CS0C is set to "1", the area 0 is accessed, that is, the ICS
When 0 is the high level which is the selection level and ICS2 is the low level which is the non-selection level, conversely to the above, the area selection signal CS0 is the low level which is the non-selection level, C
S2 is set to the high level which is the selection level. Regardless of the state of the control bit CS0C, during area 2 access, CS0 is inactive and CS2 is active.
The area selection signal CS0 * output to the outside is the signal C described above.
The area selection signal CS2 *, which is an inverted signal of S0 and is output to the outside, is an inverted signal of the signal CS2.

FIG. 22 shows a modification of the printer system to which the speed-up method described with reference to FIG. 21 is applied. Figure 2
3 shows an address map in the system of FIG. The system of FIG. 22 has SRAM 17 added to that of FIG. The SRAM 17 is a memory that is used by receiving the programs and tuning information stored in the flash memory 10, and is arranged in the area 2. The same circuit blocks as those in FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted.

In such a system, immediately after reset, the operation is first started by the program on the flash memory 10. Area 0 has 3 states and area 2 has 2 states. The contents of the flash memory 10 in area 0 are copied to the SRAM 17 in area 2. For example, the DMAC3 may be used. After that, the control bit CS0C is set to "1". When the address of area 0 is accessed by CPU 1 or DMAC 3, CS
0 * is set to inactive, and CS2 * is set to active level. The access attribute is the same as that of area 2. That is, the logical address of the CPU 1 is area 0, while the physical address is area 2. Since the contents of area 0 and area 2 are common, there is no malfunction even if the physical address is changed. Low speed flash memory 1
Store programs etc. in 0 and operate at high speed with SRA
The data processing speed can be increased by transferring a program or the like to M17. For example, since the program fetch can be speeded up by 1.5 times, the overall processing speed is also speeded up accordingly.

Due to the characteristics of the flash memory 10, it is conceivable to accumulate information peculiar to the system user. In this case, at the end of the system operation, the SRAM 17
Contents are transferred to the flash memory 10. D to this
MAC3 can be used. For example, the input signal READY of the microcomputer 1 can be used as the transfer request signal of the DMAC 3. That is, when the contents of the SRAM 17 are written back to the flash memory 10, the change to the active level (ready state) of the signal RDY / BUSY *, which means the end of writing by the flash memory 10 in word or page units, is used as the input signal READY. Each time the microcomputer 1 receives the signal, the signal is DMed.
It is processed as a transfer request signal of AC3. In order to use the signal as a transfer request signal, the port may be set so that the port receiving the signal READY is guided to the DMAC 3 as the transfer request signal of the DMAC 3.

Such processing is possible because the bus controller 4 is accessed by the CPU 2 and DMAC.
Flash memory 1 for any access
This is because a command write bus cycle for 0 can be automatically added. Note that the transfer to the SRAM 17 described above can be applied to other than the flash memory 10. For example, only the initialization operation program may be stored in the mask ROM 12, and the other programs may be transferred from the secondary storage such as a floppy disk to the SRAM 17 in the area 4. Also, as a high-speed memory,
Besides SRAM, it may be one such as a synchronous DRAM.

FIG. 24 shows a block diagram when the microcomputer 1 is applied to an emulation microcomputer. The emulation microcomputer 50 includes a microcomputer part 5
1 and an emulation interface 52 including a buffer circuit (not shown) and the like, which are formed on one semiconductor substrate by a known semiconductor manufacturing technique.

The emulation microcomputer 50 has a user interface 53 for transmitting and receiving signals to and from the application system of the single chip microcomputer corresponding to the microcomputer portion 51.
The emulation interface 52 transmits / receives signals to / from an emulator (not shown) or a system development device. In FIG. 24, circuit blocks having the same functions as those of the single-chip microcomputer shown in FIG. 1 are designated by the same reference numerals. In FIG. 24, the user interface 5
3 includes the input / output circuits PIO1 to PIO9 shown in FIG. The circuit block indicated by I / O in FIG. 24 includes the timer 7 and SCI8 in FIG.

As an emulation bus, IAB is used.
And IDB are input and output through the emulation interface 52. The buses PAB and PDB are emulation interfaces 52 as emulation buses.
Is not directly connected to. As a result, the number of terminals of the emulation microcomputer can be reduced, which contributes to the miniaturization of the package size and the miniaturization of the emulator.

A status signal CMDCYC indicating the automatically added command cycle is output to an emulator or the like via the emulation interface 52. In the automatically added command cycle, the CMDCYC signal is set to the active level. CMD
The CYC signal is, for example, DATASEL, BEOR, P
It can be a logical sum signal of the OL signals. others,
The emulation interface 52 includes a break request terminal BRK and the like. When the CPU 2 accepts the break interrupt, the break acknowledge signal BR
KAK is set to the active level, and a transition is made to the control program execution state for emulation. When the return instruction is executed, the BRKAK signal becomes inactive and transitions to the user program execution state. During the break mode, automatic bus cycle insertion (bus command) such as command write cycle is prohibited. The emulator memory and the user flash memory can be arranged at the same address, the emulator memory can be used in the break mode, and the user flash memory can be used in the user mode. It is desirable that the emulator memory be configured with a RAM according to the purpose of storing the program to be debugged. It is possible to prevent the contents of the RAM from being destroyed by issuing a write cycle that is a bus command to this RAM.

FIG. 25 is a block diagram showing an example of the emulator. The connector unit 60 is attached to the application system (user system) 61 instead of the single-chip microcomputer. The emulation microcomputer 50 inputs and outputs signals to and from the application system 61 via the connector section 60 and the interface cable 62.

The emulation microcomputer 50 uses the emulation interface 52.
Is used to connect to the emulation bus 63. The emulation bus 63 has status signals, control signals, data,
And various signal lines such as addresses. By using the emulation bus 63, the emulation microcomputer 50 outputs information according to the internal states of the application system 61 and the emulation microcomputer 50. Various control signals are input. An emulation mode terminal (not shown) of the emulation microcomputer 50 is fixed to the power supply level, and the emulation mode is set inside the emulation microcomputer 50.

The emulation bus 63 is not particularly limited, but an emulation memory 64 such as a RAM for substituting the memory built in the application system 61 or the target microcomputer.
The control state of the emulation microcomputer 50 and the state of the emulation bus 63 are monitored, and when the state reaches a preset state, a break interrupt as the emulator dedicated interrupt is requested and C
A break control circuit 65 for stopping the execution of the user program by the PU 2 and shifting to a control program execution state for emulation (break);
A real-time trace circuit 66 for sequentially storing addresses and data, and further control information given to the emulation bus 63 based on a signal indicating a read operation or a write operation of the CPU 2 or a signal indicating an instruction read operation.
Etc. are connected. The real-time trace circuit successively stores the signal CMDCYC.

The emulation memory 64, break control circuit 65, and real-time trace circuit 66 are also connected to the control bus 67, and the control bus 67
The control processor 68 is controlled via the. The control bus 67 is, though not particularly limited, via the host interface 69, a system development device 70 such as a personal computer.
Connected to. For example, the program input from the system development device 70 is transferred to the emulation memory 64, and the CPU 2 reads the program to be arranged on the external program ROM or, if the ROM is built in, the program to be arranged on the internal ROM. Then, the program on the emulation memory 64 is read. In addition, break conditions, real-time trace conditions, etc. can be given from the system development device 70. The system development device 70 can display the result traced by the real-time trace circuit 66 on a display screen such as a CRT or liquid crystal.

On the emulator system, a normal bus cycle and an automatically added bus cycle can be explicitly distinguished. That is, the state of the CMDCYC signal obtained corresponding to the bus cycle can be displayed or distinguished.
Alternatively, it is possible to selectively display only the normal bus cycle or the automatically added bus cycle. This is done by the processing of the system development device 70.
Whether to display the corresponding bus cycle may be selected according to the accumulated information of the CMDCYC signal. By deleting the automatically added bus cycle, the execution of the program and the bus cycle correspond to each other, so that the debugging of the program can be facilitated.
In addition, by displaying only the bus cycle that is automatically added, the execution state of the bus command can be easily traced. The emulator can interpret the bus command to facilitate displaying the contents of the command as well as the bus information. The CMDCYC signal is at the active level, and the data at that time is H'2.
If 0 and H'B0, "block erase" appears on the display screen.
Is displayed. As a result, the program can be debugged easily without the user sequentially confirming the content of the command.

Here, the flash memory 10 will be schematically described. The flash memory 10 includes a memory array in which flash memory cells (hereinafter also simply referred to as memory cells) configured by insulated gate field effect transistors having a two-layer gate structure are arranged in a matrix. Although not particularly limited, the control gates of the flash memory cells are connected to the corresponding word lines (not shown), the drains of the flash memory cells are connected to the corresponding data lines (not shown), and the sources of the flash memory cells are for each memory block. Connected to common source line.

The operation of writing information to the memory cell is realized, for example, by applying a high voltage to the control gate and the drain and injecting electrons from the drain side to the floating gate by avalanche injection. Due to this write operation, the threshold voltage of the flash memory cell seen from the control gate becomes higher than that of the erased memory cell in which the write operation is not performed.

On the other hand, the erase operation is realized, for example, by applying a high voltage to the source and extracting electrons from the floating gate to the source side by the tunnel phenomenon. The erase operation lowers the threshold voltage of the memory transistor viewed from its control gate. The threshold voltage of the memory cell transistor is set to a positive voltage level in both the write and erase states. That is, the threshold voltage in the written state is raised and the threshold voltage in the erased state is lowered with respect to the word line selection level applied from the word line to the control gate. By having such a relationship between both threshold voltages and the word line selection level, it is possible to configure a memory cell with one transistor without employing a selection transistor.

In the read operation, the voltage applied to the drain and the control gate is relatively low so that weak writing to the flash memory cell, that is, unwanted carrier injection to the floating gate is not performed. Limited to low values. For example, a low voltage of about 1 V is applied to the drain and a low voltage of about 5 V is applied to the control gate. By detecting the magnitude of the channel current flowing through the memory cell transistor by these applied voltages, the logical values "0" and "1" of the information stored in the memory cell can be determined.

According to the above embodiment, the following operational effects are obtained. (1) A bus controller 4 for selectively controlling a memory or the like connected to a part or all of the address space of the microcomputer 1 having an external bus, and
The internal register CMDCR makes it possible to specify the flash memory 10 that requires command writing, and the flash memory 10 can be designated in an area on the selected address space.
When a bus master such as the CPU 2 or the DMAC 3 performs a read / write, the timing control circuit 44 of the bus controller 4 inserts a write cycle for a command corresponding to the read / write, thereby minimizing the load on software. The flash memory 10 can be connected as long as possible. (2) Register the bus width and the number of bus cycles in the register BSWCR,
By setting ASTCR, WSCRA, and WSCRB, various memories can be directly connected without using an external circuit. (3) By automatically inserting a command during a read / write operation, a data transfer control can be performed between a bus master such as the DMAC3 that only transfers data and between the flash memory 10 and SRAM. . (4) The memory can be directly connected by outputting the area selection signal. By changing the output condition of the area selection signal as described with reference to FIG. 21, it is possible to rearrange the memory and the like in the address space of the CPU 2 without changing the physical system. . As a result, when the contents stored in the low-speed nonvolatile memory are transferred to the high-speed volatile memory to operate, it can be dealt with only by changing the output condition of the area selection signal. (5) In the emulation microcomputer, a signal C indicating the bus cycle performed by the bus master or the bus cycle automatically inserted by the bus controller
The debug efficiency can be improved by outputting MDCYC and by the emulator distinguishing and displaying them. (6) In the emulation microcomputer, when the external memory is not used (break mode), the emulation memory can be protected by automatically prohibiting the bus controller from inserting a bus cycle.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Yes.

For example, as the bus master, CPU, D
In addition to the MAC, it may be a data transfer controller or a digital signal processor (DSP). Any data processing device that reads / writes a memory using the bus may be used. It may have three or more bus masters. Any number of data processing devices can be built in one semiconductor integrated circuit. The present invention is DM
It goes without saying that it can be applied to AC and DSP itself. The external circuit whose operation is instructed by the command is not limited to the flash memory. If it's memory,
For example, it may be a synchronous DRAM.

The details of the bus specifications can be changed in various ways.
For example, in addition to selecting the bus width of 8/16 bits, 16 /
It may be 32 bits, or 8/16/32 bits may be selectable. If you use a 32-bit bus,
Four 8-bit commands may be output in parallel.
The command may be output only for a predetermined bus by determining the address and the bus size.

A manual reset and a power-on reset may be provided at the time of reset, and the content of the register of the bus controller may be held at the time of manual reset. Further, the reset command may be output prior to the operation of the CPU.

The specific circuit configuration of the bus control circuit can be changed in various ways. The configuration of the control register and the like can be changed in various ways. The register for storing the command can be written by the CPU at any time, or may be fixed. The area dividing method can also be set in units of 128 kbytes or the like. The size of the area may be continuously changeable. The attribute may not be set for all the divided areas. When the address space is expanded, it is desirable to prevent each area from becoming large. It is not desirable to be larger than the available memory capacity. When the number of divided areas is large or the terminals of the microcomputer are not large enough, it is not necessary to output the area selection signal for all areas. There is no restriction on other functional blocks of the single-chip microcomputer.

In the above description, the case where the invention made by the present inventor is mainly applied to the single-chip microcomputer which is the field of application which is the background of the invention has been described, but the present invention is not limited to this and other data processing. The present invention can be applied to a device, a control system, and an emulator, and at least the present invention can be applied to a data processing device that can use an external bus.

[0117]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, when a predetermined address space allocated to an external circuit such as a flash memory is accessed, a first command for writing a command instructing the operation of the external circuit is accessed prior to the access. A write cycle can be automatically inserted. As a result, it is possible to eliminate the processing for writing a command each time writing in a byte or page unit to the flash memory and the program description for defining the command.

Predetermined bits of the built-in control register are CPU
When operated by, the second command write cycle for writing a command instructing the operation of the external circuit can be automatically inserted next to the operation. As a result, even when command writing is required for a plurality of times, such as a block erase write to a flash memory, the instruction description may specify writing to the control register. The size can be reduced.

The external read cycle for polling control can be started and maintained by the operation of a predetermined bit of the built-in control register by the CPU.
In terms of generation of external bus cycles, improvement of data processing efficiency and reduction of program size can be realized.

In consideration of emulation, the data processing device outputs a signal indicating the bus cycle performed by the bus master or the bus cycle automatically inserted by the bus controller, whereby the debugging efficiency can be improved.

In consideration of emulation, the emulation memory can be protected by prohibiting the automatic insertion of the bus cycle in the break mode.

Even if the bus master means is a direct memory access controller, the direct memory access controller can also use such a command format flash memory as a data transfer source or a data transfer destination by automatically inserting the command write cycle. it can.

The interface with the flash memory whose operation is instructed by the command can be simplified and the usability can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of a single-chip microcomputer that is an embodiment of a data processing device according to the present invention.

2 is an explanatory diagram of an example of an address map of the microcomputer of FIG.

FIG. 3 is an explanatory diagram of a bus control register.

FIG. 4 is an explanatory diagram of other bus control registers.

5 is a block diagram showing an example of a printer system using the single-chip microcomputer shown in FIG.

6 is an explanatory diagram showing an example of a connection state by an external bus 16 in the system of FIG.

FIG. 7: 16-bit bus in area 0, read operation in 3-state access and 16-bit bus in area 4, 3
It is an example bus cycle timing diagram of a read in state access.

FIG. 8 is a bus cycle timing diagram showing an example of a write operation in a 16-bit bus in area 0 and 3-state access.

FIG. 9 is a bus cycle timing diagram showing an example of a write operation in a 16-bit bus in area 4 and 3-state access.

FIG. 10 is a bus cycle timing chart showing an example of a read operation in a 16-bit bus in area 5, 3-state access, and address multiplex access.

11 is a bus cycle timing diagram showing an example of a write operation in a 16-bit bus in area 5, 3-state access, and address multiplex access. FIG.

FIG. 12 is a bus cycle timing chart showing an example of a read operation in a 16-bit bus in area 6 and 2-state access.

FIG. 13 is a bus cycle timing chart showing an example of a write operation in a 16-bit bus in area 6 and 2-state access.

FIG. 14 is a bus cycle timing chart showing an example of a read operation in an 8-bit bus in area 7 and 3-state access.

FIG. 15 is a bus cycle timing chart showing an example of a write operation in an 8-bit bus in area 7 and 3-state access.

FIG. 16 is a block diagram of an example of a bus controller.

FIG. 17 is a circuit diagram showing an example of a timing control circuit included in the bus controller.

18 is an operation timing chart of an example of the circuit of FIG.

FIG. 19 is a circuit diagram showing another example of each timing control circuit included in the bus controller.

20 is an example operation timing chart regarding automatic generation of a command write cycle for block erasing in the circuit of FIG. 19;

FIG. 21 is an example circuit diagram for CS control.

22 is a block diagram of an example of a printer system to which the circuit of FIG. 21 is applied.

23 is an explanatory diagram of an example of an address map in the system of FIG.

FIG. 24 is a block diagram of an example of an emulation microcomputer.

FIG. 25 is a block diagram of an example of an emulator.

FIG. 26 is an explanatory diagram of an example of a command of the flash memory.

[Explanation of symbols]

1 Single-chip microcomputer 2 CPU 3 DMAC 4 Bus controller BSWCR Register for specifying bus width of each area ASTCR, WSCRA, WSCRB Register for specifying bus cycle of each area MPXCR Register for specifying address of each area CMDCR Command cycle Register for automatically generating area WCMD, CDATA0, CDATA1 Register for command storage BADR0-BADR3 Register for address storage CNTL Command bus cycle insertion condition specification register 10 Flash memory 11 DRAM 12 Mask ROM 13, 17 SRAM 44 Timing control circuit 50 Emulation microcomputer

Claims (12)

[Claims] 1. A data processing device having a built-in bus master unit capable of using an external bus and connectable to an external circuit whose operation is instructed by a command, wherein the data processing unit responds to an instruction to access an external predetermined address space by the bus master unit. Then, prior to the generation of the external bus access cycle corresponding to the access instruction, a first command write cycle for writing a command for instructing the operation of the external circuit to the predetermined address space is generated. A data processing device comprising a bus control means. 2. The bus control means is an address space designating means for designating an address space in which the first command write cycle is to be activated, and an access address by the bus master means is an address designated by the address space designating means. Determination means for determining whether or not it is included in the space,
2. The data processing apparatus according to claim 1, further comprising: timing control means for generating the first command write cycle based on the detection result of the determination means. 3. The data processing according to claim 2, wherein the bus control means includes a command storage means for rewritably holding a command to be written in the first command write cycle. apparatus. 4. A bus master means includes a CPU, and the bus control means includes a control register means and a CPU.
Further includes timing control means for generating a second command write cycle for writing predetermined command data in a predetermined address space by manipulating the first bit of the control register means. The data processing device according to claim 1, wherein the data processing device is a data processing device. 5. The data processing apparatus according to claim 4, wherein the bus control means further comprises address storage means for holding an address to be output in the second command write cycle. 6. The external read cycle for the bus control means to perform polling control for waiting for a change in a signal input from a predetermined external terminal by the CPU operating the second bit of the control register means. 6. The data processing device according to claim 4, wherein the data processing device is for generating. 7. The emulation interface according to claim 1, further comprising an emulation interface for outputting an identification signal indicating whether or not the bus cycle to the outside is the command write cycle. The data processing device according to item 1. 8. The data according to claim 7, wherein the CPU outputs a control signal for prohibiting generation of the first command cycle by the bus control means on the basis of a predetermined external interrupt. Processing equipment. 9. A direct memory access controller as the bus master means, further comprising a single-chip microcomputer formed on one semiconductor substrate, as claimed in any one of claims 1 to 8. The described data processing device. 10. A data processing system comprising the data processing device according to claim 9 and a flash memory as an external circuit directly connected to the data processing device. 11. A data processing apparatus according to claim 8, and an emulator coupled to an emulation interface included in the data processing apparatus, wherein the emulator has a trace memory and a break control circuit.
The trace memory inputs and accumulates the identification signal together with the bus information of the data processing device, and the break control circuit breaks as the interrupt signal when the control state by the data processing device reaches a preset state. A data processing system which outputs a signal to the data processing device. 12. A data processing device having a built-in bus master unit capable of using an external bus and connectable to a flash memory whose operation is instructed by a command, wherein the bus master unit gives an instruction to access an external predetermined address space. In response, bus control means for generating a command write cycle for writing a command for instructing the operation of the flash memory to the predetermined address space prior to generation of an external bus access cycle corresponding to the access instruction. And a data input device for externally inputting a signal indicating an internal operation state of the flash memory instructed by the command write, the data processing device being formed on one semiconductor substrate.