JPH07295852A - Logical emulator compilation method - Google Patents

Abstract

PURPOSE:To eliminate the trial and error and to reduce the logical compiling manhour by performing a compiling job with use of the information added for correction of the design data and in response to this design data. CONSTITUTION:A gate allotment function 120 performs the allotment of the elements registered in an element library 124 of a logical compiling system based on the design data stored in a design data file 110 serving as the input of the compiling system and also on the information added to the design data. The result or the logical generation processing 100 is outputted to a gate allotment/logical division result design data file 140. These output data are processed by the arrangement/wiring processing 150 and finally the data to be loaded into a programmable logic device are produced and output to a programmable logic device data file 160. In such a way, the design data are changed by the logical compiling system based on the added information and the data are generated for a logic circuit data which can operate on the programmable logic device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic emulation system for performing logic verification of a digital logic system on a computer, and more particularly to a logic compiling method for generating logic circuit data to be given to a programmable logic device.

[0002]

2. Description of the Related Art Conventionally, as the logic scale of a computer and the number of man-hours for logic verification increase, it is required to improve the efficiency of logic verification of a computer. As one of the solutions to this, recently, a logic verification method using a logic emulator has been proposed. In this method, a netlist of a logic circuit is read into a computer, logic compilation is performed, and design data for a programmable logic device is generated. This data is loaded into a programmable logic device, and the verification target logic circuit is realized as hardware on the programmable logic device. Test data is applied to the realized logic circuit to verify the correctness of the logic. Since the logic circuit is realized as hardware, it is possible to execute the test at a sufficiently high speed as compared with the conventional software simulator. Regarding the logic emulation method including the logic compilation method, for example,
"Electronic hardware system emulation device" described in Japanese Patent Laid-Open No. 2-245831 and US patent US
No. 5,036,473 `` Method of electronically reconfigurable log circuit
ic circuit) ”.

[0003]

As described above, the logic verification method using the logic emulator is sufficiently faster than the conventional software simulator when executing the test. However, it takes time to perform the preparation process of the logic verification method. That is, logic compilation, which generates design data to load into programmable logic devices, requires more processing time than conventional approaches. This is because the software simulator has only to realize the logic circuit on a computer by software, whereas the logic emulator has to realize the logic circuit to be verified as hardware, which is programmable by loading the design data. This is because the logical device causes the following restrictions. That is, even if the design data that can be handled by the conventional software simulator is directly input to the logic emulator and realized on the programmable logic device, it is difficult to operate it. For example, Field Programmable Gate Array (FPGA), which is one of programmable logic devices.
Has a smaller capacity than the conventional gate array. Therefore, it is necessary to realize the logic by using a plurality of FPGAs, so that the logical division occurs. Since a signal line extending between chips is required due to the logical division, a delay time is increased in propagating these signal lines, which causes a malfunction.
In order to prevent such malfunctions, conventionally, the result of logic compilation or the result of emulation execution is checked,
The design data was changed. However, when changing the settings, there was a lot of trial and error, and there was a lot of rework when they did not work, and it took a considerable amount of time to correct to an appropriate value. As a result, the number of logical compilation steps has been increased. The object of the present invention is to solve such conventional problems,
To provide a logical emulator logical compiling method that can prevent a rework when logical compiling is performed and does not operate without increasing delay time even if logical division occurs and can reduce the number of logical compiling steps. is there.

[0004]

In order to achieve the above object, a logic compiling method for a logic emulator according to the present invention comprises: (a) inputting design data of a digital logic circuit;
In a logic compiling system realized on a memory of a computer for generating data to be given to a programmable logic device, compiling using design information and additional information for modifying the design data. According to this, the logic compilation system changes the design data based on the additional information to generate logic circuit data operable on a programmable logic device. Further, (b) by giving the logical compilation system designation information as additional information to the logic compilation system, the logic compilation system may change the design data and divide the logic based on the division location designation information. It has a feature. In addition, (c) by providing the logic compiling system with information designating that a plurality of logic circuits having a possibility of logic change are arranged in the same divided portion as the additional information, the logic compiling system outputs the design data. It is also characterized in that it is changed and logical division is performed based on the designation information. Further, (d) as additional information, information designating a signal for shortening the delay time of the signal line is given to the logic compilation system, so that the logic compilation system changes the design data, and the logic compilation system changes the design data based on the designation information. Another feature is that the delay time of the signal line is shortened. Further, (e) by giving information for designating the range of the delay time of the signal line to the logic compilation system as additional information, the logic compilation system changes the design data, and based on the designation information, the signal line of the signal line is changed. Another feature is that the delay time is set within the specified range. Also,
(F) It is also characterized in that, as additional information, information designating an observation signal is given to the logic compilation system, the logic compilation system changes design data, and an observation signal line is extracted from the position of the designation information. . (G) By adding the additional information to the same file by adding it to the design data and reading the design data and the additional information from the file into the logical compiling system, the logical compiling system designs based on the additional information. It also features changing the data. Furthermore, (h) the additional information is made a file separate from the design data, and the design data and the additional information are read into the logical compilation system from both files, so that the logical compilation system creates the design data based on the additional information. It also features changing.

[0005]

In the present invention, additional information is provided to the logic compilation system separately from the design data, the know-how of the user of the logic emulation system is reflected through the additional information, and the system changes the design data based on this additional information. To generate logic circuit data operable on the programmable logic device. That is, the logic compiling system uses the additional information to replace the three-state element net with a multiplexer, convert it into a logic circuit with a reduced delay time, perform logic division based on the designation of the logic division position, and further perform logic division. Logic elements that can be changed are arranged in the same division logic, and the signal line of the observation signal is drawn out. As a result, the logic compilation system can generate a logic circuit operable on a programmable logic device. Then, by setting the additional information, which is the know-how of the user, in advance, this is input to the logic compiling system together with the design data, so trial and error operations are eliminated, and there is a rework in the case where the logic compiling does not work. Can be prevented. As a result, the number of logical compilation steps can be shortened.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a software configuration diagram of a logic compilation system showing an embodiment of the present invention. The logic compiling system of the present invention mainly comprises a logic generation process 100 and a placement / wiring process 150. Further logic generation processing 100
Is composed of a gate allocation function 120 and a logical division function 130. The gate allocation function 120 is based on the design data of the design data file 110 which is an input of the logic compilation system and the additional information to the design data which will be described later in detail, and stores the elements registered in the element library 124 included in the logic compilation system. Make an assignment. The additional information for the design data newly provided in the present invention is the design data file 110.
In some cases, it is described together with the design data, and in other cases, it is described in the additional information file 111 separately from the design data. In FIG. 1, the latter case is shown.

The gate allocation function 120 is provided with three types of programs, that is, a multiplexer replacement program 121, a delay time reduction program 122, and a signal observation program 123 in order to realize the logic specified by the additional information. The function of each program 121, 122, 123 will be described in detail later. On the other hand, the logical partitioning function 130 partitions the design data whose element allocation is completed according to the capacity of programmable hardware. The logical partitioning function 130 has a program 131 for arranging logics that can be logically changed in the same cluster, and a logical partitioning program 132 based on the partitioning net designation in order to realize the logic designated by the additional information. Here, the same cluster refers to a group of a plurality of logic elements in the same group obtained by division. Logic generation processing 10
The result of 0 is output to the gate allocation / logical division result design data file 140. The output data is processed by the placement / wiring processing 150 to finally create data to be loaded into the programmable logic device and output to the programmable logic device data file 160.

Next, the logic corresponding to the example of the additional information will be described with reference to FIGS. 2 to 7. 2 to 6 are examples in which the design data and the additional information are described in the same file. Further, FIG. 7 is an example in which the additional information is described in the additional information file 111 separately from the design data. Figure 2
FIG. 3 is a diagram showing an example of additional information for multiplexer replacement in FIG. 1. FIG. 2A shows an example in which additional information for multiplexer replacement is added to the netlist. The design data stored in the design data file 110 has a netlist format shown in FIG. The netlist of FIG. 2 (a) corresponds to the logic circuit of FIG. 2 (b). In FIG. 2A, the description blocks A200 and end201 represent that the logic described between them is one block and forms a hierarchy. The description of G1: Tri-state buffer; 210 represents that the element G1 is a buffer of three-state elements. Description 1 = a,
2 = b, 3 = X; 211 means that the signal a is connected to the terminal 1 of the element G1, the signal b is connected to the terminal 2, and the signal X is connected to the terminal 3, respectively. The description attri (MUX); is an example of additional information, and specifies that the element G1 is replaced as part of the multiplexer. FIG. 2C shows the result of replacing the logic circuit of FIG. 2B with a multiplexer.

FIG. 3 is a diagram showing an example of specifying a logical division position. FIG. 3A is a netlist representation of the logic circuit diagram of FIG. 3B. The description method is the same as that in FIG. When logical division is performed at the broken line 310 in FIG. 3B, attri (cut; Z) 301 and attri (cut;
Z) Specify by 302. FIG. 3C shows a division result based on the division designation. The logic is divided into chip M320 and chip N321. Furthermore, on the signal line of the divided signal Z,
Buffers 322 and 323 for transmitting and receiving signals between chips are inserted. This prevents signal delay. Figure 4
FIG. 6 is a diagram showing an example of designating a logic circuit which is stored in the same division logic and has a possibility of logic change during the logic division of the present invention. The description method of the netlist of FIG. 4A is the same as the description method of FIG. The netlist of FIG. 4 (a) is shown in FIG.
This is a representation of the logic circuit in (b). In FIG. 4 (a), FF1 402 and FF2 403 are added by the description attri (modify: 1) 401.
G1 404 specifies to store in the same division logic. The division result is shown in FIG. FF1 402 and FF2 403 and G1 404
Were stored in the same chip, Chip mod 410. This designation is useful for gathering potentially modifiable logic in one place. That is, since it is difficult to process when the logic element to be changed is separated into various chips, it is desirable to combine the logic elements that may be changed in advance in the same chip. Further, if the logics collected as one are realized on the hardware considering the easiness of signal observation,
The observation signal 411 etc. can be easily extracted. In addition, since the change points of the logic realized on the hardware are concentrated, the logic change is easy.

FIG. 5 is a diagram showing an example of specifying the delay time of the logic circuit according to the present invention. The description method of the netlist of FIG. 5A is the same as the description of FIG. 2A. The netlist in FIG. 5A represents the logic circuit in FIG. 5B. The description attri (mindelay: OUT1-a); 501 in FIG.
Specifies the reduction of the delay time between the output signal OUT1 and the input signal a. Also, the description attri (delay value: 20-30: d-OU
T1); 502 specifies that the delay time between the input signal d and the output signal OUT1 should be between 20 and 30 unit times. The result of processing based on this designation is shown in Fig. 5 (c).
Is. However, in FIG. 5 (c), the delay time between OUT1 522 and d521 is assumed to be 25 unit time. In order to reduce the delay time between the output signal OUT1 522 and the input signal a523,
G2 510 and G3 511 are combined into a composite gate device G2 '52
It has been replaced by 0. On the other hand, since the delay time between the output signals OUT1 522 and d521 is 25 unit time, which is within the specified constraint condition, the logic circuit does not change between FIG. 5 (b) and FIG. 5 (c). Absent. FIG. 6 is a diagram showing an example of designation of observation signals in the present invention. The description method of the netlist of FIG. 6A is the same as that of FIG. 2A. The netlist of FIG. 6 (a) expresses the logic circuit of FIG. 6 (b). Figure 6 (a)
The description attri (observe: Y) 601 specifies that the signal Y610 is to be observed. The result of processing based on the designation of FIG. 6 (a) is shown in FIG. 6 (c). In order to observe the state of the signal Y610, a signal line is pulled out of the chip Chip M620. At this time, the output buffer 621 is inserted.

FIG. 7 is a diagram showing a description example when the additional information of the design data according to the present invention is read as an additional information file. Here, the case where the same additional information as in the cases of FIGS. 2 to 6 is set as an additional information file different from the design data file is shown. The description mux; 701 is
Indicates that the specified element is replaced with a multiplexer.
The description block A: G1, G2, G3, G4; 711 specifies G1, G2, G3, G4 of block A as elements to be replaced by the multiplexer. Description partition; 720 is a specification regarding logical partitioning. The description cut: block B: Z; 721 specifies that signal Z of block B is to be logically divided. Similarly modify: block C: FF
1, FF2, G1; 722 specifies that FF1, FF2 and G1 are stored in the same division logic. Also, the description delay; 731 is a designation regarding the delay time. Description min delay block D: OUT1-a
732 specifies reduction of the delay time between the output signal OUT1 and the input signal a. Description delay time: block D: 20-30 OUT1-d;
The 733 sets the delay time between the output signal OUT1 and the input signal d to 2
Specifies to fit within 0 to 30 credit hours. The description observe; 741 specifies the observation of the signal and the description b
lock D: Y742 specifies that the signal Y of block D is observed.

FIG. 8 shows details of the logic generation process shown in FIG.
It is the figure shown in the PAD figure. In the logic generation process 100, after the gate allocation function 120 is executed, the logic division function 130 is executed.
The gate allocation function 120 searches the input netlist and replaces the replaceable partial netlist with the library element 124 prepared by the logic compilation system. This replacement process is performed by the netlist element conversion program 810.
Done in. This method is described, for example, in the US patents listed above.
It is described in detail in US Pat. No. 5,036,473. next,
The element once allocated is changed based on the additional information described above, and the netlist is locally converted. The multiplexer allocation program 121 converts the logic shown in FIG. 2B into the logic circuit shown in FIG. In the next delay time reduction program 122, the delay time of the signal line is reduced based on the additional information. This method is described in, for example, Kluwer Academic Publisher (Kluwer Academic P
ublishere) Issued "Field Programmable Gate Array" for details. Also, the delay time of the signal line specified by the additional information is evaluated to see if the delay time falls within the specified range. At the end of the gate allocation function 120 is the signal observation processing program 123. An output terminal and a netlist of an output buffer are added, and the observation signal is drawn to the input / output terminals of the hardware.

After executing the gate allocation function 120, the logical partitioning function 130 is executed. The logical partitioning function 130 executes the cluster creating program 131 and then the logical partitioning execution program 132. Here, the cluster refers to each of a plurality of logics obtained by division. In the cluster creation program 131, the elements designated as logics whose logic may change are placed in the same cluster, the elements are placed in different clusters based on the designation of the split net, and the cost function is applied to the last remaining element. It is arranged in the cluster based on the calculation result of. Here, the cost function is calculated based on the number of nets between clusters after logical division. By using the cost function, logical partitioning with a small number of nets between clusters is possible. The logical partitioning method based on the cost function is described in detail, for example, in the above-mentioned US Pat. No. 5,036,473. Logic generation can be executed by taking the above steps. In the embodiments described so far, the method of using the additional information in the logic generation processing has been described, but the additional information can be used in the layout / wiring processing as well.

[0014]

As described above, according to the present invention,
By using the additional information, a logic circuit operable on a programmable logic device can be realized. In that case, since the know-how possessed by the user of the logic emulation system can be reflected through the additional information, by setting the additional information in advance, it is possible to prevent a rework when the logical compilation is performed and the operation does not occur. It is possible to shorten the logical compilation man-hours.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a logic compilation system showing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a multiplexer replacement designation of a logic circuit according to the present invention.

FIG. 3 is a diagram showing an example of designation of division positions of a logic circuit according to the present invention.

FIG. 4 is a diagram showing designation of a logic circuit having a possibility of changing logic in the same division portion in division of the logic circuit of the present invention.

FIG. 5 is a diagram showing an example of designation of reduction of delay time of a logic circuit in the present invention.

FIG. 6 is a diagram showing an example of designation of observation signals of a logic circuit according to the present invention.

FIG. 7 is a diagram showing an example of designation when reading additional information of a logic circuit as a separate file in the present invention.

FIG. 8 is an example of a PAD diagram of a processing procedure of logic generation processing of the present invention.

[Explanation of symbols]

100 ... Logic generation processing, 110 ... Design data file, 111 ... Additional information file, 120 ... Gate allocation function, 121 ... Multiplexer gate replacement program, 122 ... Logic stage reduction program, 123 ・ ・ ・ Signal observation program, 124 ・ ・ ・ Device library, 130 ・ ・ ・
Logical partitioning function, 131 ... Arrangement program for logic with possibility of logical change in the same cluster, 132 ... Logical partitioning program based on partition net designation, 140 ... Gate allocation / logical partitioning result design data file , 150 ...
・ Placement / wiring processing, 160 ・ ・ ・ Data file for programmable logic device.

Claims (8)

[Claims] 1. A logic compilation system realized on a memory of a computer for inputting design data of a digital logic circuit and generating data to be given to a programmable logic device, together with the design data. , By compiling using the additional information for modifying the design data, the logic compiling system changes the design data based on the additional information to generate logic circuit data operable on a programmable logic device. A logical compiling method of a logical emulator characterized by generating. 2. The logic compiling method for a logic emulator according to claim 1, wherein, as the additional information, logical partitioning position designation information is given to the logical compiling system, whereby the logical compiling system changes design data, A logic compiling method of a logic emulator, characterized in that logic is divided based on designation information of the division position. 3. The logic compiling method for a logic emulator according to claim 1, wherein the additional information is information designating that a plurality of logic circuits having a possibility of logic change are arranged in the same divided portion. A logical compiling method for a logical emulator, characterized in that the logical compiling system changes design data by giving it to a compiling system and logically divides it based on the designation information. 4. The logic compiling method of the logic emulator according to claim 1, wherein, as the additional information, information for designating a signal for shortening a delay time of a signal line is given to a logic compiling system to perform the logic compiling. A logic compiling method of a logic emulator, wherein a system changes design data and shortens a delay time of the signal line based on the designation information. 5. The logic compiling method for a logic emulator according to claim 1, wherein the additional information is information designating a range of delay time of a signal line to the logical compiling system to design the logical compiling system. A logic compiling method for a logic emulator, characterized in that data is changed so that a delay time of the signal line falls within a designated range based on the designated information. 6. The logic compiling method for a logic emulator according to claim 1, wherein, as the additional information, information designating an observation signal is given to the logic compiling system so that the logic compiling system changes design data, A logic compiling method for a logic emulator, characterized in that an observation signal line is extracted from the position of the designated information. 7. The logic compiling method for a logic emulator according to claim 1, wherein the additional information is added to the design data to form the same file, and the design data and the additional information are read from the file into the logical compilation system. Accordingly, the logic compiling system modifies the design data based on the additional information, whereby the logic compiling method of the logic emulator. 8. The logic compiling method for a logic emulator according to claim 1, wherein the additional information is a file separate from the design data, and the design data and the additional information are read from both files into a logical compiling system.
A logic compiling method for a logic emulator, wherein the logic compiling system changes the design data based on the additional information.