JPH07283751A - Radio communication equipment - Google Patents

Abstract

PURPOSE:To provide a radio communication equipment which can improve its transmission/reception performance without increasing the size of its power supply such as a battery, etc., nor complicating its peripheral circuits. CONSTITUTION:A radio communication equipment contains the PLL type oscillation circuits 25, 26 and 29 for synchronization with the transmission/reception frequency. Then the communication equipment is provided with an original frequency signal generating means 30-B which generates an original reference frequency signal to the circuits 25, 26 and 29 as a standard of phase comparison, and a pulse distributing means 30-A which distributes the pulses of the original reference frequency signal to the circuits 25, 26 and 29 respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mainly relates to a wireless communication device used in the field of mobile wireless communication such as a mobile phone and a car phone.

[0002]

2. Description of the Related Art In recent years, with the advancement of advanced information technology, various information communication media have appeared and become popular. Among them, mobile communication, which has excellent immediacy and mobility, has become the most noticed information communication medium. Mobile communication is information communication by radio, such as mobile phones, car phones, radio calls,
It has been widely and steadily spread in various forms such as MCA radio, satellite communication, and personal radio.

By the way, when using radio waves, it is necessary to take a necessary frequency width for each frequency to be used and to further provide an appropriate interval in order to prevent interference with adjacent frequencies. In many systems currently in practical use, the frequency width of 25 KHz or 12.5 KHz is taken. Therefore, in order to set one line, it is necessary to have a frequency width of 25 KHz or 12.5 KHz.

On the other hand, the radio frequency is a limited resource, and the radio frequency (channel) cannot be assigned to the user blindly. Even in the field of analog mobile phones and car phones, which are currently being implemented, it is not possible to provide a satisfactory communication service to an increasing number of subscribers only with the usable 800 MHz band.

Therefore, the development of quasi-microwave as the next main frequency band has been carried out, and high frequency radio technology based on the advanced semiconductor technology and small component manufacturing technology and digital signal processing technology have been largely adopted to use radio waves. Digital mobile phones (using the 1.9 GHz band) and car phones (using the 1.5 GHz band) for improving efficiency have been developed all over the world, and have already been put into practical use in some regions. Even in Japan, PHP (Personal Handy)
An abbreviation for Phone, also called a second-generation cordless phone, which is standardized by "RCR STD-28" issued by the Radio Wave System Development Center) and PDC.
(Personal Digital Celler, which is a digital car phone,
R STD-27 ”) has been developed, and practical services and practical application testing services have already started in some areas.

Next, in the PDC system, TDMA / FDM
A (Time Division Multiple A
ccess / Frequency Division M
The cellular system of "ultimate access" is adopted. In this case, the interval between the transmission frequency and the reception frequency used by the mobile station and the base station is 800 MHz band and 15
In the 00MHz band, 130MHz and 48M respectively
Hz is taken. Also, during a call, it is necessary to investigate (by measuring the electric field strength) the usage of radio waves at a channel frequency other than the channel frequency being used. Furthermore, regarding the transceiver,
It is necessary to maintain high digital modulation accuracy (12.5% or less) and demodulation accuracy with little distortion associated with digital modulation in response to fast switching of transmission / reception frequency (approximately 5 msec or less). It is necessary to have a high-performance oscillator circuit.

[0007] In addition, since the mobile radio telephone performs position registration during standby and continuous communication during movement, one cell (a cell means one base station for one mobile station) is used as necessary. It is the range that can be communicated with) and must switch the wireless communication channel when moving to another cell. Therefore, the transmitter / receiver is required to have high frequency stability after switching, as well as to support high-speed switching of the transmission / reception frequency.

A possible method for obtaining high transmission / reception performance is to provide a frequency synthesizer for determining one transmission frequency in the transmission system circuit and separately determine one reception frequency in the reception system circuit. It is to construct a high frequency circuit in the wireless communication device, which is provided with a frequency synthesizing means and further with an intermediate frequency synthesizing means for determining an intermediate frequency used for transmission and reception.

Therefore, in a conventional radio communication apparatus capable of receiving or transmitting radio waves having many radio frequencies, a PLL is generally used as a frequency synthesizing means for obtaining a target frequency required at the time of transmission and reception. (Ph
an as Locked Loop) synthesizer circuit is used. In a PLL synthesizer circuit, a voltage controlled oscillator (VCO) is used.
The output frequency signal of the d. Oscillator (hereinafter abbreviated as VCO) is divided by the VCO divider to a frequency substantially equal to the original reference frequency signal output from the original reference frequency signal generator, and the divided frequency signal is obtained. And a phase difference between the original reference frequency signal and a phase comparator, and the comparison result is passed through a charge pump or a differential input OP amplifier for current amplification, followed by a loop filter (a low-pass filter, There is a so-called phase control loop for controlling the output frequency of the VCO by converting it into a DC voltage by a lag lead type or an active type) and inputting this into a control terminal of the VCO.

The control direction for this VCO always works so as to eliminate the phase difference or maintain the same phase, and the state for this VCO is called lock. At this time,
Is oscillating at a fixed frequency. By changing the set frequency division ratio of the VCO frequency divider and the output frequency of the reference signal generator, various kinds of frequency signals can be produced.

The frequency of the output signal of the VCO is controlled by a control voltage having a control sensitivity of about 10 MHz per 1V. Further, in the PLL synthesizer circuit, each time the output frequency of the VCO is changed, its output frequency fluctuates and gradually converges to the changed frequency. The signal is not exactly contained in the frequency, and always causes a small fluctuation of the frequency with a certain width. However, although this fluctuation is an undesired operating state, it does not cause any particular problem as long as it is within the allowable range.

FIG. 7 is a block diagram showing a circuit configuration example of a conventional radio communication device. Reference numeral 121 is an antenna for both transmission and reception, 122 is a duplexer, 123 is a transmission circuit, 124 is a modulation circuit, 125 is a transmission PLL synthesizer for supplying a high frequency signal to the transmission circuit 123 for determining a transmission frequency, and 126 is a transmission circuit. An intermediate frequency PLL circuit that supplies a frequency signal for determining an intermediate frequency common to reception to the modulation circuit 124 and the demodulation circuit 128, 127 is a reception circuit, 128 is a demodulation circuit, and 129 is a reception frequency to the reception circuit 127. A receiving PLL synthesizer for supplying a high frequency signal for determining, 130 is a transmitting / receiving PLL synthesizer 125, 129, and an original reference frequency generator for supplying an original reference frequency to the intermediate frequency PLL circuit 126, and 131 is a transmission system circuit. Power switch for transmission system circuit that connects / disconnects power supplied to Power switch reception system circuit for connecting / interrupting the power supply to the circuit,
133 is a power supply device such as a battery, and 134 is a transmission / reception PLL
Synthesizers 125, 129 and intermediate frequency PL
L circuit 126, and further two power switch 131, 132
Is a CPU for controlling the.

In the conventional wireless communication device, all the PLL synthesizer circuits start operating at the same time when the power is turned on, and the receiving system circuit changes the frequency channel to be received momentarily and measures the electric field strength in that channel. (This is an operation called carrier sense.) In addition, when performing location registration, the base station is notified of the frequency channel and the measurement result of the electric field strength on that channel by the transmission operation, if necessary. ing.

FIG. 8 shows the original reference frequency generator 1 shown in FIG.
30 and three frequency synthesizer circuits 125, 12
6 and 129, reference frequency generation circuits 125-A and 1
It is a block diagram which shows the structure of 26-A, 129-A.
As shown in the figure, the original reference frequency generator 130 includes the 12.
It is composed of a crystal oscillator with an 8 MHz setting. Further, reference frequency generation circuits 125-A, 126-A, 129 in the respective frequency synthesizer circuits 125, 126, 129.
-A is composed of a 1/512 frequency divider (DIVDER).

The frequency signal of 12.8 MHz oscillated by the original reference frequency oscillator 130 is 1/51 in each reference frequency generation circuit 125-A, 126-A, 129-A.
The frequency is divided into two, and each becomes a frequency signal of 25 KHz, which is supplied to the phase comparator in each frequency synthesizer circuit. In the figure, 125-B, 126-
B and 129-B are the reference frequency generation circuits 125-A and 12-12 in each PLL synthesizer circuit.
The remaining block configurations except 6-A and 129-A are shown.

FIG. 9 shows a power supply voltage and its current in the conventional wireless communication device shown in FIG. 7, a reference frequency signal in each PLL synthesizer circuit, a consumption current, and a VCO.
Is a timing chart showing the output fluctuation of (I) to (I
It is divided into II) and three cases are shown respectively. 9-1
Is a reference frequency signal in the transmitting PLL synthesizer 125, 9-2 is a reference frequency signal in the intermediate frequency PLL circuit 126, and 9-3 is a receiving PLL synthesizer 129.
The waveform changes of the reference frequency signal are shown respectively. (I)
In the above case, the three reference frequency signals have different phases for each ⅓ cycle (note that one cycle is 0.04 msec in this case), and there is no mutual influence. In the case of (II), the phases of the two reference frequency signals 9-1 and 9-2 are in agreement with each other, and they influence each other. In the case of (III), the signal positions of the three reference frequency signals 9-1, 9-2, and 9-3 overlap with each other in a partially superposed state. Therefore, all three signals influence each other.

The influence of each reference frequency signal is
As shown in the figure, each PLL synthesizer circuit 125, 1
No. 26,129 consumption current 9-4,9-5,9-6, each VCO output frequency variation 9-7,9-8,9-9, power supply voltage 9-A, power supply current 9-B The waveform changes are shown.

[0018]

As described above, in each PLL synthesizer circuit incorporated in the conventional wireless communication device, the frequency of each reference frequency signal is the same,
For each reference frequency signal, generate the original reference frequency signal 1
A common original reference frequency signal generated by 30 is created by individually dividing the frequency in each PLL synthesizer circuit. In that case, the operating phase in the VCO divider that divides the original reference frequency signal into the reference frequency signal does not include any information for determining the operating phase in the control signal for setting the frequency division ratio. The operating phase differences of each VCO divider have not always been fixed in a fixed relationship.

However, the operation phases of the PLL synthesizer circuits may match depending on the timing of power-on and the switching of the channel frequency. In such a case, a plurality of PLL synthesizer circuits are mutually connected through the power source. They can affect each other. In particular,
The load current in each PLL synthesizer circuit is increased with the period of the reference frequency signal, resulting in a drop in the power supply voltage. However, each PLL synthesizer circuit has frequency holding response individually. Therefore, due to the fluctuation of the power supply voltage, the fluctuation of the power supply voltage of the VCO is caused, and the frequency of the output signal of each VCO is greatly changed.

Further, such a fluctuation of the power supply voltage naturally affects the control voltage of each VCO. That is, a noise component is mixed in the control voltage of each VCO due to the fluctuation of the power supply voltage. Specifically, as described above, a switching circuit such as a charge pump is provided between the phase comparator and the loop filter. However, this circuit uses the output of the phase comparator to provide a sufficient loop filter. It has the function of power amplification so that it can be driven. Therefore, when there is a change in the power supply voltage of the switching circuit, a noise component is added to the phase error detection signal that is the output of the phase comparator, which causes a change in the VCO control voltage and changes the output frequency of the VCO. It fluctuates greatly.

In the above-mentioned conventional wireless communication device,
The power supply to each PLL synthesizer circuit 125, 126, 129 is restarted, and at the same time, each PLL operation is reset, and the setting data of each PLL operation is reset to C
An operation to transfer from PU134 is required. However, the operating phase of each PLL synthesizer circuit is not specified by the power-on timing or the transmission / reception control timing, as described above. Therefore, the operating phases of the respective PLL synthesizer circuits should originally be in a completely non-uniform state, but sometimes the operating phases of two or more PLL synthesizer circuits are the same. In such a case, since each PLL synthesizer circuit operates at the cycle of the reference frequency, the peaks of the respective operating currents overlap with each other, resulting in a drop in the power supply voltage, and eventually a decrease in the output frequency of the VCO. I will end up. On the other hand, each PLL synthesizer circuit operates in an attempt to restore its frequency.

However, the PLL synthesizer circuits in the same device do not have the same response characteristics, and even if the PLL synthesizer circuits operate with the same phase of the same reference frequency, the VCO of a certain period is Even if the control directions are the same, the control directions are not always the same during the next one cycle. That is, a certain PLL
The synthesizer circuit may be moving in the direction of increasing the output frequency of its corresponding VCO, and another PLL synthesizer circuit may be moving in the direction of decreasing the output frequency of its corresponding VCO.

Therefore, in reality, the PLL synthesizer circuits that do not have the same response characteristics compete with each other to change the load current, which causes an abnormal change in the power supply voltage of the charge pump circuit or the like or an abnormal change in the power supply voltage of the VCO. Will appear. As a result, the frequency of the output signal of the VCO may cause anomalous fluctuations within the range locked by the PLL synthesizer circuit, or even unlock.

As described above, when the frequency of the output signal fluctuates in each VCO, in the radio communication apparatus adopting the digital system, the digital modulation accuracy at the time of transmission is greatly deteriorated, This causes demodulation distortion during reception and an increase in data error rate. Therefore, from the past, V
In order to reduce the fluctuation of the power supply voltage of CO, each PLL synthesizer circuit is strengthened around its power supply and equipped with more inductance and capacitance than other circuits.

Further, in the conventional radio communication apparatus, as described above, the individual PLL synthesizer circuits are controlled in a phase-unrelated manner, and the reference frequency signals generated by the respective circuits are controlled. The phases are uneven and each PLL
It is difficult to always keep the mutual phase difference between the operating phases of the synthesizer circuit at a certain value. Therefore,
When the operation phases of two or more PLL synthesizer circuits are in the same phase or close to each other, the fluctuation of the power supply voltage caused by the phase becomes large due to the synergistic effect. Since the load current of the PLL synthesizer circuit is concentrated at the cycle of the reference frequency, it is necessary to increase the maximum allowable current value of the power supply, and in addition, it is provided to reduce the voltage fluctuation of the power supply. It is also necessary to improve the performance of the stabilizing circuit. This causes an increase in the size of a power source such as a battery and a complicated voltage stabilizing circuit.
In a conventional portable wireless communication device that uses a common battery or a set of batteries as a power source, this is a problem in manufacturing in terms of measures for downsizing the power source and stabilizing the voltage. ing.

The present invention has been made in view of the above circumstances, and provides a wireless communication device capable of improving transmission / reception performance without increasing the size of a power source such as a battery or complicating peripheral circuits. It is intended to be provided.

[0027]

In order to achieve the above object, the present invention according to claim 1 is a wireless communication device comprising two or more PLL type oscillation circuits for tuning to a transmission / reception frequency. In each oscillation circuit, an original reference frequency signal generating means for generating an original reference frequency signal serving as a reference for phase comparison, and each pulse of the original reference frequency signal generated by the original reference frequency signal generating means are distributed to different oscillation circuits. It is characterized by including a pulse distribution means for outputting.

Further, in the invention according to claim 2, when the pulse distributing means sets the number of the oscillating circuits to N, the phase difference between the reference frequency signals of the respective oscillating circuits is 360.
The feature is that it is adjusted to degrees / N.

[0029]

According to the above structure, the radio communication device according to the present invention is provided with two or more PLL type oscillation circuits for tuning to the transmission / reception frequency. Then, for each oscillation circuit, the original reference frequency signal generating means generates an original reference frequency signal as a reference for phase comparison. Further, the pulse distributing means distributes the respective pulses of the original reference frequency signal generated by the original reference frequency signal generating means to different oscillation circuits and outputs them. In this case, when the number of the oscillation circuits is N, the phase difference between the reference frequency signals of the oscillation circuits is 360 due to the pulse distributing means.
Adjusted to degrees / N.

As described above, in the wireless communication device according to the present invention, the operation phases of the respective PLL type oscillation circuits capable of synthesizing various frequencies are fixed to a constant value without overlapping. Load current is not concentrated in the oscillator circuit. Therefore, it is possible to suppress the fluctuation of the oscillation frequency of each oscillation circuit. Further, since the required permissible peak current value of the device power supply can be reduced, the power supply circuit can be further simplified, and the price of the power supply unit can be further suppressed.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 1 is a block diagram showing a circuit configuration of a wireless communication device which is a first embodiment of the present invention. This wireless communication device is a double super-heterodyne wireless communication device, and its configuration is as follows.
Reference numeral 21 is an antenna for inducing a high-frequency electric signal from the airwaves in the air and, conversely, converting it into a radiowave for radiating the high-frequency electric signals into the air, and 22 is a duplexer for using the same antenna 21 for transmission and reception. Is.

Reference numeral 23 is a transmission circuit having a function of frequency-converting the modulated intermediate frequency signal into a high frequency electric signal and further amplifying the electric power radiated into the air from the antenna 21, and 24 is a voice signal of the intermediate frequency signal. A modulation circuit that modulates a signal or a digital signal. Also, 27 is
A receiving circuit 28 amplifies the high frequency signal induced in the antenna 21 and further frequency-converts it into an intermediate frequency signal for reception. Reference numeral 28 denotes an intermediate frequency signal converted to a lower frequency for amplification, and a voice is extracted from the signal. It is a demodulation circuit having a function of extracting signals such as signals and digital signals.

Reference numeral 25 is a transmission PLL synthesizer for generating and supplying a local oscillation frequency signal necessary for determining the transmission frequency to the transmission circuit 23. Reference numeral 29 is for the reception circuit 27. Is a receiving PLL synthesizer that generates and supplies a local oscillation frequency necessary for determining
On the other hand, it is an intermediate frequency PLL circuit that generates and supplies a local oscillation frequency necessary for determining the intermediate frequency.

Reference numeral 30 is a reference frequency generating circuit for generating and supplying a reference frequency to each of the PLL synthesizers 25 and 29 and the intermediate frequency PLL circuit 26, and the reference frequency generating circuit 30-A and the reference frequency generating circuit 30-A. The reference frequency generation circuit 30-A is composed of an original reference frequency generation circuit 30-B that generates and supplies a stable original reference frequency. Here, the original reference frequency generation circuit 30-B
Is composed of, for example, a stable crystal oscillating circuit, and is set to an integral multiple of the frequency three times the reference frequency signal generated by the reference frequency generating circuit 30-A. Then, in the reference frequency generation circuit 30-A, based on the original reference frequency signal generated in the original reference frequency generation circuit 30-B, for example, the phase difference is set to 1
It is designed to generate three reference frequency signals having the same frequency kept at 20 °.

Reference numeral 31 is a power supply circuit switch for the transmission system circuit which connects or disconnects the power supply to the transmission system circuit, and 32
Is a power supply switch for the receiving system circuit that connects or disconnects the power supply to the receiving system circuit, and 33 is a power supply composed of a battery or the like. The fine opening and closing of the power supply in each circuit is performed in each circuit. Further, 34 is the PL
L synthesizers 25 and 29, and intermediate frequency PL
It is a CPU that individually controls the L circuit 26, the transmission circuit power supply switch 31 and the reception circuit power supply switch 32.

The operation of the wireless communication device having the circuit configuration described above is as follows. First, at the time of reception, a high frequency electric signal is induced in the antenna 21 by a radio wave emitted from a base station, a fixed station (or a parent station), etc., and is input to the receiving circuit 27 via the duplexer 22. The high frequency electric signal input to the reception circuit 27 is converted to an intermediate frequency signal and amplified, and then input to the demodulation circuit 28. The demodulation circuit 28 extracts a signal such as a voice signal or a digital signal from the received signal converted into the intermediate frequency signal. Further, the receiving circuit 27 and the demodulating circuit 28 are operated by being supplied with power from the power supply 33 through the power supply switch 32 for receiving system circuit only during the period of receiving the signal.

Next, at the time of transmission, the modulating circuit 24 modulates the transmitting intermediate frequency by a signal such as a voice signal or a digital signal, and the transmitting circuit 23 that follows subsequently modulates the modulated transmitting intermediate frequency signal in the air. It is converted into a carrier frequency, amplified in power, guided to the antenna 21 through the duplexer 22, converted into a radio wave by the antenna 21, and radiated into the air. Further, the transmission circuit 23 and the modulation circuit 24 are operated by being supplied with power from the power supply 33 through the transmission circuit power supply switch 31 only during the period in which signals are transmitted.

Then, the CPU 34 centrally controls the operation of each part of the apparatus, and the PLL synthesizers 25 and 2 are operated.
A data signal for determining the oscillation frequency of the internal VCO is sent to the intermediate frequency PLL circuit 26 and the intermediate frequency PLL circuit 26. The transmission PLL synthesizer 25 and the reception PLL synthesizer 29 can be controlled to perform the frequency supply operation only when power is supplied to the transmission system circuit and the reception system circuit. Further, the intermediate frequency PLL circuit 26 can also be controlled to operate only when necessary.

On the other hand, the receiving PLL synthesizer 29 is
The first local oscillation frequency signal of double superheterodyne is supplied to the receiving circuit 27, and the PLL synthesizer 25 for transmission supplies the first local oscillation frequency signal of double superheterodyne to the transmitting circuit 23. Further, the intermediate frequency PLL circuit 26 includes the modulation circuit 24.
The second local oscillation frequency signal of double superheterodyne is supplied to the demodulation circuit 28.

Further, as described above, the reference frequency generation circuit 30 has three reference frequencies of the same frequency with respect to the PLL synthesizers 25 and 29 and the intermediate frequency PLL circuit 26, each having a phase difference of 120 °. Generate and supply signals. In this case, in order to generate three reference frequency signals having the same frequency with a phase difference of 120 ° different from each other, for example, an original reference frequency signal obtained from a crystal oscillation circuit forming the original reference frequency generator 30-B is After dividing to some extent, maybe it's a 3-stage ring counter,
Alternatively, it can be obtained by passing it through another loop type counter.

Regarding the set frequency of the original reference frequency generator 30-B, in the case of the PDC system, the receiving PLL synthesizer 29 and the transmitting PLL synthesizer 2 are used.
The reference frequency signal of 5 is set to 25 KHz in order to match the radio channel interval, and the original reference frequency signal is set to 3
Since the frequency is set to an integral multiple of the double frequency, the frequency is set to an integral multiple of 75 KHz. Then, if the frequency is to be obtained in the vicinity of 12 MHz which is commonly used, 75
12.15MHz which is 162 times as high as KHz or 1 which is 168 times as high as 168 times
The frequency is set to 2.6 MHz or the like.

In the first embodiment and the second embodiment to be described later, the transmitting and receiving PLL synthesizers 25 and 29, and the intermediate frequency PLL circuit 26 are the same as those of the conventional PLL synthesizer circuit. The remaining circuit configuration excluding the provided reference frequency generation circuit is shown. As a result, when sending,
The transmitting PLL synthesizer 25, the receiving PLL synthesizer 29, and the intermediate frequency PLL synthesizer 26 operate while maintaining a phase difference of 120 ° with each other, and mutual influences via the power supply can be suppressed to a minimum. As a result, the deterioration of the modulation accuracy is close to the minimum. Further, the load fluctuation peak current value of the power supply 33 by each PLL synthesizer circuit is PL
It becomes one L synthesizer circuit, and compared with the load fluctuation peak current value of the power supply 33 when the operating phases of the three PLL synthesizers match, the load current becomes lighter by the amount of two PLL synthesizer circuits. .

Also during reception, the PLL synthesizer 29 for reception, the PLL synthesizer 25 for transmission, and the intermediate frequency PLL circuit 26 operate while maintaining a phase difference of 120 ° with each other. Mutual influences through them are suppressed close to the minimum. As a result, the data error rate and demodulation distortion rate of the demodulated signal can be suppressed close to the minimum. Further, similarly, the load fluctuation peak current value of the power source is also one of the PLL synthesizer circuits, and the power source load is light.

FIG. 2 shows the reference frequency generator 30 shown in FIG.
3 is a block diagram showing the circuit configuration of FIG. Here, one original reference frequency signal is generated by the original reference frequency generator 30-B, and three signals having a phase difference of 120 ° at the same frequency are generated by the reference frequency generation circuit 30-A. It is designed to generate a three-wave frequency division so as to be generated.
Specifically, the original reference frequency generator 30-B has 12.6.
Stable 12.6M composed of crystal oscillator with MHz setting
A frequency signal of Hz is generated and this is supplied to the reference frequency generation circuit 30-A.

Further, the reference frequency generating circuit 30-A
/ 168 frequency divider (DIVIDER) and 3 stages
Ring counter (3 JK flip flow of A, B, C)
It is composed of
Frequency signal of 12.6MHz received from Genki 30-B
Frequency signal of 75 KHz obtained by dividing the signal by 1/168
Is used as a count pulse, and this is used as three JK flip-flops.
Input to each CP terminal of rop A, B, C. As a result,
12 from the Q terminal of each JK flip-flop A, B, C
Three reference frequency signals of 25 KHz with a phase difference of 0 °
Q_A, Q_B, Q _CAre output in order, and the corresponding transmissions are sent.
PLL synthesizer 25, intermediate frequency PLL circuit 2
6, supplied to the receiving PLL synthesizer 29.

FIG. 3 is a timing chart showing the power supply voltage and its current in the wireless communication device shown in FIG. 1, the reference frequency signal in each PLL synthesizer circuit, the current consumption, and the output fluctuation of the VCO. However, each P
It is assumed that the LL synthesizer circuit cannot be turned off. Reference numeral 3-1 indicates a reference signal of the transmitting PLL synthesizer 25, reference numeral 3-2 indicates a reference signal of the intermediate frequency PLL circuit 26, and reference numeral 3-3 indicates a waveform change of the reference signal of the receiving PLL synthesizer 29. As shown in the figure, the reference frequency signals are generated with a phase difference of 120 ° from each other and do not affect each other at all.

As a result, regarding the consumption currents 3-4, 3-5 and 3-6 in the respective PLL synthesizer circuits, the output frequency fluctuations 3-7, 3-8 and 3-9 of the respective VCOs are also obtained.
Furthermore, the power supply voltage 3-A and the power supply current 3-B do not influence each other at all, and both are 1/3.
It has a waveform that changes with the cycle. FIG. 4 is a block diagram showing a circuit configuration of a wireless communication device according to a second embodiment of the present invention, which is basically the same as the circuit configuration shown in FIG. However, the configuration of the reference frequency generator 30 is different from that of the first embodiment described above, as will be described below.

FIG. 5 shows the reference frequency generator 30 shown in FIG.
3 is a block diagram showing the circuit configuration of FIG. Here, one original reference frequency signal is generated by the original reference frequency generator 30-B, and then a signal having a phase difference of 180 ° at the same frequency is divided into two waves. This is for operating the transmitting PLL frequency synthesizer 25 and the receiving PLL frequency synthesizer 29 with the same phase, and operating the intermediate frequency PLL circuit 26 with an operating phase different from them.

Specifically, the original reference frequency generator 30-B
Consists of a crystal oscillator with a 12.6MHz setting,
A stable frequency signal of 12.6 MHz is generated and supplied to the reference frequency signal generation circuit 30-A. The reference frequency generation circuit 30-A is composed of a 1/252 frequency divider (DIVIDER) and a 1/2 frequency divider composed of one JK flip-flop A.

Then, the frequency signal of 12.6 MHz received from the original reference frequency generator 30-B becomes a frequency signal of 50 KHz in the frequency division of the first stage and 25 KHz in the frequency division of the second stage. It becomes a frequency signal. Then, from the Q and notQ terminals of the JK flip-flop A, 180
The 25 kHz reference frequency signal is supplied to the transmitting PLL synthesizer 25, the receiving PLL synthesizer 29, and the intermediate frequency PLL circuit 26 with a phase difference of °.

FIG. 6 is a timing chart showing the power supply voltage and its current in the wireless communication apparatus shown in FIG. 4, the reference signal, the current consumption, and the output fluctuation of the VCO in each PLL synthesizer. Reference numeral 6-1 shows a reference frequency signal in the transmitting and receiving PLL synthesizers 25 and 29, and reference numeral 6-2 shows a waveform change of the reference frequency signal in the intermediate frequency PLL circuit 26. As shown in the figure, since the reference frequency signals are generated with a phase difference of 180 °, they do not affect each other at all.

As a result, with respect to the current consumptions 6-4 and 6-5 of the transmitting and receiving PLL synthesizers 25 and 29 and the intermediate frequency PLL circuit 26, the output frequency fluctuations 6-7 and 6 of the respective VCOs are further. -8, the power supply voltage 6-A, and the power supply currents 6-B do not affect each other at all, and in any case, the waveform changes in 1/2 cycle.

The reference signal generating circuit 30-A in the first and second embodiments may be provided in each PLL synthesizer circuit, and the operating phase of each PLL synthesizer circuit may be controlled by the CPU 34. The configuration may be controlled by software.

[0054]

According to the above-described wireless communication device of the present invention, the deterioration of the power source quality due to the operation between the plurality of PLL synthesizer circuits is eliminated, and the mutual influence when the power sources are passed through is minimized. At the time of transmission, at least the deterioration of the modulation accuracy by the PLL synthesizer circuit is suppressed to the minimum, and at the time of reception, the demodulation distortion and the data error rate at least by the PLL synthesizer circuit are suppressed to the minimum. Also,
Since the load on the power source is reduced, it is easy to reduce the size and weight of the power source, which is advantageous for reducing the size and weight of the wireless communication device.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a circuit configuration of a wireless communication device that is a first embodiment of the present invention.

2 is a block diagram showing a circuit configuration of a reference frequency generator 30 shown in FIG.

3 is a timing chart showing a power supply voltage and its current in the wireless communication device shown in FIG. 1, a reference frequency signal in each PLL synthesizer circuit, a consumption current, and an output fluctuation of a VCO.

FIG. 4 is a block diagram showing a circuit configuration of a wireless communication device according to a second embodiment of the present invention.

5 is a block diagram showing a circuit configuration of a reference frequency generator 30 shown in FIG.

6 is a timing chart showing a power supply voltage and its current in the wireless communication device shown in FIG. 4, as well as a reference frequency signal, current consumption, and VCO output fluctuation in each PLL synthesizer circuit.

FIG. 7 is a block diagram showing an example of a circuit configuration of a conventional wireless communication device.

8 is a circuit of reference frequency generation circuits 125-A, 129-A, and 126-A in the reference frequency generator 130, the transmission PLL synthesizer 125, the reception PLL synthesizer 129, and the intermediate frequency PLL circuit 126 shown in FIG. It is a block diagram which shows a structure.

9 is a timing chart showing a power supply voltage and its current in the conventional wireless communication device shown in FIG. 7, a reference frequency signal in each PLL synthesizer circuit, a consumed current, and a VCO output fluctuation.

[Explanation of symbols]

 21 antenna 22 duplexer 23 transmitter circuit 24 modulator circuit 25 transmitter PLL synthesizer 26 intermediate frequency PLL circuit 27 receiver circuit 28 demodulator circuit 29 receiver PLL synthesizer 30 reference frequency generator 31 transmitter circuit power supply switch 32 receiver system circuit Power switch 33 Power supply 34 CPU 30-A Reference frequency generation circuit 30-B Original reference frequency generator

Claims (2)

[Claims] 1. A radio communication device comprising two or more PLL type oscillation circuits for tuning to a transmission / reception frequency, wherein an original reference frequency for generating an original reference frequency signal as a reference for phase comparison in each of the oscillation circuits. A wireless communication apparatus comprising: a signal generating unit; and a pulse allocating unit that allocates each pulse of the original reference frequency signal generated by the original reference frequency signal generating unit to different oscillation circuits and outputs the pulse. 2. The pulse allocating means adjusts a phase difference between reference frequency signals of the respective oscillation circuits to 360 degrees / N, where N is the number of the oscillation circuits. Wireless communication device.