JPH07281924A - Trace device and emulator equipped with the same - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a trace device capable of acquiring bus information at the time of data access, bus information of program fetch immediately before that, and bus information of program fetch immediately before / after the instruction execution flow is changed. . [Structure] Each of the latch circuits 110 and 111 latches bus information for each instruction fetch cycle, and holds the bus information of two bus cycles by exclusively controlling the latch operation. The trigger of the exclusive latch operation is in response to the changed state of the instruction execution flow detected by the branch signal 205 and the data access state detected by the program fetch signal 206, and is latched after the exclusive latch operation is completed. Bus information is written in parallel to the trace memory 100.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trace technique for tracing bus information of a data processor for system debugging and software debugging, and more particularly to a technique effective when applied to an emulator.

[0002]

2. Description of the Related Art A trace technique for acquiring an instruction execution locus by a data processor in system debugging or software debugging is, for example, a data processor (CPU).
Of course, the bus information (various information of the address bus, the data bus, and the control bus) of a data processing device that has a CPU such as a microprocessor or a microcomputer and executes instructions is stored in a trace memory every bus cycle, After the instruction execution is interrupted, the stored bus information is analyzed, the data value and the instruction word are inversely converted and displayed for each bus cycle, and the execution locus of the program can be traced.

Bus information to be traced by the trace circuit is various information appearing on an address bus, a data bus, a control bus, etc. in association with an access of the data processor, and these are changed for each access. Therefore, if the operation speed of the data processor becomes faster, the change cycle of the bus information becomes shorter accordingly, and if all of it is to be stored in the trace memory, a high-speed and large-capacity trace memory having a memory cycle shorter than the bus cycle is required. You will need it.

Therefore, in order to obtain a program execution locus for a long time with a small trace memory capacity,
Japanese Patent Application Laid-Open No. 63-129432 discloses a technique of writing only a branch source address and a branch destination address into a trace memory only when a process for changing a flow of instruction execution such as a branch instruction or interrupt acceptance is performed. It has been proposed and a similar technique is also proposed in Japanese Patent Laid-Open No. 4-42331. In addition, Japanese Patent Laid-Open No. 3-241437 discloses a CPU
A technique has been proposed in which only the address information of (1) is stored in the trace memory, and later compared with the operating program to determine the execution locus of the program in which the CPU actually operated.

[0005]

However, the prior art only focuses on the instruction address, and does not consider efficiently obtaining the information necessary for debugging with a small memory capacity. That is, in order to analyze the program execution locus based on the limited information acquired by the trace, the bus information at the time of data read / write, the bus information of the program fetch immediately before that, and the instruction execution such as branch instruction and interrupt acceptance The present inventor has found that the bus information of the program fetch immediately before / after the flow of is changed must be acquired. The former information is at least necessary to understand the actual data access status such as operand acquisition accompanying instruction execution,
The latter information is needed to follow the program flow even if the instruction execution flow is changed.

Further, when only the predetermined bus information is stored in the trace memory as described above, in order to continuously obtain the preceding and following bus information, the high-speed access memory whose memory cycle is shorter than the bus cycle is required. You have to use it. It is still the case that a very high-speed and expensive storage device and control circuit are required for a high-speed CPU.

An object of the present invention is to provide bus information at the time of data access, bus information for program fetch immediately before that, and bus information for program fetch immediately before / after the flow of instruction execution such as branch instruction or interrupt acceptance is changed. It is to provide a trace device that can be acquired. Another object of the present invention is to provide a trace device that can acquire the bus information by using a trace memory that is slower than its changing speed. Still another object of the present invention is to provide an emulator equipped with such a tracing device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

(A) The trace device stores the bus information of the data processor temporarily for a plurality of bus cycles, the trace memory connected to the input of the buffer means, and the trace memory while referring to the bus information. Write control means for selectively controlling bus information to be stored. The write control means has a first state in which the data processor executes processing for changing the flow of instruction execution, and a second state in which data access other than instruction fetch is performed.
From the buffer means to the trace memory for the bus information including the bus information of the first instruction fetch whose execution order is changed after the first state and the bus information of the instruction fetch immediately before that. From the buffer means to the trace memory for bus information of consecutive bus cycles including the bus cycle of the data access and the instruction fetch cycle immediately before that in response to the second state. To generate a write control signal that allows parallel writing.

(B) In order to simply construct the buffer means, the bus information of the data processor is received in parallel by the plurality of latch circuits whose outputs are connected to the data input terminals of the trace memory. It constitutes a buffer means. At this time, the write control means allows the plurality of latch circuits to perform a parallel latch operation for each bus cycle of instruction fetch, and then responds to each of the first state and the second state. A latch control signal that causes the latch circuit to latch the bus information by the exclusive latch operation is generated, and after the exclusive latch operation by the latch control signal is completed, the latched bus information is written to the trace memory by the write control signal. Allow writing. The write control means is provided with a function of generating a sequentially updated write address signal when the write control signal permits writing, and a read control means for performing read control of the trace memory in the same order as the write order. Can be provided.

(C) As a more specific mode of simplifying the write control means in the above means, the trace device has a trace memory for storing bus information of the data processor and a bus information of the data processor, respectively. Two latch circuits which receive in parallel and each output of which is connected to the data input terminal of the trace memory;
First information such as a branch signal indicating a state in which the data processor executes a process that changes the flow of instruction execution,
Then, the latch control signal of the latch circuit is referred to while referring to the second information such as a program fetch signal, a read signal, and a write signal that can identify whether the current bus cycle is an instruction fetch or another data access. And write control means for generating a write control signal for the trace memory and selectively controlling bus information to be stored in the trace memory. At this time, the write control means detects the execution of an instruction that changes the instruction execution flow according to the first information after allowing the two latch circuits to perform a latch operation in parallel for each instruction fetch cycle. Sometimes, the latch operation of one latch circuit is prohibited until the end of the next instruction fetch cycle, so that the two latch circuits respectively latch the bus information of the preceding and following instruction fetches, and the data access is detected by the second information. At this time, a latch control signal is generated for prohibiting the latch operation of one latch circuit in the data access cycle to cause the two latch circuits to latch the bus information for the data access and the bus information for the previous instruction fetch. After the exclusive latch operation by the latch control signal is completed, the latched bus information is I shall write acceptable trace memory with the write control signal.

(D) The trace device mounted on the emulator is connected to the emulation bus to which the bus information of the emulation data processor for controlling the target system is supplied.

[0014]

According to the above-mentioned means (a), the buffer means capable of temporarily storing the bus information for a plurality of bus cycles is:
Regardless of whether the first state or the second state occurs, the bus information of the instruction fetches before and after the first state is temporarily held. Therefore, the write control unit detects the first state, The acquisition of bus information for instruction fetch immediately before / after a change in instruction execution flow such as a branch instruction or interrupt acceptance is realized so that the program flow can be followed even if the instruction execution flow is changed. Similarly, the write control unit realizes the acquisition of the bus information at the time of data access and the bus information of the instruction fetch immediately before that by detecting the second state, and in the analysis of the execution locus of the program, the instruction execution is accompanied. Make it possible to grasp the actual data access status such as operand acquisition. As a result, it is possible to efficiently obtain the information necessary for software debugging or system debugging with a small memory capacity.

According to the above-mentioned means (b), each of the plurality of latch circuits latches the bus information at every instruction fetch cycle, and the latch operation is exclusively controlled, so that the number of the latch circuits as a whole is increased. Holds bus information about the number of bus cycles. The trigger for the exclusive latch operation is the first one above.
And the second state, all of the latched bus information is written in parallel to the trace memory after the completion of the exclusive latch operation. This enables writing of a plurality of pieces of bus information even if the access speed of the trace memory is lower than the bus cycle. In the write cycle of the trace memory, in order to hold the above bus information in the latch circuit, the latch operation of the latch circuit may be stopped during that period, and the trace memory is provided with an input latch circuit for write data. If so, it is not necessary. The number of latch circuits is determined according to the number of bus cycles of bus information to be continuously acquired, and the above-mentioned means (c) is the case of the minimum number of two bus cycles.

According to the above-mentioned means (c), the information used as the trigger of the exclusive latch operation for the two latch circuits, that is, the first information such as the branch signal,
The second information such as the program fetch signal, the read signal, and the write signal is the information included in the bus information output by the data processor, and thus the second information is directly used to perform the exclusive latch operation of the two latch circuits. The logic configuration of the write control means for controlling is significantly simplified.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a trace device according to an embodiment of the present invention. In the figure, 1 is a trace device, 2 is a computer system, 3 is a decoding unit, 4 is an auxiliary storage device, and 5 is a display device.

In the computer system 2, a CPU 201 and a storage device 202 connected to the bus 200 are typically shown. The storage device 202 is to be understood as a general term for storage means that stores an operation program of the CPU 201 and various data necessary for execution of the program and serves as a work area of the CPU 201. The auxiliary storage device 4 stores a source program and an object program corresponding to the operation program to be executed by the CPU 201. The object program stored in the auxiliary storage device 4 may be downloaded as the operation program stored in the storage device 202.

The bus 200 includes an address bus, a data bus, and a control bus (not shown). The information exchanged on these buses 200 is bus information. In the bus information, the read signal 203, the write signal 204, and the branch signal 20 output by the CPU 201 are included.
5 and a program fetch signal 206. The read signal 203 is a signal instructing the CPU 201 to read information from the outside, and the write signal 204 is a signal instructing the CPU 201 to write information to the outside. The branch signal 205 is a signal for notifying externally that the flow of instruction execution such as branch instruction or interrupt acceptance is changed, and the process for changing the flow of instruction execution is actually CP.
A signal that is changed to an active level when the U 201 performs (execution of a branch instruction or execution of processing for accepting an interrupt), and the program fetch signal 206 is a signal that indicates a bus cycle for instruction fetch.

The trace device 1 uses the read signal 20 described above.
3, the bus information appearing on the bus 200 of the CPU 201 is selectively stored in bus cycle units according to the states of the write signal 204, the branch signal 205, and the program fetch signal 206. The details will be described later.

The decoding unit 3 decodes / edits the information read from the trace device 1 and sends it to the display device 5.
For example, the decoding unit 3 sequentially receives the information read from the trace device 1, determines whether the information is information related to program fetch or data access other than an instruction, and edits the bus information according to the information. The contents are displayed on the display device 5 in order. The program fetch is displayed by disassembling or separately capturing the object program output by a language processing program such as a compiler and using the file name information of the source program included in the object program and the address information for each source line The source line in the source program file corresponding to the fetch address can be fetched, edited, and displayed.

The trace device 1 comprises a trace memory 1
00, latch circuits 110 and 111, write control circuit 12
0, and a read control circuit 130. The trace memory 100 is a memory for storing bus information of the CPU 201. The latch circuits 110 and 111 are the CPU 201.
Of bus information of the CPU 201 are received in parallel, and their outputs are connected to the data input terminal of the trace memory 100. The write control circuit 120 refers to the read signal 203, the write signal 204, the branch signal 205, and the program fetch signal 206 output from the CPU 201, and the latch control signals 121 and 122 of the latch circuits 110 and 111 and the write control signal for the trace memory 100. 123 and the write address signal 124 are generated to selectively control the bus information to be stored in the trace memory 100. The read control circuit 130 generates a read control signal 131 and a read address signal 132 for controlling the read of the trace memory 100 in the same order as the write order.

The write control circuit 120 uses the latch control signals 121 and 122 to generate two latch circuits 11.
For 0 and 111, parallel latch operation is permitted for each instruction fetch cycle of the CPU 201. After that, when it is detected by the branch signal 205 that the program execution order is changed in the next instruction fetch cycle, one latch circuit 1 until the end of the next instruction fetch cycle.
By prohibiting the latch operation of 10, the two latch circuits 110 and 111 are made to latch the bus information of the preceding and following instruction fetches respectively, and the program fetch signal 20
6, when the data access other than the instruction is detected by the read signal 203 and the write signal 204, the latch operation of one of the latch circuits 110 is prohibited in the bus cycle, so that the two latch circuits 110 and 111 can be accessed. The bus information and the bus information of the instruction fetch immediately before that are latched. Then, after the exclusive latch operation by the latch control signals 121 and 122 is completed, the write control circuit 120 gives the write control signal 123 and the write address signal 124 to the trace memory 100, and the two buses latched by the latch circuits 110 and 111. Cycle information of the bus for one cycle is collectively or continuously provided.
Perform control to write to 0. According to this embodiment,
During the write operation to the trace memory 100, the latch operation of both latch circuits 110 and 111 is prohibited.
The inhibition period of the latch operation is a plurality of bus cycle periods of the CPU 201, which is equal to or longer than the memory cycle of the trace memory 100, and is determined in advance. If another data latch circuit is provided in the data input stage of the trace memory 100, such a latch operation need not be prohibited.

The latch timing by the latch control signals 121 and 122 is the timing at which all the bus information is fixed on the bus 200. For example, in the read cycle, the change timing of the read signal 203 to the active level (for example, low level). It is performed after being delayed for a predetermined time in synchronism with, and in the write cycle, after being delayed for a predetermined time in synchronization with the change timing of the write signal 204 to the active level (for example, low level).

FIG. 2 shows a timing chart of an example of the write operation to the trace memory 100. The bus cycles 1 to 7 shown in the figure are program fetch (also referred to as instruction fetch) cycles, and the bus cycle 8 is a data write bus cycle. The instruction is not limited to a word length that can be fetched in a single bus cycle, and may require a plurality of bus cycles. According to this example, the bus cycle 3 is the start instruction address (11) of the processing routine branched by the branch instruction.
This is an instruction fetch cycle for address 00). The branch signal 205 is set to an active low level when the branch instruction is executed. For example, if the branch instruction consists of multiple words and the last word is fetched with the first word already fetched being decoded,
The branch signal 205 is activated in parallel with the fetch of the final word. Further, when a prefetched branch instruction is being processed in the instruction decode stage of the pipeline stage, if a prefetch of another instruction is activated in the bus cycle 2 in parallel with this, a branch signal is issued in parallel with it. 205 is activated.

FIG. 2 shows the latch control signals 121 and 12 described above.
2 is not shown. Instead, a fetch permission signal 121P of the latch circuit 110 and a fetch permission signal 122P of the latch circuit 111 are shown. Those acquisition permission signals 12
It should be understood that 1P and 122P are internal control signals of the write control circuit 120. The write control circuit 120 reads the read signal 203 and the write signal 2 when the write enable signals 121P and 122P are at the active level (for example, low level).
The latch control signals 121 and 122 are changed in clock in synchronization with the timing at which all the bus information is determined in synchronization with 04 (the timing delayed from the change of the read signal 203 or the write signal 204 to the active level for a predetermined time). Let As a result, the latch circuits 110 and 111 perform the latch operation.

According to FIG. 2, when the write control circuit 120 detects that the branch signal 205 has been changed from the low level to the high level (bus cycle 2), the latch circuit 110 for the next bus cycle 3 for, for example, 4 cycles. The capture permission signal 121P is controlled to an inactive high level to permit only the latch operation of the latch circuit 111. afterwards,
The write control circuit 120 responds to the change of the capture enable signal 121P to the inactive level, and responds to the latch circuit 111.
The latch enable signal 122P is also controlled to an inactive high level, and the latch circuit 110 and the latch circuit 111 inhibit the latch operation until the bus cycle 6. In addition, the write control circuit 120 uses the program fetch signal 2
When it is detected that 06 is set to the inactive high level (bus cycle 8), the fetch enable signal 121P of the latch circuit 110 is controlled to the inactive high level for four cycles from the bus cycle in the same manner as described above. Only the latch operation of the latch circuit 111 is permitted. After that, the write control circuit 120 also controls the capture enable signal 122P of the latch circuit 111 to be an inactive high level to inhibit the latch operation of the latch circuit 111 together with the latch circuit 110.

In this way, the exclusive latch operation is performed in the bus cycles 2 and 3 and the bus cycles 7 and 8. As a result, at the start of the bus cycle 4, the latch circuit 110 holds all the bus information about the instruction fetch in the bus cycle 2, and the latch circuit 111 holds all the bus information about the fetch of the first instruction of the branch destination routine. To be done. The write control circuit 120 is the latch circuit 11
The write control signal 123 and the updated write address signal 124 are supplied to the trace memory 100 during the period from the bus cycle 4 to the bus cycle 6 in which the latch operation of 1 is prohibited, and all the buses held by the latch circuits 110 and 111. Information is controlled to be written in the trace memory in parallel during the period. Similarly, at the end of the bus cycle 8, the latch circuit 111 holds all the bus information related to the data write, and the latch circuit 110 holds the immediately preceding instruction fetch, that is, all the bus information of the instruction fetch in the bus cycle 7. Retained. After that, the write control circuit 12
0 supplies the write control signal 123 and the updated write address signal 124 to the trace memory 100 during the period in which the latch operation of both the latch circuits 110 and 111 is prohibited, and all the buses held by the latch circuits 110 and 111. Information is controlled to be written in the trace memory in parallel during the period. According to the example of FIG. 2, the trace memory 100 has a CP
Even a low-speed memory having a write cycle three times as large as the bus cycle of U201 can store bus information for two consecutive bus cycles in the trace memory 100.

In FIG. 3, the entire control modes (modes) by the write control circuit 120 are classified and shown. No in FIG.
The numbers described in the columns of No. are shown in FIG. 2 to n
o. 4, no. 6, no. Corresponding to 7.

No. 1 in FIG. As shown in FIG. 2, the latch operation of both latch circuits 110 and 111 is permitted in the case of program fetch.

No. 1 in FIG. As indicated by 3, the read / write of data that is not a program fetch prohibits the latch operation of one latch circuit 110 because it is not a program fetch, and the latch circuit 111 latches the bus information. Then, both latch circuits 110, 11
1 take-in permission signals 121P and 122P are off (off)
The state is made inactive, that is, the data held in the latch circuits 110 and 111 is written in the trace memory 100 during that period. After writing, both capture enable signals 121P,
122P is returned to the on state or active.

No. 1 in FIG. In the cycle in which the branch instruction is executed and the program fetch is performed as indicated by 4, the branch signal 205 and the program fetch signal 2
06 is activated and both latch circuits 110, 1
11 latches the bus information of the program fetch,
After that, the acquisition permission signal 121P of the latch circuit 110 is set to the inactive off state. The cycle in which the branch instruction is executed and the program is fetched is, for example, a case where the instruction itself fetched in the bus cycle is the last word of the branch instruction and the first word thereof is executed, prefetch or pipeline. In some cases, a branch instruction that has already been fetched may be executed by executing a specific instruction.

No. 1 in FIG. 5 shows a cycle in which a branch instruction is executed and data is read / written other than program fetch. Such a cycle is a case where the data read / write access of another pipeline stage is performed first when the prefetched branch instruction is executed. The fetch cycle of the branch destination instruction will be activated after that. no. The state of No. 5 is no. 3 and no. Although the states of 4 are in conflict with each other, the bus information of the instruction fetch cycle of the subsequent branch destination is preferentially traceable. That is, in this state, the branch signal 205 is made active, but the program fetch signal 206 is made inactive, so that one latch circuit 11
For 0, the latch operation is prohibited, and only the latch circuit 111 is latched. After that, the acquisition permission signal 121P of the one latch circuit 110 is maintained in the off state. That is,
This is to allow the latch circuit 110 to maintain the bus information of the instruction fetch that was latched before that, and to allow the latch circuit 111 to later latch the bus information of the instruction fetch cycle of the branch destination.

No. 1 in FIG. 6 is no. 4 or no. This is processing when a bus cycle of program fetch occurs after 5. In this case, the bus information is latched in the latch circuit 111. Then, both latch circuits 1
The capture enable signals 121P and 122P of 10, 111 are turned off, and the latch circuit 110,
The held data of 111 is written in the trace memory 100. After writing, both capture enable signals 121P and 122P
Is turned back on.

In the modes other than the above, the writing operation to the trace memory 100 is in progress. If no. Three
no. 4, no. When the state 5 occurs, the trace operation corresponding to the state 5 is not performed, but if such a state does not continue frequently, if the state is interpolated by referring to the program, the execution trajectory of the program is followed. There is no practical problem.

By repeatedly executing the processing shown in FIG. 3, among the program operations executed by the CPU 201, the bus information of the instruction fetch immediately before the data read / write and the bus information of the data read / write are executed. The bus information of the program fetch immediately before the execution order of the program is changed and the bus information of the instruction fetch immediately after that are accumulated in the trace memory 100 according to the execution order of the program. If the data read / write and the branch overlap, no. As indicated by 5, the trace of the bus information regarding the processing of the branch has priority. Incidentally, no. Reference numeral 1 denotes an initial state in which the latch enable signals 121P and 122P of the latch circuits 110 and 111 are turned on.

Next, the read operation of the bus information accumulated in the trace memory 100 and the decoding of the information are performed to CP.
A process of editing and displaying the execution result of U201 will be described.

The read control circuit 130 reads the bus information read control signal 131 and read address signal 132.
It is generated and the bus information is read from the trace memory 100 in the same order as the writing order. The read bus information is supplied to the decoding unit 3. The decoding unit 3 determines whether the information is bus information related to program fetch or bus access such as data read / write, edits the bus information according to the information, and sequentially displays the contents on the display device 5. indicate. The program fetch is displayed by disassembling, or a separate object program output by a language processing program such as a compiler is fetched from the auxiliary storage device 4, and the file name information and the source line of the source program included in the object program are stored. The source line in the source program file corresponding to the program fetch address is fetched from the address information, edited, and displayed. Because the instruction fetch address immediately before the branch and the instruction fetch address immediately after the branch can be acquired in the trace information, the source line that is not acquired in the trace memory can be displayed by displaying the source lines in the range immediately after the branch to immediately before the branch. Can display program lines. For data read / write, a valid control signal is edited and displayed. In the display example on the display device 5 of FIG. 1, the line marked with * is the description line of the source code, and the instruction address and the object code are displayed below it.

FIG. 4 shows an emulator to which the tracing device 1 is applied. Emulator 6 shown in FIG.
Is connected between a host system 7 such as a parent computer and a microcomputer system (also referred to as a target system) 8 as an embedded device to be debugged, and a target microcomputer that should originally control the target system 8. While substituting the function of, it has a function as a debugger and supports detailed system evaluation and program debugging. The host system 7 and the emulator 6 are connected by a serial line 71 or the like, for example. The target system 8 and the emulator 6 are connected by an interface cable 81. That is, the tip of the interface cable 81 is coupled to the target microcomputer socket 80 of the target system 8 so that the emulator 6 controls the target system 8 on its behalf. Emulator 6
And the host system 7 constitutes a debug tool.

The emulator 6 is not particularly limited, but controls the entire emulator such as the emulation data processor 60 for substituting the function of the target microcomputer which should originally control the target system 8 and the condition setting for emulation. A control data processor 61 for controlling is provided. The emulation data processor 60 is coupled to an emulation bus 62, the control data processor 61 is coupled to a control bus 63, and both buses 62 and 63 have an emulation control circuit 64,
The break control circuit 65, the trace device 1, and the proxy memory circuit 67 are connected to each other. The emulation data processor 60 stores addresses and data exchanged with the target system 8 while executing the target program developed for the target system 8 or executing the target program to control the target system 8 on behalf of the target system 8. Various bus information and control signals are also given to the emulation bus 62. The information thus provided is traced by the tracing device 1 according to the present invention in accordance with the bus cycle of the emulation data processor 60 as described above. In addition,
The control circuit 65 stores the desired instruction address as break address information (break condition) in order to suspend the execution of the target program by the emulation data processor at the desired instruction address, for example. The break control circuit 65 monitors the state of the emulation bus 62, and executes control for stopping the emulation operation when the execution of the target program reaches a preset break address (break condition). The proxy memory circuit 67 is
It is used as a storage area for supplementing a memory not yet prepared in the target system 8 and a storage area for the target program. The control data processor 61 carries out setting of various conditions such as setting of break conditions for the break control circuit 65 and setting of a trace start address for the trace device 1 and initial setting via the control bus 63. When the emulation operation is stopped by the break control circuit 65,
The trace information held by the trace device 1 is read to the control bus 63, and the read information is transferred by the control processor 61 to the host system 7 through the host interface 68. The host system 7 supports debugging by displaying the transferred trace information and analyzing it. In this embodiment, the decoding unit 3, the auxiliary storage device 4, and the display device 5 shown in FIG. 1 are provided in the host system 7. The read control circuit 130 may be realized by the control data processor 61.

According to the above embodiment, there are the following effects. (1) Since the write control circuit 120 is provided with the pair of latch circuits 110 and 111 capable of temporarily storing bus information for a plurality of bus cycles, the write control circuit 120 executes an instruction flow such as a branch instruction or interrupt acceptance based on the branch signal 205. Is fetched into the pair of latch circuits 110 and 111 immediately before / after the change of the instruction, and writing to the trace memory 100 is realized in parallel, and the program is executed even when the instruction execution flow is changed. Can be followed. Similarly, the write control circuit 120 fetches the bus information at the time of data access and the bus information of the instruction fetch immediately before that into the pair of latch circuits 110 and 111 based on the program fetch signal 206 and the like, and writes it to the trace memory 100. In order to analyze the execution locus of the program, it is possible to grasp the actual data access status such as operand acquisition associated with instruction execution. As a result, it is possible to efficiently obtain the information necessary for software debugging or system debugging with a small memory capacity. When the bus information of the instruction fetch just before / after the change of the instruction execution flow such as the branch instruction or the interrupt acceptance is fetched into the pair of latch circuits 110 and 111, the bus information regarding the first instruction fetch at the branch destination is surely obtained. Even if the bus information related to the instruction fetch immediately before that is not a branch instruction, the branch instruction can be tracked by referring to the source program or object program description and the pipeline stage number or prefetch stage number, etc. . Similarly, when the bus information at the time of data access and the bus information of the instruction fetch immediately before that are fetched into the pair of latch circuits 110 and 111, the instruction that caused the data access is fetched in the instruction fetch cycle immediately before that. Even if the instruction does not exist, the instruction that started the corresponding data access can be specified from the bus information of the instruction fetch immediately before by referring to the number of pipeline stages or the number of prefetch stages along with the description of the source program or the object program.

(2) Each of the latch circuits 110 and 111 latches the bus information for each instruction fetch cycle, and the latch operation is exclusively controlled to hold the bus information of two bus cycles as a whole. . The exclusive latch operation is triggered in response to each of the first state in which the flow of instruction execution such as branch instruction execution and interrupt acceptance is changed and the second state in which data access other than instruction fetch is performed, and the exclusive latch operation is performed. After the completion of the latch operation, all the bus information latched is parallel to the trace memory 100.
Written in. Therefore, a plurality of pieces of bus information can be written even if the access speed of the trace memory 100 is slower than the bus cycle.

(3) Information used as a trigger for exclusive latch operation for the two latch circuits 110 and 111, that is, set to an active level in synchronization with execution of a branch instruction or execution of interrupt acceptance processing. First information, such as branch signal 205, and program fetch signal 20
6, the second information such as the read signal 203 and the write signal 204 is the information included in the bus information output by the CPU 201, and thus is directly used to exclusively latch the two latch circuits 110 and 111. The logical configuration of the write control circuit 120 that controls the operation can be significantly simplified. That is, after the latch operation of both latch circuits 110 and 111 is permitted in the instruction fetch cycle, the branch signal 205
In the bus cycle after the detection of the first state indicated by, the latch operation of the latch circuit 110 is prohibited until the instruction fetch cycle immediately after that is detected, and the data access cycle indicated by the program fetch signal 206 or the like. Then, the latch operation of the latch circuit 110 is prohibited, and the bus information at the time of data read / write, which is important information for debugging the program, the bus information of the program fetch immediately before that, and the execution order of the program are stored in each latch circuit. The bus information of the program fetch immediately before / after the change can be latched.

(4) During the write operation to the trace memory 100, the write control circuit 120 inhibits the latch operation of the latch circuit during that period to prevent the bus information from being rewritten, so the write operation to the trace memory is performed. A data input latch circuit or the like need not be specially provided.

(5) As described above, the bus information at the time of data read / write, which is important information for program debugging, the bus information of the program fetch immediately before that, and the program information immediately before / after the program execution order changes. Since only the bus information can be stored in the trace memory 100 at a writing speed that is less than or equal to the speed at which the bus information changes, even if the CPU 201 operates at a high speed, it can be replaced with a very high speed / expensive trace memory and a low speed. / Inexpensive trace memory can be used.

(6) The emulator 6 to which the trace device 1 is applied can enable debugging of a target system to which a high speed data processor is applied. Also, the cost of such an emulator can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes. For example,
The detection of the first state is not limited to the case of using the branch signal output from the CPU, but may be detected by the discontinuous state of the instruction fetch address. The second state is the CPU
However, the address on the address bus may be detected by comparing it with the address assigned to the instruction memory. Further, the latch circuit may have three or more stages, which is limited to two stages, but the control becomes complicated accordingly. Further, the buffer means such as the latch circuit is not limited to the case where it is configured by a static latch circuit such as a flip-flop.

The present invention can be applied to a bus trace device, an emulator, a bus analyzer and the like.

[0049]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the bus information at the time of data access, the bus information of the program fetch immediately before that, and the bus information of the program fetch immediately before / after the flow of instruction execution such as branch instruction and interrupt acceptance are changed can be acquired. The bus information can be obtained by using the trace memory which is slower than the changing speed, and the cost of the trace device can be reduced. Information used as a trigger for an exclusive latch operation for two latch circuits, that is, first information such as a branch signal that is set to an active level in synchronization with execution of a branch instruction or execution of interrupt acceptance processing, The second information such as the program fetch signal is the information included in the bus information output by the data processor,
By directly utilizing this, the logical configuration of the write control means for controlling the exclusive latch operation of the two latch circuits can be remarkably simplified. During the write operation to the trace memory, the write control means prohibits the latch operation of the latch circuit during that period to prevent the bus information from being rewritten.
It is not necessary to specially provide a write data input latch circuit or the like in the trace memory. An emulator that uses a trace device can enable debugging of a target system that uses a high-speed data processor. Also, the cost of such an emulator can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a trace device according to an embodiment of the present invention.

FIG. 2 is a timing chart of an example of a write operation to a trace memory.

FIG. 3 is an explanatory diagram showing classified control modes by the write control circuit.

4 is a block diagram of an embodiment of an emulator to which the trace device of FIG. 1 is applied.

[Explanation of symbols]

 1 Trace device 100 Trace memory 110,111 Latch circuit 120 Write control circuit 121,122 Latch control signal 121P, 122P Acquisition permission signal 123 Write control signal 124 Write address signal 130 Read control circuit 131 Read control signal 132 Read address signal 2 Computer System 200 Bus 201 CPU 202 Storage device 203 Read signal 204 Write signal 205 Branch signal 206 Program fetch signal 3 Decoding section 6 Emulator 60 Emulation data processor 62 Emulation bus

Claims (6)

[Claims] 1. A buffer means capable of temporarily storing bus information of a data processor for a plurality of bus cycles, a trace memory having an input connected to the buffer means, and a trace memory for storing the trace information while referring to the bus information. Write control means for selectively controlling bus information to be used, wherein the write control means has a first state in which the data processor executes processing for changing the flow of instruction execution, and a data access other than instruction fetch. 2 state is detected, and the bus information including the bus information of the first instruction fetch whose execution order is changed after the first state and the bus information of the instruction fetch immediately before the first state is traced from the buffer means to the trace memory. Parallel writing to the
In response to the above state, a write control signal that allows parallel writing from the buffer means to the trace memory is generated for the bus information of the bus cycle including the bus cycle of the data access and the instruction fetch cycle immediately before that. A tracing device characterized by being a thing. 2. The buffer means comprises a plurality of latch circuits, each of which receives bus information of a data processor in parallel, each output of which is connected to a data input terminal of the trace memory, and the write control means. Excludes a plurality of latch circuits in response to each of the first state and the second state after allowing a parallel latch operation for each bus cycle of instruction fetch for the plurality of latch circuits. A latch control signal for latching the bus information by latching the bus information, and after the exclusive latch operation by the latch control signal is completed, the latched bus information is allowed to be written in the trace memory by the write control signal. The tracing apparatus according to claim 1, wherein the tracing apparatus is a thing. 3. A trace memory for storing bus information of a data processor, and two trace memories each of which receives the bus information of the data processor in parallel and each output of which is connected to a data input terminal of the trace memory. And the first information indicating the state in which the data processor executes the processing that changes the flow of instruction execution, and whether the current bus cycle is instruction fetch or other data access can be identified. Write control means for generating a latch control signal of the latch circuit and a write control signal for the trace memory while referring to the second information, and selectively controlling bus information to be stored in the trace memory. Allows the two latch circuits to perform a latch operation in parallel every instruction fetch cycle, and then When the execution of an instruction that changes the flow of instruction execution is detected by the information, the latch operation of one latch circuit is prohibited until the end of the next instruction fetch cycle, so that the two latch circuits are provided with a bus for fetching instructions before and after, respectively. Information is latched, and when the data access is detected by the second information, the latch operation of one of the latch circuits is prohibited in the data access cycle, so that the bus information of the data access and the bus information of that A latch control signal for latching the bus information of the immediately preceding instruction fetch is generated, and after the exclusive latch operation by the latch control signal is completed, the latched bus information is allowed to be written in the trace memory by the write control signal. A tracing device characterized by: 4. The write control means inhibits the latch operation of all the latch circuits over a plurality of bus cycles from the write permission of the bus information to the trace memory by the write control signal to the completion thereof, and then the parallel latch operation. The trace device according to claim 2, wherein the trace device is restarted. 5. The write control means according to claim 1, wherein when the write control signal permits writing, the write control signal generates a sequentially updated write address signal. Trace device. 6. An emulation bus to which bus information of an emulation data processor for controlling the target system is supplied, and a trace device according to claim 1, which is connected to the emulation bus. An emulator characterized by comprising: